NR LDPC With Interleaver

Abstract

Concepts and schemes pertaining to information coding for mobile communications are described. A processor of an apparatus encodes data to provide encoded data. The processor also transmits the encoded data to a network node of a wireless network. In encoding the data, the processor encodes the data with a low-density parity-check (LDPC) code to provide LDPC-coded data. Moreover, the processor processes the LDPC-coded data with a forward error correction (FEC) robustness enhancement function to provide the encoded data. The FEC robustness enhancement function includes an interleaving function that interleaves the LDPC-coded data to provide the encoded data, an interlacing function that interlaces the LDPC-coded data to provide the encoded data, or a bit-reordering function that reorders bits of the LDPC-coded data to provide the encoded data.

Claims

1. A method, comprising: encoding, by a processor of an apparatus, data to provide encoded data, the encoding comprising: encoding the data with a low-density parity-check (LDPC) code to provide LDPC-coded data; and processing the LDPC-coded data with a forward error correction (FEC) robustness enhancement function to provide the encoded data; and transmitting, by the processor, the encoded data to a network node of a wireless network.

2. The method of claim 1, wherein the FEC robustness enhancement function comprises an interleaving function that interleaves the LDPC-coded data to provide the encoded data.

3. The method of claim 2, wherein the interleaving function interleaves the LDPC-coded data with a pseudo-random interleaver.

4. The method of claim 1, wherein the FEC robustness enhancement function comprises an interlacing function that interlaces the LDPC-coded data to provide the encoded data.

5. The method of claim 1, wherein the FEC robustness enhancement function comprises a bit-reordering function that reorders bits of the LDPC-coded data to provide the encoded data.

6. The method of claim 5, wherein the bit-reordering function is code rate-dependent.

7. The method of claim 5, wherein the bit-reordering function is code rate-independent.

8. The method of claim 1, wherein the wireless network comprises a 5.sup.th Generation (5G) New Radio (NR) network.

9. A method, comprising: receiving, by a processor of an apparatus, encoded data from a network node of a wireless network; and decoding, by the processor, the encoded data to provide decoded data, the decoding comprising: processing the encoded data with a forward error correction (FEC) robustness enhancement function to provide processed data; and decoding the processed data with a low-density parity-check (LDPC) code to provide the decoded data.

10. The method of claim 9, wherein the FEC robustness enhancement function comprises a de-interleaving function that de-interleaves the encoded data to provide the processed data.

11. The method of claim 10, wherein the de-interleaving function de-interleaves the encoded data with a pseudo-random de-interleaver.

12. The method of claim 9, wherein the FEC robustness enhancement function comprises a de-interlacing function that de-interlaces the encoded data to provide the processed data.

13. The method of claim 9, wherein the FEC robustness enhancement function comprises a bit-reordering function that reorders bits of the encoded data to provide the processed data.

14. The method of claim 13, wherein the bit-reordering function is code rate-dependent.

15. The method of claim 13, wherein the bit-reordering function is code rate-independent.

16. The method of claim 9, wherein the wireless network comprises a 5.sup.th Generation (5G) New Radio (NR) network.

17. An apparatus, comprising: a transceiver capable of wireless communications with at least one network node of a wireless network; and a processor coupled to the transceiver, the processor comprising: an encoder capable of encoding first data to provide encoded data by performing operations comprising: encoding the first data with a low-density parity-check (LDPC) code to provide LDPC-coded data; and processing the LDPC-coded data with a first forward error correction (FEC) robustness enhancement function to provide the encoded data.

18. The apparatus of claim 17, wherein the first FEC robustness enhancement function comprises one of: an interleaving function that interleaves the LDPC-coded data to provide the encoded data; an interlacing function that interlaces the LDPC-coded data to provide the encoded data; or a bit-reordering function that reorders bits of the LDPC-coded data to provide the encoded data.

19. The apparatus of claim 17, wherein the processor further comprises: a decoder capable of decoding second data to provide decoded data by performing operations comprising: processing the second data with a second FEC robustness enhancement function to provide processed data; and decoding the processed data with the LDPC code to provide the decoded data.

20. The apparatus of claim 19, wherein the second FEC robustness enhancement function comprises one of: a de-interleaving function that de-interleaves the second data to provide the processed data; a de-interlacing function that de-interlaces the second data to provide the processed data; or a bit-reordering function that reorders bits of the second data to provide the processed data.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of the present disclosure. The drawings illustrate implementations of the disclosure and, together with the description, serve to explain the principles of the disclosure. It is appreciable that the drawings are not necessarily in scale as some components may be shown to be out of proportion than the size in actual implementation in order to clearly illustrate the concept of the present disclosure.

[0012] FIG. 1 illustrates an example encoder architecture and an example decoder architecture in accordance with an implementation of the present disclosure.

[0013] FIG. 2 is a diagram of an example base matrix for LDPC code in accordance with an implementation of the present disclosure.

[0014] FIG. 3 is a block diagram of an example apparatus in accordance with an implementation of the present disclosure.

[0015] FIG. 4 is a flowchart of an example process in accordance with an implementation of the present disclosure.

[0016] FIG. 5 is a flowchart of an example process in accordance with an implementation of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED IMPLEMENTATIONS

[0017] Detailed embodiments and implementations of the claimed subject matters are disclosed herein. However, it shall be understood that the disclosed embodiments and implementations are merely illustrative of the claimed subject matters which may be embodied in various forms. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments and implementations set forth herein. Rather, these exemplary embodiments and implementations are provided so that description of the present disclosure is thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. In the description below, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.

Overview

[0018] Under the proposed concepts and schemes in accordance with the present disclosure, NR LDPC code block may include an interleaving function, an interlacing function, or a bit-reordering function to achieve improved performance. That is, a LDPC code with an interleaving function, an interlacing function, or a bit-reordering function may mitigate effects of burst interference as well as noise from high-priority channels.

[0019] FIG. 1 illustrates an example encoder architecture 100 and an example decoder architecture 150 in accordance with an implementation of the present disclosure. Referring to FIG. 1, encoder architecture 100 may include an LDPC encoder block 110 and a first forward error correction (FEC) robustness enhancement block 120. LDPC encoder block 110 may be configured, designed or otherwise adapted to perform LDPC encoding. First FEC robustness enhancement block 120 may be configured, designed or otherwise adapted to provide an interleaving function, an interlacing function, or a bit-reordering function. Each of encoder block 110 and first FEC robustness enhancement block 120 may be implemented by hardware, software or a combination of hardware and software.

[0020] Additionally, referring to FIG. 1, decoder architecture 150 may include a second FEC robustness enhancement block 160 and an LDPC decoder block 170. Second FEC robustness enhancement block 160 may be configured, designed or otherwise adapted to provide a de-interleaving function, a de-interlacing function, or a bit-reordering function. LDPC decoder block 170 may be configured, designed or otherwise adapted to perform LDPC decoding. Each of second FEC robustness enhancement block 160 and LDPC decoder block 170 may be implemented by hardware, software or a combination of hardware and software.

[0021] Under the proposed concepts and schemes, NR LDPC may support HARQ-IR. In particular, a raptor-like structure may be utilized to extend the parity bits for HARQ-IR. FIG. 2 illustrates an example base matrix 200 for LDPC code in accordance with an implementation of the present disclosure. For base matrix 200 of dimensions MN with K information bits and N=K+M, the base matrix may be mathematically expressed as follows:

[00001]$\begin{array}{c}{H}_{MN}=.Math.\left[\begin{array}{ccc}{A}_{LK}& C_{LL}& 0_{L\left(M-L\right)}\\ B_{\left(M-L\right)K}& D_{\left(M-L\right)K}& I_{\left(M-L\right)\left(M-L\right)}\end{array}\right]\\ =.Math.\left[\begin{array}{cccccc}{s}_1& \mathrm{.Math.}& s_K& p_1& \mathrm{.Math.}& p_M\end{array}\right]\end{array}$

[0022] Here, s.sub.i denotes column vector related to systematic bit with dimension M1, and p.sub.i denotes column vector related to parity bit with dimension M1. As an example, the utilization of a bit-reordering function with the base matrix may be mathematically expressed as follows:

H.sub.MN.Math..sub.reorder

[0023] Accordingly, by using an interleaver with NR LDPC, which may be a pseudo-random interleaver, data loss may be spread out through fading. Moreover, correlations in related data streams may be broken up. Moreover, it may also be overblown for this particular usage as LDPC codes inherently do not have bit-ordering properties that would result in correlated data.

[0024] Under the proposed concepts and schemes, a full interleaver of systematic bits and parity bits may be mathematically as follows:

[00002]$\left[\begin{array}{cccccc}{s}_{11}& \mathrm{.Math.}& s_{1.Math.K}& p_{11}& \mathrm{.Math.}& p_{1.Math.M}\\ s_{21}& \mathrm{.Math.}& s_{2.Math.K}& p_{21}& & p_{2.Math.M}\\ \mathrm{.Math.}& & \mathrm{.Math.}& \mathrm{.Math.}& & \mathrm{.Math.}\\ s_{M.Math..Math.1}& \mathrm{.Math.}& s_{\mathrm{MK}}& p_{M.Math..Math.1}& \mathrm{.Math.}& p_{M.Math..Math.M}\end{array}\right].Math.{}_{\mathrm{full}-\mathrm{interleaver}}=\left[\begin{array}{cccccc}{s}_{11}& p_{11}& s_{12}& p_{12}& s_{13}& \mathrm{.Math.}\\ s_{21}& s_{22}& p_{21}& s_{23}& p_{22}& \mathrm{.Math.}\\ \mathrm{.Math.}& & \mathrm{.Math.}& \mathrm{.Math.}& & \mathrm{.Math.}\\ s_{M.Math..Math.1}& p_{M.Math..Math.1}& P_{M.Math..Math.2}& s_{M.Math..Math.2}& p_{M.Math..Math.3}& \mathrm{.Math.}\end{array}\right]$

[0025] Under the proposed concepts and schemes, interleaving of systematic bits and parity bits according to an interlacing function may be mathematically as follows:

[s.sub.1 . . . s.sub.K p.sub.1 . . . p.sub.M].Math..sub.interlacing=[s.sub.1 p.sub.1 s.sub.2 p.sub.2 . . . p.sub.M]

[0026] Under the proposed concepts and schemes, reordering of systematic bits and parity bits according to a bit-reordering function may be mathematically as follows:

[s.sub.1 . . . s.sub.K p.sub.1 . . . p.sub.M].Math..sub.re-ordering=[s.sub.1 s.sub.2 p.sub.1 p.sub.2 p.sub.3 s.sub.3 s.sub.4 p.sub.4 p.sub.5 p.sub.6 . . . s.sub.E3 s.sub.E p.sub.M2 p.sub.M2 p.sub.M]

[0027] The bit-reordering function may be code rate-dependent. Alternatively, the bit-reordering function may be code rate-independent. Moreover, the interleaver may be pseudo-random.

Illustrative Implementations

[0028] FIG. 3 illustrates an example apparatus 300 in accordance with an implementation of the present disclosure. Apparatus 300 may perform various functions as a communication device to implement concepts, schemes, techniques, processes and methods described herein pertaining to NR LDPC with interleaver, including those described above with respect to FIG. 1 and FIG. 2 as well as processes 400 and 500 described below. More specifically, apparatus 300 may implement various aspects of the proposed concepts and schemes pertaining to NR LDPC code block with an interleaving function, an interlacing function, or a bit-reordering function to achieve improved performance by mitigating effects of burst interference as well as noise from high-priority channels.

[0029] Apparatus 300 may be a part of an electronic apparatus which may be a communication device, a computing apparatus, a portable or mobile apparatus, or a wearable apparatus. For instance, apparatus 300 may be implemented in a user equipment, a base station, a smartphone, a smartwatch, a smart bracelet, a smart necklace, a personal digital assistant, or a computing device such as a tablet computer, a laptop computer, a notebook computer, a desktop computer, or a server. Alternatively, apparatus 300 may be implemented in the form of one or more integrated-circuit (IC) chips such as, for example and not limited to, one or more single-core processors, one or more multi-core processors, or one or more complex-instruction-set-computing (CISC) processors.

[0030] Apparatus 300 may include at least some of those components shown in FIG. 3. For instance, apparatus 300 may include at least a processor 310. Additionally, apparatus 300 may include a transceiver 340 configured to engage in wireless communications by transmitting and receiving data wirelessly (e.g., in compliance with one or more 3GPP and 5G NR stands, protocols, specifications and/or any applicable wireless protocols and standards). Apparatus 300 may further include other components (e.g., memory, power system, display device and user interface device), which are not pertinent to the proposed scheme of the present disclosure and, thus, are neither shown in FIG. 3 nor described herein in the interest of simplicity and brevity.

[0031] In one aspect, processor 310 may be implemented in the form of one or more single-core processors, one or more multi-core processors, or one or more CISC processors. That is, even though a singular term a processor is used herein to refer to processor 310, processor 310 may include multiple processors in some implementations and a single processor in other implementations in accordance with the present disclosure. In another aspect, processor 310 may be implemented in the form of hardware (and, optionally, firmware) with electronic components including, for example and without limitation, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors and/or one or more varactors that are configured and arranged to achieve specific purposes in accordance with the present disclosure. In other words, in at least some implementations, processor 310 is a special-purpose machine specifically designed, arranged and configured to perform specific tasks including NR LDPC with interleaver in accordance with various implementations of the present disclosure.

[0032] Processor 310, as a special-purpose machine, may include non-generic and specially-designed hardware circuits that are designed, arranged and configured to perform specific tasks pertaining to NR LDPC with interleaver in accordance with various implementations of the present disclosure. In one aspect, processor 310 may execute the one or more sets of codes, programs and/or instructions (e.g., stored in memory accessible by processor 310) to perform various operations to render NR LDPC with interleaver in accordance with various implementations of the present disclosure. In another aspect, processor 310 may include an encoder 320 and a decoder 330 that, together, perform specific tasks and functions to render NR LDPC with interleaver in accordance with various implementations of the present disclosure. In some implementations, encoder architecture 100 and its functionality and capabilities described above may be implemented in or by encoder 320. In some implementations, decoder architecture 150 and its functionality and capabilities described above may be implemented in or by decoder 330. Each of encoder 320 and decoder 330 may be implemented in the form of hardware with electronic circuitry. Alternatively, each of encoder 320 and decoder 330 may be implemented in the form of software. Still alternatively, each of encoder 320 and decoder 330 may be implemented in the form of a combination of hardware and software.

[0033] In some implementations, encoder 320 may include a LDPC encoder 322 and a FEC robustness enhancement block 324, and encoder 320 may be capable of encoding first data to provide encoded data. For instance, LDPC encoder 322 may encode the first data with a LDPC code to provide LDPC-coded data. Moreover, FEC robustness enhancement block 324 may process the LDPC-coded data with a first FEC robustness enhancement function to provide the encoded data. In some implementations, the first FEC robustness enhancement function may include one of the following functions: an interleaving function that interleaves the LDPC-coded data to provide the encoded data, an interlacing function that interlaces the LDPC-coded data to provide the encoded data, or a bit-reordering function that reorders bits of the LDPC-coded data to provide the encoded data.

[0034] In some implementations, decoder 330 may include a LDPC decoder 332 and a FEC robustness enhancement block 334, and decoder 330 may be capable of decoding second data to provide decoded data. For instance, FEC robustness enhancement block 334 may process the second data with a second FEC robustness enhancement function to provide processed data. Moreover, LDPC decoder 332 may decode the processed data with the LDPC code to provide the decoded data. In some implementations, the second FEC robustness enhancement function may include one of the following: a de-interleaving function that de-interleaves the second data to provide the processed data, a de-interlacing function that de-interlaces the second data to provide the processed data, or a bit-reordering function that reorders bits of the second data to provide the processed data.

Illustrative Processes

[0035] FIG. 4 illustrates an example process 400 in accordance with an implementation of the present disclosure. Process 400 may represent an aspect of implementing the proposed concepts and schemes such as those described with respect to FIG. 1FIG. 3. More specifically, process 400 may represent an aspect of the proposed concepts and schemes pertaining to NR LDPC with interleaver. Process 400 may include one or more operations, actions, or functions as illustrated by one or more of blocks 410 and 420 as well as sub-blocks 412 and 414. Although illustrated as discrete blocks, various blocks of process 400 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks/sub-blocks of process 400 may be executed in the order shown in FIG. 4 or, alternatively in a different order. Process 400 may be implemented by apparatus 300 and any variations thereof. For instance, process 400 may be implemented in or by apparatus 300. Solely for illustrative purposes and without limiting the scope, process 400 is described below in the context of apparatus 300. Process 400 may begin at block 410.

[0036] At 410, process 400 may involve encoder 320 of processor 310 of apparatus 300 encoding data to provide encoded data. Process 400 may proceed from 410 to 420.

[0037] At 420, process 400 may involve processor 310 transmitting, via transceiver 340, the encoded data to a network node of a wireless network, which may be a 5G NR network.

[0038] With respect to encoding the data, process 400 may involve processor 310 performing a number of operations as represented by sub-blocks 412 and 414.

[0039] At 412, process 400 may involve encoder 320 of processor 310 encoding the data with a LDPC code to provide LDPC-coded data. Process 400 may proceed from 412 to 414.

[0040] At 414, process 400 may involve encoder 320 of processor 310 processing the LDPC-coded data with a FEC robustness enhancement function to provide the encoded data.

[0041] In some implementations, the FEC robustness enhancement function may include an interleaving function that interleaves the LDPC-coded data to provide the encoded data. In some implementations, the interleaving function may interleave the LDPC-coded data with a pseudo-random interleaver.

[0042] In some implementations, the FEC robustness enhancement function may include an interlacing function that interlaces the LDPC-coded data to provide the encoded data.

[0043] In some implementations, the FEC robustness enhancement function may include a bit-reordering function that reorders bits of the LDPC-coded data to provide the encoded data. In some implementations, the bit-reordering function may be code rate-dependent. Alternatively, the bit-reordering function may be code rate-independent.

[0044] FIG. 5 illustrates an example process 500 in accordance with an implementation of the present disclosure. Process 500 may represent an aspect of implementing the proposed concepts and schemes such as those described with respect to FIG. 1FIG. 3. More specifically, process 500 may represent an aspect of the proposed concepts and schemes pertaining to NR LDPC with interleaver. Process 500 may include one or more operations, actions, or functions as illustrated by one or more of blocks 510 and 520 as well as sub-blocks 512 and 514. Although illustrated as discrete blocks, various blocks of process 500 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks/sub-blocks of process 500 may be executed in the order shown in FIG. 5 or, alternatively in a different order. Process 500 may be implemented by apparatus 300 and any variations thereof. For instance, process 500 may be implemented in or by apparatus 300. Solely for illustrative purposes and without limiting the scope, process 500 is described below in the context of apparatus 300. Process 500 may begin at block 510.

[0045] At 510, process 500 may involve processor 310 of apparatus 300 receiving, via transceiver 340, encoded data from a network node of a wireless network, which may be a 5G NR network. Process 500 may proceed from 510 to 520.

[0046] At 520, process 500 may involve decoder 330 of processor 310 decoding the encoded data to provide decoded data.

[0047] With respect to decoding the encoded data, process 500 may involve processor 310 performing a number of operations as represented by sub-blocks 512 and 514.

[0048] At 512, process 500 may involve decoder 330 of processor 310 processing the encoded data with a FEC robustness enhancement function to provide processed data. Process 500 may proceed from 512 to 514.

[0049] At 514, process 500 may involve decoder 330 of processor 310 decoding the processed data with a LDPC code to provide the decoded data.

[0050] In some implementations, the FEC robustness enhancement function may include a de-interleaving function that de-interleaves the encoded data to provide the processed data. In some implementations, the de-interleaving function may de-interleave the encoded data with a pseudo-random de-interleaver.

[0051] In some implementations, the FEC robustness enhancement function may include a de-interlacing function that de-interlaces the encoded data to provide the processed data.

[0052] In some implementations, the FEC robustness enhancement function may include a bit-reordering function that reorders bits of the encoded data to provide the processed data. In some implementations, the bit-reordering function may be code rate-dependent. Alternatively, the bit-reordering function may be code rate-independent.

Additional Notes

[0053] The herein-described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely examples, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively associated such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as associated with each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being operably connected, or operably coupled, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being operably couplable, to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.

[0054] Further, with respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.

[0055] Moreover, it will be understood by those skilled in the art that, in general, terms used herein, and especially in the appended claims, e.g., bodies of the appended claims, are generally intended as open terms, e.g., the term including should be interpreted as including but not limited to, the term having should be interpreted as having at least, the term includes should be interpreted as includes but is not limited to, etc. It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases at least one and one or more to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles a or an limits any particular claim containing such introduced claim recitation to implementations containing only one such recitation, even when the same claim includes the introductory phrases one or more or at least one and indefinite articles such as a or an, e.g., a and/or an should be interpreted to mean at least one or one or more; the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number, e.g., the bare recitation of two recitations, without other modifiers, means at least two recitations, or two or more recitations. Furthermore, in those instances where a convention analogous to at least one of A, B, and C, etc. is used, in general such a construction is intended in the sense one having skill in the art would understand the convention, e.g., a system having at least one of A, B, and C would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc. In those instances where a convention analogous to at least one of A, B, or C, etc. is used, in general such a construction is intended in the sense one having skill in the art would understand the convention, e.g., a system having at least one of A, B, or C would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc. It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase A or B will be understood to include the possibilities of A or B or A and B.

[0056] From the foregoing, it will be appreciated that various implementations of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various implementations disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.