Frequency modulation receiver and frequency modulation receiving method

Abstract

A frequency modulation receiver includes a frequency modulation demodulation circuit that generates a first signal, and a phase locked loop (PLL) circuit coupled to the frequency modulation demodulation circuit to receive the first signal. The PLL circuit includes: a voltage-controlled oscillator (VCO), generating an oscillation output signal according to a filtered output signal; a phase detector, coupled to the VCO, generating a phase signal according to the oscillation output signal and the first signal; and a proportional-integral-derivative (PID) filter, coupled to the VCO and the phase detector, receiving the phase signal and generating the filtered output signal to the VCO.

Claims

1. A frequency modulation receiver, comprising: a frequency modulation demodulation circuit, generating a first signal; and a first phase locked loop (PLL) circuit, coupled to the frequency modulation demodulation circuit to receive the first signal, the PLL circuit comprising: a voltage-controlled oscillator (VCO), generating an oscillation output signal according to a filtered output signal; a phase detector, coupled to the VCO, comprising a phase extractor for generating a phase signal according to the oscillation output signal and the first signal; and a proportional-integral-derivative (PID) filter, coupled to the VCO and the phase detector, receiving the phase signal and generating the filtered output signal to the VCO, the PID filter comprising: a proportion circuit, multiplying the phase signal by a proportion coefficient to generate a proportion result; an integration circuit, performing an integration calculation on the phase signal, and multiplying the integration calculation result by an integration coefficient to generate an integration result; a differentiation circuit, performing a differentiation calculation on the phase signal, and multiplying the differentiation calculation result by a differentiation coefficient to generate a differentiation result; and a summation circuit, generating the filtered output signal according to the proportion result, the integration result and the differentiation result, wherein the phase detector comprises: a mixer, mixing the first signal with the oscillation output signal to generate a mixed result; and a low-pass filter, performing a low-pass filter operation on the mixed result to generate a low-frequency signal, wherein the phase extractor extracts a phase of the low-frequency signal to generate the phase signal.

2. The frequency modulation receiver according to claim 1, wherein the integration circuit comprises: a first buffer, generating a first buffered output signal; and an adder, adding the first buffered output signal with the phase signal to generate an addition result; wherein, the first buffer generates the first buffered output signal according to the addition result, and the integration circuit multiplies the addition result by the integration coefficient to generate the integration result.

3. The frequency modulation receiver according to claim 1, wherein the differentiation circuit comprises: a second buffer, generating a second buffered output signal according to the phase signal; and a subtractor, subtracting the second buffered output signal from the phase signal to generate a subtraction result; wherein, the differentiation circuit multiplies the subtraction result by the differentiation coefficient to generate the differentiation result.

4. The frequency modulation receiver according to claim 1, further comprising: a coefficient adjusting circuit, adjusting the proportion coefficient, the integration coefficient and the differentiation coefficient after the PLL operates for a predetermined period of time.

5. A frequency modulation receiving method, applied to a frequency modulation receiver to track a frequency or a phase of a single-tone signal of a first signal, the frequency modulation receiver comprising a frequency modulation demodulation circuit and a phase locked loop (PLL) circuit, the PLL circuit comprising a voltage-controlled oscillator (VCO) and a phase detector, the frequency modulation receiving method comprising: generating the first signal by the frequency modulation demodulation circuit; generating a phase signal according to the first signal and an oscillation output signal that the VCO generates by a phase extractor of the phase detector; multiplying the phase signal by a proportion coefficient to generate a proportion result; performing an integration calculation on the phase signal, and multiplying the integration calculation result by an integration coefficient to generate an integration result; performing a differentiation calculation on the phase signal, and multiplying the differentiation calculation result by a differentiation coefficient to generate a differentiation result; generating the filtered output signal according to the proportion result, the integration result and the differentiation result; and generating the oscillation output signal according to the filtered output signal by the VCO; wherein, the PLL circuit approximates the frequency or the phase of the single-tone signal according to the oscillation output signal and the step of generating the phase signal according to the first signal and the oscillation output signal comprises: mixing the first signal with the oscillation output signal to generate a mixed result; performing a low-pass filter operation on the mixed result to generate a low-frequency signal; and extracting a phase of the low-frequency signal to generate the phase signal.

6. The frequency modulation receiving method according to claim 5, further comprising: adjusting the proportion coefficient, the integration coefficient and the differentiation coefficient after a predetermined period of time.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram of a phase locked loop (PLL) circuit according to an embodiment of the present invention;

(2) FIG. 2 is a block diagram of a filter circuit according to an embodiment of the present invention;

(3) FIG. 3 is a block diagram of an integration circuit according to an embodiment of the present invention;

(4) FIG. 4 is a block diagram of a differentiation circuit according to an embodiment of the present invention;

(5) FIG. 5 is a block diagram of a frequency modulation receiver according to an embodiment of the present invention;

(6) FIG. 6 is a schematic diagram of a spectrum of a signal;

(7) FIG. 7 is a block diagram of a coefficient adjusting circuit according to an embodiment of the present invention;

(8) FIG. 8 is a schematic diagram of oscillation frequencies according to an embodiment of the present invention;

(9) FIG. 9 is a flowchart of a tracking process according to an embodiment of the present invention; and

(10) FIG. 10 is a block diagram of a channel separator.

DETAILED DESCRIPTION OF THE INVENTION

(11) FIG. 1 shows a block diagram of a phase locked loop (PLL) circuit 10 according to an embodiment of the present invention. The PLL circuit 10 includes a voltage-controlled oscillator (VCO) 120, a phase detector 120 and a filter circuit 100. The phase detector 140 generates a phase signal e.sub. according to a signal m (i.e., a first signal) and an oscillation output signal e.sub.o generated by the VCO 120. The filter circuit 100 receives and processes the phase signal e.sub. to generate a filtered output signal e.sub.v. The VCO 120 generates the oscillation output signal e.sub.o according to the filtered output signal e.sub.v. The structure of the VCO 120 is generally known to one person skilled in the art, and shall be omitted herein.

(12) The PLL circuit 10 locks a frequency f.sub.p or a phase .sub.p of a single-tone signal in the signal m. The phase signal e.sub. includes a frequency difference and a phase difference between the single-tone signal in the signal m and the oscillation output signal e.sub.o. When the PLL circuit 10 starts operating, the phase signal e.sub. gradually converges to 0. That is, after the PLL circuit 10 has operated for a period of time, an absolute value |e.sub.| of the phase signal e.sub. becomes smaller than a predetermined value . The faster the phase signal e.sub. converges to 0, the better the convergence speed the PLL circuit 10 provides. In other words, the PLL circuit 10 has a better frequency tracking capability or phase tracking capability for the single-tone signal in the signal m.

(13) To enable the PLL circuit 10 to have a better frequency tracking capability or phase tracking capability, the PLL circuit 10 uses a proportional-integral-derivative (PID) filter as a filter structure of the filter circuit 100, i.e., the filter circuit 100 is a PID filter. The filter circuit 100 includes a proportion circuit 102, an integration circuit 104, a differentiation circuit 106, and a summation circuit 108. The proportion circuit 102 multiplies the phase signal e.sub. by a proportional coefficient k.sub.p to generate a proportional result r.sub.p. The integration circuit 104 performs an integration calculation on the phase signal e.sub. and multiplies the integration calculation result by an integration coefficient k.sub.i to generate an integration result r.sub.i. The differentiation circuit 106 performs a differentiation calculation on the phase signal ee and multiplies the differentiation calculation result by a differentiation coefficient k.sub.d to generate a differentiation result r.sub.d. The summation circuit 108 adds up the proportion result r.sub.p, the integration result r.sub.i and the differentiation result r.sub.d to generate the filtered output signal e.sub.v, which is the sum of the proportion result r.sub.p, the integration result r.sub.i and the differentiation result r.sub.d. In brief, the PLL circuit 10, by using the filter circuit 100 having a PID filter structure, provides a better frequency tracking capability or phase tracking capability.

(14) Details of the filter circuit 100 are given with reference to FIG. 2 to FIG. 4 below. FIG. 2 shows a block diagram of a filter circuit 200 according to an embodiment of the present invention. FIG. 3 shows a block diagram of an integration circuit 304 according to an embodiment of the present invention. FIG. 4 shows a block diagram of a differentiation circuit 406 according to an embodiment of the present invention. The filter circuit 200 has a structure substantially similar to that of the filter circuit 100, and may realize the filter circuit 100. The filter circuit 200 includes a proportion circuit 202, an integration circuit 204, a differentiation circuit 206 and a summation circuit 108. The proportion circuit 202 includes a multiplier MP.sub.p, which multiplies a phase signal e.sub. by a proportional coefficient k.sub.p to generate a proportional result r.sub.p. The integration circuit 204 includes an integrator 240 and a multiplier MP.sub.i. The integrator 240 performs an integration calculation on the phase signal ee, and the multiplier MP.sub.i multiplies the integration calculation result by an integration coefficient k.sub.i to generate an integration result r.sub.i. The differentiation circuit 206 includes a differentiator 260 and a multiplier MP.sub.d. The differentiator 260 performs a differentiation calculation on the phase signal e.sub., and multiplier MP.sub.d multiplies the differentiation calculation result by a differentiation coefficient k.sub.d to generate a differentiation result r.sub.d.

(15) The integrator 240/differentiator 260 may be realized by a digital circuit. As shown in FIG. 3, the integration circuit 304 further includes a digital integrator 340, which includes a register RG_I and an adder AD. The adder AD adds a first buffered output signal generated by the register RG_I with the phase signal e.sub. to generate an addition result sum. The register RG_I buffers the addition result sum in the register RG_I in a (-1).sup.th clock cycle, and, in a k.sup.th clock cycle, outputs the addition result sum stored in the register RG_I in the (k1).sup.th clock cycle (i.e., the first buffered output signal) to the adder AD. As such, the addition result sum represents an integration calculation result that the digital integrator 340 performs on the phase signal e.sub., and the integration circuit 304 multiplies the addition result sum by the integration coefficient k.sub.i to generate the integration result r.sub.i.

(16) Similarly, the differentiation circuit 406 includes a digital differentiator 460, which includes a buffer RG_D and a subtractor SUB. The buffer RG_D buffers the phase signal ee in the register RG_D in the (k1).sup.th clock cycle, and, in the k.sup.th clock cycle, outputs the phase signal ee stored in the register RG_D in the (k1).sup.th clock cycle (i.e., the second buffered output signal) to the subtractor SUB. In the k.sup.th clock cycle, the subtractor SUB may substrate the phase signal e.sub. of the (k1).sup.th clock cycle (i.e., the second buffered output signal) from the phase signal e.sub. of the k.sup.th clock cycle to generate a subtraction signal diff. As such, the subtraction signal diff represents a differentiation calculation result that the digital differentiator 460 performs on the phase signal e.sub., and the differentiator 406 may then multiply the subtraction signal diff by the differentiation coefficient k.sub.d to generate the differentiation result r.sub.d.

(17) It should be noted that, the integrator 240/differentiator 260 is not limited to being realized by a digital circuit. Alternatively, the integrator 240/differentiator 260 may also be realized by an analog circuit (e.g., an RC integrator/an RC differentiator), which is also encompassed within the scope of the present invention.

(18) Known from the above discussion, the PLL circuit 10 is enabled to have a better frequency tracking capability by using the filter circuit 100 having a PID filter structure. When the phase signal e.sub. is larger (particularly when the PLL circuit 10 is about to start to operate), the proportion result r.sub.p in the filtered output signal e.sub.v may increase a variance in the frequency of the oscillation output signal e.sub.o in the next time interval, such that the frequency of the oscillation output signal e.sub.o generated by the VCO 120 promptly approximates the frequency f.sub.p of the single-tone signal in the signal m, thereby accelerating the convergence speed of the PLL circuit 10. On the other hand, during the tracking process of the PLL circuit 10, the differentiation result rd in the filtered output signal e.sub.v may accelerate or alleviate/suppress the variance in the frequency of the oscillation output signal e.sub.o in the next time interval, so as to accelerate the convergence speed and at the same time prevent the frequency of the oscillation output signal e.sub.o from excessively tracking the frequency f.sub.p of the single-tone signal in the signal m that may then cause an even longer convergence time. In comparison, the filter circuit of a conventional PLL is formed by one single loop filter. That is to say, a filtered output signal of a conventional PLL circuit contains only an integration result of the phase signal, and the variance in the frequency of an oscillation output signal in each time interval cannot be adaptively or accurately adjusted based on tracking conditions, in a way that the convergence speed of such conventional PLL circuit is slower. In brief, because the filtered output signal e.sub.v generated by the filter circuit 100 of the PLL circuit 10 according to the embodiment of the present invention further includes the proportion result r.sub.p and the differentiation result r.sub.d, the PLL circuit 10 has a better frequency tracking capability compared to known technologies.

(19) The PLL circuit 10 further includes a coefficient adjusting circuit 12. The coefficient adjusting circuit 12 may selectively adjust the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d after the PLL circuit 10 operates for a predetermined period. In one embodiment, the coefficient adjusting circuit 12 may output the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d having larger values in a first phase, and reduce the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient IQ in a second phase, i.e., outputting the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d having smaller values, so that the PLL circuit 10 has a better convergence effect. Associated details of the performance of frequency tracking are to be described shortly. In one embodiment, the coefficient adjusting circuit 12 may include a counter 70 and a memory 72, as shown in FIG. 7. The memory 72 stores the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d needed in the first phase and the second phase. When a counter value of the counter 70 is greater than a threshold, the coefficient adjusting circuit 12 replaces the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d originally provided in the first phase with the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d of the second phase, and provides the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d of the second phase to the PID filter.

(20) Further, the PLL circuit 10 may be applied in a frequency modulation (FM) receiver. FIG. 5 shows a block diagram of a frequency modulation receiver 5 according to an embodiment of the present invention. The frequency modulation receiver 5 may be a stereo-phonic frequency modulation receiver, and includes a frequency modulation demodulation circuit 52, a PLL circuit 52 and a channel separator 54. The frequency modulation demodulation circuit 52 receives a reception signal x from an antenna of the frequency modulation receiver 5, and generates a frequency modulation demodulated signal m according to the reception signal x. The signal m includes a single-tone pilot signal. The PLL circuit 50 may lock/track a frequency f.sub.p or a phase .sub.p of the pilot signal and generate an oscillation output signal e.sub.o. The channel separator 54 may separate the signal m into a left-channel signal L and a right-channel signal R according to the oscillation output signal e.sub.o.

(21) More specifically, the frequency modulation demodulation circuit 52 may include a superheterodyne receiver. Operation principles are generally known to one person skilled in the art, and shall be omitted herein. For stereo-phonic frequency modulation (given that channel effect and noise are omitted), a time function of the signal m may be represented as m(t)=[L(t)+R(t)]+x.sub.p(t)+[L(t)R(t)] cos(22f.sub.pt+2.sub.p), where L(t) and R(t) respectively represent time functions of the left-channel signal L and the right-channel signal R, x.sub.p(t) is the time function of a (single-tone) pilot signal, the pilot signal x.sub.p(t) may be represented as x.sub.p(t)=A.sub.p cos(2f.sub.pt+.sub.p), and A.sub.p, f.sub.p and .sub.p respectively represent the amplitude, frequency and phase of the pilot signal x.sub.p(t). Further, the spectrum of the signal m(t) may be as shown in FIG. 6. In general, the spectrum of L(t)+R(t) are substantially located between 0 KHz and 15 KHz, the spectrum of the pilot signal x.sub.p(t) is substantially located at 19 KHz, and the spectrum of [L(t)R(t)] cos(22f.sub.pt+2.sub.p) is substantially located between 23 KHz and 53 KHz.

(22) Further, the PLL circuit 50 tracks/locks the phase f.sub.p and phase .sub.p of the pilot signal x.sub.p(t), and thus includes a phase detector 540. The phase detector 540 includes a mixer 502, a low-pass filter (LPF) 504 and a phase extractor 506. The mixer 502 multiplies the signal m by the oscillation output signal o.sub.e to generate a mixed result e.sub.m. The time function of the mixed result e.sub.m may be represented as e.sub.m(t)=m(t) e.sub.o(t), where e.sub.o(t) represents the time function of the oscillation output signal e.sub.o, the oscillation output signal e.sub.o(t) may be represented as e.sub.o(t)=A.sub.o cos(2f.sub.ot+.sub.o), and A.sub.o, f.sub.o and .sub.o respectively represent the amplitude, frequency and phase of the oscillation output signal e.sub.o(t). After the signal m is mixed, the spectrum of the pilot signal x.sub.p(t) shifts to near the baseband, and the LPF 504 may then filter out signal components other than the baseband from the mixed result e.sub.m to generate a low-frequency signal e.sub.d. The time function of the low-frequency signal e.sub.d may be represented as e.sub.d(t)=A.sub.pA.sub.o cos [2(f.sub.pf.sub.o)t+(.sub.p.sub.o)]. The phase extractor 506 extracts the phase of the low-frequency signal e.sub.d to generate the phase signal e.sub.. The time function of the phase signal e.sub. may be represented as e.sub.(t)=2(f.sub.pf.sub.o)t+(.sub.p.sub.o). Other details of the PLL circuit 50 are identical to those of the PLL circuit 10, and shall be omitted herein. The PLL circuit 50 may then generate the oscillation output signal e.sub.o, so as to promptly track/lock the frequency f.sub.p and phase .sub.p of the pilot signal x.sub.p(t).

(23) Further, the channel separator 54 may separate the signal m into the left-channel signal L and the right-channel signal R according to the oscillation output signal e.sub.o. FIG. 10 shows a block diagram of the channel separator 54. The channel separator 54 filters out the signal L(t)+R(t) in 0 KHz to 15 KHz from the signal m(t) by an LPF 548 to obtain a sum signal L+R. Further, the channel separator 54 filters out the signal [L(t)R(t)] cos(22f.sub.pt+2.sub.p) in 23 KHz to 53 KHz from the signal m(t) by a band-pass filter (BPF) 540. Further, the channel separator 54 generates a frequency multiplied signal of the oscillation output signal e.sub.o by a frequency multiplier 544, and relocates [L(t)R(t)] cos(22f.sub.pt+2.sub.p) to baseband by a mixer 542 and an LPF 546 to obtain a difference signal LR. Thus, the channel separator may obtain the left-channel signal L and the right-channel signal R according to the sum signal L+R and the difference signal LR. It should be noted that, as the oscillation output signal e.sub.o(t) gets closer to the pilot signal x.sub.p(t), the effect of separation between the left-channel signal L and the right-channel signal R generated by the channel separator gets better, i.e. the separation between the left and right channels gets better. The performance of the frequency modulation receiver 5 (i.e., the separation of the left and right channels) is described shortly.

(24) In brief, using the filter circuit 100 having a PID filter structure, the present invention enhances the frequency tracking capability of the PLL circuit 10 and further improves the separation between the left and right channels of the frequency modulation receiver 5.

(25) It should be noted that, the foregoing embodiments are for illustrating concepts of the present invention, and one person skilled in the art may make different modifications without departing from the spirit of the present invention. For example, in the operation process of the PLL circuit 10, the coefficient adjusting circuit 12 adjusts the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d in two phases. In an alternative embodiment, the coefficient adjusting circuit 12 may also adjust the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d in multiple phases based on actual conditions during the converging process of the PLL circuit. Given that the PLL circuit 10 adjusts the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d during the converging process, modifications made thereto are encompassed within the scope of the present invention.

(26) The performance of the PLL circuit is given in detail below with reference to Table I and FIG. 8. Table I lists values of the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d, the convergence time of the PLL circuit, and the mean square error of the PLL circuit after the PLL circuit operates for 1500T in scenarios A to D, where T is a time interval that is substantially 3.89 s. FIG. 8 shows a schematic diagram of the oscillation frequency f.sub.o generated by the VCO 120 in the scenarios A to D (the pilot frequency f.sub.p is 19 KHz).

(27) TABLE-US-00001 TABLE I A B C D Scenario t < 2500T t < 2500T t < 200T t > 200T t < 200T t > 200T k.sub.p 0 1/128 1/32 1/128 1/32 1/128 k.sub.i 1/(1024 4) 1/(1024 8) 1/(1024 4) 1/(1024 32) 1/(1024 4) 1/(1024 32) k.sub.d 0 0 0 0 1/64 1/256 Convergence time 2500T 1500T 600T 200T MSE after 1500T 7.37e05 3.38e05 2.68e05 2.5e05

(28) In scenario A, the integration coefficient k.sub.i is persistently 1(1024*4) from a time point T to a time point 2500T, and the proportion coefficient k.sub.p and the differentiation coefficient k.sub.d are persistently 0 from the time point 0 to the time point 2500T. In the above situation, the filtered output signal e.sub.v contains only the integration result r.sub.i. At this point, the effect of the filter circuit in scenario A is equivalent to that of a loop filter of a conventional PLL circuit. The curve of the oscillation frequency f.sub.o corresponding to scenario A in FIG. 8 may represent the frequency tracking performance of a conventional PLL circuit.

(29) In scenario B, the integration coefficient k.sub.i is persistently 1(1024*8) from the time point T to the time point 2500T, the proportion coefficient k.sub.p is persistently 1/128 from the time point T to the time point 2500T, and the differentiation coefficient k.sub.d is persistently 0 from the time point 0 to the time point 2500T. In the above situation, the filtered output signal e.sub.v contains only the proportion result r.sub.p and the integration result r.sub.i but not the differentiation result r.sub.d. At this point, the filter circuit in scenario B is equivalent to the filter circuit 700. The curve of the oscillation frequency f.sub.o corresponding to scenario B in FIG. 8 may represent the frequency tracking performance of the PLL circuit 700 under conditions that the proportion coefficient k.sub.p and the integration coefficient k.sub.i are not adjusted. It is seen from Table I and FIG. 8 that, a conventional PLL circuit (scenario A) needs 2500T to have the oscillation frequency f.sub.o converge to the pilot frequency f.sub.p. Further, even when the filter circuit 700 includes only the proportion circuit and the integration circuit but not the differentiation circuit (scenario B), the convergence speed of the PLL circuit 70 is faster (requiring only 1500T to converge as opposed to the conventional PLL circuit), and has a lower mean square error compared to the conventional PLL circuit when in a stable state (after the time point 1500T).

(30) In scenario C, between the time point 0 and the time point 200T, the proportion coefficient k.sub.p is 1/32 and the integration coefficient k.sub.i is 1/(1024*4); between the time point 200T and the time point 2500T, the proportion coefficient k.sub.p is reduced to 1/128 and the integration coefficient ki is reduced to 1/(1024*32); the differentiation coefficient k.sub.d is persistently 0 from the time point 0 to the time point 2500T. Similarly, the PLL circuit in scenario C is equivalent to the PLL circuit 700, and the curve of the oscillation frequency f.sub.o corresponding to scenario C in FIG. 8 may represent the frequency tracking performance of the PLL circuit 70 under conditions that the proportion coefficient k.sub.p and the integration coefficient k.sub.i are adjusted. In other words, in the first phase (from the time point 0 to the time 200T), the coefficient adjusting circuit 72 provides the filter circuit 700 with higher proportion coefficient k.sub.p and integration coefficient k.sub.i to accelerate the convergence speed of the PLL circuit 70; in a second phase (from the time point 200T to the time point 2500T), the coefficient adjusting circuit 72 reduces the proportion coefficient k.sub.p and the integration coefficient k.sub.i, such that the PLL circuit 70 has a lower mean square error after the time point 1500T. Compared to scenario B, the PLL circuit 70 has a faster convergence speed and a lower mean square error.

(31) Scenario D is similar to scenario C, with differences being that, between the time point 0 and the time point 200T, the differentiation coefficient k.sub.d is 1/64; between the time point 200T and the time point 2500T, the differentiation coefficient k.sub.d is reduced to 1/256. At this point, the PLL circuit in scenario D is equivalent to the PLL circuit 10, and the curve of the oscillation frequency f.sub.o corresponding to scenario D in FIG. 8 may represent the frequency tracking performance of the PLL circuit 700 under conditions that the proportion coefficient k.sub.p, the integration coefficient k.sub.i and the differentiation coefficient k.sub.d are adjusted. Because the differentiation result r.sub.d in the filtered output signal e.sub.v is capable of accelerating or alleviating/suppressing the variance in the frequency of the oscillation outputted signal e.sub.o of a next time interval to prevent the frequency of the oscillation output signal e.sub.o from excessively tracking the frequency f.sub.p of the single-tone signal in the signal m that may cause an even longer convergence time, the PLL circuit 10 in scenario D has a faster convergence speed and a lower mean square error compared to the PLL circuit 70 in scenario C.

(32) Further, as opposed to known technologies, the frequency modulation receiver 5 using the filter circuit 100 (having a PID structure) provides better left and right channel separation. A frequency modulation receiver using a conventional PLL circuit (including a loop filter) provides left and right channel separation that is approximately 20 dB, whereas the frequency modulation receiver 5 (including the filter circuit 100 having a PID filter structure) achieves left and right channel separation that is at least 40 dB.

(33) One person skilled in the art can understand that the function units/circuits in FIG. 1 to FIG. 5 and FIG. 7 may be realized or implemented by digital circuits (e.g., RTL circuit) or a digital signal processor (DSP), and associated details are omitted herein.

(34) Operation details of the frequency modulation receiver 5 may be concluded into a frequency modulation receiving process. FIG. 9 shows a frequency modulation receiving process 90 according to an embodiment of the present invention. The frequency modulation receiving process 90 may be performed by the frequency modulation receiver 5, and includes following steps.

(35) In step 900, the frequency modulation demodulation circuit 52 generates the frequency modulation demodulated signal m according to the reception signal x.

(36) In step 902, the phase detector 140 generates the phase signal e.sub. according to the signal m and the oscillation output signal e.sub.o generated by the VCO 120.

(37) In step 904, the phase signal e.sub. is multiplied by the proportion coefficient k.sub.p to generate the proportion result r.sub.p.

(38) In step 906, an integration calculation is performed on the phase signal e.sub., and the integration calculation result is multiplied by the integration coefficient k.sub.i to generate the integration result r.sub.i.

(39) In step 908, a differentiation calculation is performed on the phase signal e.sub., and the differentiation calculation result is multiplied by the differentiation coefficient k.sub.d to generate the differentiation result r.sub.d.

(40) In step 910, the proportion result r.sub.p, the integration result r.sub.i and the differentiation result r.sub.d are added up to generate the filtered output signal e.sub.v.

(41) In step 912, the VCO 120 generates the oscillation output signal e.sub.o according to the filtered output signal e.sub.v.

(42) In step 914, after a predetermined period, the proportion result r.sub.p, the integration result r.sub.i and the differentiation result r.sub.d are adjusted.

(43) In step 916, the channel separator 54 separates the signal m into the left-channel signal L and the right-channel signal R according to the oscillation output signal e.sub.o.

(44) Operation details of the frequency modulation receiving process 90 may be referred from the foregoing paragraphs, and shall be omitted herein.

(45) While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.