Integrated circuitry

Abstract

There is disclosed herein integrated circuitry, comprising a signal path connected to a connection pad, for connection to external circuitry; and a termination circuit connected between the signal path and a voltage reference, wherein the termination circuit comprises a resistor and an inductor. The resistor and the inductor are connected together so as to compensate for parasitic capacitance associated with the connection pad. The signal path may carry an output signal from high-speed circuitry such as digital-to-analog converter circuitry.

Claims

1. Integrated circuitry, comprising: a signal path connected to a connection pad, for connection to external circuitry; and a termination circuit connected between the signal path and a voltage reference, wherein: the termination circuit comprises first and second resistors connected in series between the signal path and the voltage reference, and an inductor connected in parallel with one of the resistors, so as to compensate for parasitic capacitance associated with the connection pad.

2. The integrated circuitry of claim 1, wherein the resistance of the first resistor is larger than the resistance of the second resistor, and wherein the inductor is connected in parallel with the second resistor.

3. The integrated circuitry of claim 1, wherein the signal path is a signal output path or a signal input path.

4. The integrated circuitry of claim 1, wherein the termination circuit is connected between the signal path and a ground voltage reference.

5. The integrated circuitry of claim 1, wherein the termination circuit is connected between the signal path and a substrate of the integrated circuitry.

6. The integrated circuitry of claim 1, wherein the signal path is implemented as a transmission line.

7. The integrated circuitry of claim 1, wherein the termination circuit is a passive termination circuit.

8. The integrated circuitry of claim 1, wherein the connection pad is a metalized connection pad or land.

9. The integrated circuitry of claim 1, wherein a resistance of the substrate of the integrated circuitry is higher than a resistance of the termination circuit.

10. Digital-to-analogue converter circuitry or analogue-to-digital converter circuitry, comprising the integrated circuitry of claim 1.

11. An IC Chip, comprising the digital-to-analogue converter circuitry or analogue-to-digital converter circuitry of claim 10.

12. The IC chip of claim 11, wherein the IC chip is a flip chip.

13. An IC chip, comprising the integrated circuitry of claim 1.

14. The IC chip of claim 13, wherein the IC chip is a flip chip.

Description

(1) Reference will now be made, by way of example only, to the accompanying drawings, of which:

(2) FIG. 1, mentioned above, presents example step response and frequency response graphs relating to previously-considered circuitry;

(3) FIG. 2 is a schematic diagram representing integrated circuitry useful for understanding embodiments of the present invention;

(4) FIG. 3 presents a frequency response graph showing a change in input impedance over frequency;

(5) FIG. 4 is a schematic diagram of example circuitry alongside existing circuitry for comparison purposes; and

(6) FIG. 5 is another schematic diagram of example circuitry alongside existing circuitry for comparison purposes.

(7) FIG. 2 is a schematic diagram representing integrated circuitry 1 useful for understanding embodiments of the present invention. The integrated circuitry is shown in a simplified form.

(8) Integrated circuitry 1 comprises a high-speed, wideband circuitry block 2, an input or output signal line 4, a connection pad 6, a termination resistor 8, and a substrate 10. Also shown by dashed-line connection is a capacitor C.sub.PAD 12, representing the parasitic capacitance of the connection pad 6.

(9) Incidentally, although focus is placed on analogue output signal lines here it will be appreciated that the present invention is equally applicable to analogue input signal lines, and the present disclosure will be understood accordingly.

(10) The connection pad 6 may be a metalized connection pad or land, useful as an external terminal of the circuitry. For example the connection pad 6 may be suitable to be soldered to a connection pad in another circuit or on a carrier substrate. For example, circuitry 1 may be implemented as a flip chip for connection via one or more such connection pads to a substrate of a flip-chip package.

(11) For the sake of further explanation, it is assumed that the high-speed circuitry block 2 is DAC or ADC circuitry, for example as mentioned above.

(12) As indicated in FIG. 2, and taking an output signal line as an example, the output signal line 4 connects an output of the circuitry block 2 to the connection pad 6. In the case of DAC circuitry, this could be an overall analogue output of that circuitry. The termination resistor 8, for example a 50 resistor, connects the signal line 4 to the substrate 10, i.e. to ground supply, to terminate that signal line.

(13) Of importance here is the parasitic capacitance of the connection pad 6, identified by the present inventors as contributing to the performance problems mentioned above. This parasitic capacitance is modelled here for the benefit of explanation as the discrete capacitor C.sub.PAD 12 connected between the connection pad 6 and the substrate 10. However, it will be understood that this represents a parasitic capacitance, and that no discrete capacitor 12 is provided in the circuitry 1 as such.

(14) This clear insightthe identification and isolation of capacitor C.sub.PAD 12 as being a source of the performance problems discussed aboveis of course a significant contribution and step towards the embodiments disclosed herein. For example, it will be appreciated that circuitry block 2 itself may be very complex, having many thousands of components, with the overall circuitry 1 being similarly complex. Note that the pad 6 will also have some resistance in practice, which may also be taken into account.

(15) FIG. 3 presents a frequency response graph showing how the input impedance may vary over frequency given the circuitry 1 of FIG. 2. A representation of the circuitry 1 is shown in the upper right-hand corner with the circuit block 2 modelled as a current source 2 and with a resistance R.sub.SUBSTRATE 14 modelling the resistance of the substrate explicitly shown in series between the capacitor 12 (parasitic pad capacitance) and ground.

(16) Assuming (as a running example) a target input impedance Z.sub.IN of 50, and thus with the termination resistor 8 being a 50 resistor and the signal line 4 being 50 transmission line, the lower trace 22 in FIG. 3 shows the effect of capacitor 12. The 50 termination resistor appears as such at DC and low frequencies, but as a 45 termination resistor at high frequency. The transition is shown here at around 5 GHz merely as an example, and the value 450 is also simply an example.

(17) The upper trace 24 in FIG. 3 shows in this example that by employing a 55 termination resistor the target 50 input impedance may be experienced at high frequency. However, this may be unsatisfactory given the desired wideband performance.

(18) FIG. 4 is a schematic diagram showing representative circuitry 20 and 30 in order to better explain embodiments of the present invention.

(19) Representative circuitry 20 of FIG. 4(a) corresponds to that shown in FIG. 3 and is provided for comparison purposes.

(20) FIG. 4(b) presents representative circuitry 30. As can be seen from FIG. 4, compared to representative circuitry 20, in representative circuitry 30 the termination resistor 8 has been replaced with a termination circuit 32. The termination circuit 32 comprises termination resistor 8 and an inductor 34. For example, the termination resistance itself may have some inductance. Although the termination resistors 8 are denoted in the same way in FIGS. 4(a) and 4(b), their resistance values may be different from one another.

(21) By maximising or increasing the resistance of the substrate R.sub.SUBSTRATE 14 in the circuitry 30, for example relative to that in circuitry 20, it is effectively possible to minimise the impact of the parasitic capacitance C.sub.PAD 12 of the connection pad 6. The resistance of the substrate may be set when configuring the eventual fabrication of the integrated circuitry, in relation to the materials and processes used. With the resistance of the substrate itself usually fixed by the fabrication process, beyond configuring the fabrication process another possibility is to have a big gap between the pad and other circuits (which adds area, and is often undesirable or even impossible in a practical layout).

(22) FIG. 5 is a schematic diagram showing representative circuitry 20 and 40 also in order to better explain embodiments of the present invention.

(23) Representative circuitry 20 of FIG. 5(a) corresponds to that shown in FIGS. 3 and 4(a) and is again provided for comparison purposes.

(24) FIG. 5(b) presents representative circuitry 40, which embodies the present invention. As can be seen from FIG. 5, compared to representative circuitry 20, in representative circuitry 40 the termination resistor 8 has been replaced with a termination circuit 42. The termination circuit 42 comprises a first termination resistor 44, a second termination resistor 46 and an inductor 48. Also indicated in termination circuit 42 for the benefit of explanation is the real resistance of the (in practice, non-ideal) inductor 48, denoted R.sub.INDUCTOR 50. However, it will be appreciated that this resistance is a property of the non-ideal inductor in practice and not a separate discrete resistance as such.

(25) The first and second termination resistors 44 and 46 are connected in series with one another and in place of the termination resistor 8 of the representative circuitry 20. The inductor 48 is connected in parallel with the second termination resistor 46. The real resistance 50 of the inductor 48 is shown in series with the inductor 48 (as an ideal circuit element) itself. Thus, the combination of elements 50 and 48 correspond to a real non-ideal inductor.

(26) As above, by maximising the resistance of the substrate R.sub.SUBSTRATE 14 in the circuitry 40 it is effectively possible to minimise the impact of the parasitic capacitance C.sub.PAD 12 of the connection pad.

(27) By setting the values of the indicated components it is possible to configure the circuitry 40 to compensate for the parasitic capacitance C.sub.PAD 12 of the connection pad 6.

(28) For example, if R.sub.SUBSTRATE is 500 and R.sub.TERM(ideal) is 50, and if step error is 10%, this may require R.sub.TERM to increase by R=5 at high frequencies. Without R.sub.INDUCTOR, this would give R.sub.TERM1=50 ohms and R.sub.TERM2=5 ohms. The two time constants (RC and LJR) need to match for effective compensation. If C.sub.PAD=60 fF, then RC=R.sub.SUBSTRATE*C.sub.PAD=500 *60 fF=30 ps=L/R.sub.TERM2 which gives L=150 pH. With R.sub.INDUCTOR=30, to keep R=5 this gives R.sub.TERM2=8. This means L=240 pH and R.sub.TERM1=47 (50R.sub.INDUCTOR).

(29) Example values therefore could be: R.sub.TERM1=47 R.sub.TERM2=8 L=240 pH R.sub.INDUCTOR=3 C.sub.PAD=60 fF R.sub.SUBSTRATE=500

(30) It will be appreciated that one or more of the first and second termination resistors 44 and 46 and the inductor 48 (FIG. 5(b)) could be implemented as variable components, i.e. as variable resistors or inductors. This would enable the performance problems to be tuned out in a particular circuit, for example dynamically if need be. However, in practice it may be that fixed components designed to tune out the performance problems may be used. Thus, the termination circuit 42 may be implemented as dynamic-value (i.e. adjustable) or fixed-value circuit. Such circuits may in some embodiments include active components and in other embodiments only passive components.

(31) It will be appreciated that the circuitry embodying the present invention could be provided in the form of an IC chip having high-speed circuitry 20. The high-speed circuitry 20 could comprise mixed-signal circuitry such as DAC or ADC circuitry. Embodiments of the present invention thus may be represented by the circuitry 1 of FIG. 2, except with the termination resistor 8 replaced by the termination circuit 32 or 42.

(32) Such a chip may have one or more contact or connection pads corresponding to connection pad 6, and thus the present invention may be embodied in respect of one, a plurality, or in respect of all of such connection pads.

(33) It will also be appreciated that the circuitry disclosed herein could be described as a DAC or ADC. Circuitry of the present invention may be implemented as integrated circuitry, for example on an IC chip. The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards.

(34) The present invention may be embodied in many different ways in the light of the above disclosure, within the spirit and scope of the appended claims.