LINEARIZED NEGATIVE IMPEDANCE CONVERTER MATCHING CIRCUITS AND IMPEDANCE ADJUSTMENT CIRCUIT FOR A NEGATIVE IMPEDANCE CONVERTER

Abstract

There is disclosed a negative impedance converter for a matching circuit for matching an impedance of an antenna to an impedance of an RF source or load. The negative impedance converter comprises first and second transistors connected in a cross-over configuration. Each transistor has a source or emitter, a drain or collector and a gate or base, and each transistor further has a first biasing circuit connected to its gate or base. The first biasing circuit comprises a first DC biasing signal source and a first diode or a third transistor connected between the first DC biasing signal source and the gate or base. There is also disclosed a negative impedance converter for a matching circuit for matching an impedance of an antenna to an impedance of an RF source or load. The negative impedance converter comprises first and second transistors connected in a cross-over configuration, each transistor having a source or emitter, a drain or collector and a gate or base. The source or emitter of one transistor is configured as an RF input port and the source or emitter of the other transistor is configured as an RF output port. The drain or collector of the first transistor is connected to the gate or base of the second transistor and the drain or collector of the second transistor is connected to the gate or base of the first transistor. An impedance is connected between the drain or collector of the first transistor and the drain or collector of the second transistor. The negative impedance converter is further provided with a passive impedance adjustment network connected between the source or emitter of the first transistor and the source or emitter of the second transistor.

Claims

1. A negative impedance converter for a matching circuit for matching an impedance of an antenna to an impedance of an RF source or load, the negative impedance converter comprising first and second transistors connected in a cross-over configuration, each transistor having a source or emitter, a drain or collector and a gate or base, and each transistor further having a first biasing circuit connected only to its gate or base and not to the drain or collector of the other transistor, wherein the first biasing circuit comprises a first DC biasing signal source and a first diode connected between the first DC biasing signal source and the gate or base.

2. A negative impedance converter for a matching circuit for matching an impedance of an antenna to an impedance of an RF source or load, the negative impedance converter comprising first and second transistors connected in a cross-over configuration, each transistor having a source or emitter, a drain or collector and a gate or base, and each transistor further having a first biasing circuit connected only to its gate or base and not to the drain or collector of the other transistor, wherein the first biasing circuit comprises a first DC biasing signal source and a third transistor connected between the first DC biasing signal source and the gate or base.

3. The negative impedance converter as claimed in claim 1, further comprising a second diode connected in series with the first diode or the third transistor.

4. The negative impedance converter as claimed in claim 1, further comprising a further transistor connected in series with the first diode or the third transistor.

5. The negative impedance converter as claimed in claim 1, wherein the gate or base of each of the first and second transistors is provided with a conductive gate or base connection to allow an RF signal to be connected to the gate or base.

6. The negative impedance converter as claimed in claim 5, wherein the gate or base connection of each of the first and second transistors is connected to the respective first biasing circuit between the respective first and second diodes, third transistor and further transistor, or first diode and further transistor.

7. The negative impedance converter as claimed in claim 1, wherein the first biasing circuit of each of the first and second transistors further comprises one or more resistors, capacitors and/or inductors so as to allow the first DC biasing signal to be conditioned as required.

8. The negative impedance converter as claimed in claim 1, wherein for each of the first and second transistors, the first and second diodes or third transistor and further transistor or first diode and further transistor are connected in series with each other with the same polarity, and are connected between the first DC biasing signal source and ground.

9. The negative impedance converter as claimed in claim 8, wherein for each of the first and second transistors, resistors are provided in the first biasing circuit to act as a potential divider, thereby allowing the first biasing circuit to apply the required first DC biasing signal to the base or gate.

10. The negative impedance converter as claimed in claim 1, wherein for each of the first and second transistors, a first capacitor is connected in parallel with the first diode or third transistor.

11. The negative impedance converter as claimed in claim 10, wherein for each of the first and second transistors, an additional capacitor is connected between an input of the first diode or third transistor and ground, so as to enable a DC operation current to increase adaptively with an increase in an input signal power level.

12. The negative impedance converter as claimed claim 1, wherein for each of the first and second transistors, an inductor is connected between the first and second diodes, or between the third transistor and the further transistor or between the first diode and the further transistor.

13. The negative impedance converter as claimed in claim 1, wherein for each of the first and second transistors, there is provided a second biasing circuit connected across the collector or drain and the emitter or source of the transistor.

14. The negative impedance converter as claimed in claim 13, wherein the second biasing circuit of each of the first and second transistors further comprises a second DC biasing signal source.

15. The negative impedance converter as claimed in claim 13, wherein for each of the first and second transistors, the second biasing circuit is connected by way of an inductor to the collector or drain of the transistor, and wherein the emitter or source is connected to ground by way of a further inductor.

16. The negative impedance converter as claimed in claim 1, further comprising an RF input port connected to the emitter or source of the first transistor, and an RF output port connected to the emitter or source of the second transistor.

17. The negative impedance converter as claimed in claim 16, further comprising at least one capacitor connected in parallel between the RF input port and RF output port.

18. The negative impedance converter as claimed in claim 17, further comprising at least one resistor connected in parallel with the at least one capacitor.

19. The negative impedance converter as claimed in claim 1, wherein the collector or drain of the first transistor is connected to the base or gate of the second transistor, and the collector or drain of the second transistor is connected to the base or gate of the first transistor.

20. The negative impedance converter as claimed in claim 19, wherein a predetermined impedance is provided between the respective collectors or drains on the one hand, and the respective bases or gates on the other hand, of the first and second transistors.

21. The negative impedance converter as claimed in claim 20, wherein the predetermined impedance determines the negative impedance that the NIC applies to an RF signal passing between the input port and the output port.

22. The negative impedance converter as claimed in claim 21, wherein the predetermined impedance is adjustable.

23. The negative impedance converter as claimed in claim 22, wherein the predetermined impedance comprises a variable capacitor and/or a variable inductor.

24. The negative impedance converter as claimed in claim 22, wherein the predetermined impedance is configured to be adjustable by way of a control input from a digital controller.

25. A negative impedance converter for a matching circuit for matching an impedance of an antenna to an impedance of an RF source or load, the negative impedance converter comprising first and second transistors connected in a cross-over configuration, each transistor having a source or emitter, a drain or collector and a gate or base, wherein the source or emitter of one transistor is configured as an RF input port, the source or emitter of the other transistor is configured as an RF output port, the drain or collector of the first transistor is connected to the gate or base of the second transistor and the drain or collector of the second transistor is connected to the gate or base of the first transistor, and an impedance comprising a capacitance, and inductance and a resistance connected in series is provided between the drain or collector of the first transistor and the drain or collector of the second transistor, and further wherein the negative impedance converter is provided with a passive impedance adjustment network connected between the source or emitter of the first transistor and the source or emitter of the second transistor.

26. The negative impedance converter as claimed in claim 25, wherein the passive impedance adjustment network comprises at least one resistor connected in parallel with a capacitor.

27. The negative impedance converter as claimed claim 25, wherein the passive impedance adjustment network comprises a first parallel resistor-capacitor bank connected in series with a second parallel resistor-capacitor bank.

28. The negative impedance converter as claimed in claim 25, wherein the passive impedance adjustment network comprises a capacitor.

29. The negative impedance converter as claimed in claim 28, wherein the passive impedance adjustment network further comprises a resistor connected in series with the capacitor.

30. A negative impedance converter as claimed in claim 28, wherein the passive impedance adjustment network further comprises a resistor connected in parallel with the capacitor.

31. The negative impedance converter as claimed in claim 28, wherein the passive impedance adjustment network further comprises a resistor and an inductor connected in parallel with the capacitor.

32. The negative impedance converter as claimed in claim 25, wherein the capacitor or capacitors in the passive impedance adjustment network provide a total capacitance selected so as to compensate for a total parasitic capacitance introduced by the first and second transistors.

33. The negative impedance converter as claimed in claim 25, wherein the capacitor or capacitors in the passive impedance adjustment network is or are of fixed value capacitance.

35. (canceled)

36. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Embodiments of the invention are further described hereinafter with reference to the accompanying drawings, in which:

[0055] FIG. 1 shows an electrically small antenna connected to a 50 ohm signal port;

[0056] FIG. 2 shows the antenna of FIG. 1 represented as an equivalent series connected resistor, capacitor and inductor;

[0057] FIG. 3 shows the arrangement of FIG. 2 provided with a passive impedance matching network, together with a plot of reactance against angular frequency;

[0058] FIG. 4 shows the arrangement of FIG. 2 provided with a non-Foster matching network comprising a negative capacitance, together with a plot of reactance against angular frequency;

[0059] FIG. 5 illustrates an antenna circumscribed by a sphere of radius a;

[0060] FIG. 6 is a schematic of a conventional Linvill type negative impedance converter (NIC);

[0061] FIG. 7 shows a conventional NIC arrangement for matching an antenna to a transceiver;

[0062] FIG. 8 is a schematic of a conventional Linvill type negative impedance converter (NIC);

[0063] FIG. 9 shows a conventional NIC arrangement for matching an antenna to a transceiver;

[0064] FIG. 10 shows an NIC-based matching circuit for an electrically small antenna;

[0065] FIG. 11 shows the NIC of FIG. 10 in more detail;

[0066] FIG. 12 shows a conventional biasing circuit for one transistor in an NIC;

[0067] FIG. 13 shows a first embodiment;

[0068] FIG. 14 shows a second embodiment;

[0069] FIG. 15 shows a third embodiment;

[0070] FIG. 16 shows a plot of gain vs. power for the circuits of FIGS. 12, 13 and 14;

[0071] FIG. 17 shows an NIC with an impedance adjustment network in accordance with the third aspect;

[0072] FIG. 18 shows an implementation of the NIC of FIG. 17;

[0073] FIG. 19 is an alternative schematic showing the NIC of FIG. 15 being used to match an antenna to a feeding port;

[0074] FIG. 20 is a plot comparing the input impedance of a conventional NIC with the input impedance of an NIC as shown in FIG. 17; and

[0075] FIG. 21 is a plot comparing the matching performance of a conventional NIC with the matching performance of an NIC as shown in FIG. 17;

DETAILED DESCRIPTION

[0076] FIG. 10 illustrates an embodiment comprising an NIC-based matching circuit for an electrically small antenna. The circuit comprises an output termination 1, a two-port antenna model 2, a neutralization inductor 3, an NIC block 4, a capacitor 5 for impedance transformation and an RF source 6.

[0077] FIG. 11 shows the NIC block 4 in more detail, the NIC including an input port 7 connected to the emitter or source port P3 of a first transistor sub-circuit 9, and an output port 8 connected to the emitter or source port P3 of a second transistor sub-circuit 10. The transistor sub-circuits 9, 10 are connected in a cross-over configuration, with the base or gate port P1 of the first transistor sub-circuit 9 connected to the collector or drain port P2 of the second transistor sub-circuit 10, and the collector or drain port P2 of the first transistor sub-circuit 9 connected to the base or gate port P1 of the second transistor sub-circuit 10. A capacitor 100 and a lossy inductor 101 are connected between the collector or drain ports P2 of the transistor sub-circuits 9, 10, the capacitor 100 and inductor 101 defining the negative impedance that is presented by the NIC block 4 between its input port 7 and output port 8. By applying a negative impedance to the RF signal passing from input port 7 to output port 8, the NIC block 4 can match the RF signal to the antenna.

[0078] The NIC block 4 further comprises parallel-connected passive components in the form of resistors 64, 66 and capacitors 65, 67 which are used to adjust the impedance of the NIC block 4, thereby to enhance matching performance, linearity and stability.

[0079] Impedance tuning of the NIC block 4 can be controlled by some external device such as a microprocessor (not shown).

[0080] FIG. 12 shows one of the transistor sub-circuits 9, 10 of FIG. 11 in more detail, shown here configured with known biasing circuitry so as to illustrate present embodiments more clearly. The sub-circuit comprises a transistor 20 having an emitter or source 21, a collector or drain 22 and a base or gate 23. The base or gate 23 of the transistor 20 is connected to port P1 by way of a DC block 34. A first DC biasing signal is applied to the gate 23 by a DC source 32 and an inductor 33. The emitter or source 21 is connected to port P3 by way of a DC block 30, and the collector or drain 22 is connected to port P2 by way of a DC block 29. A second DC biasing signal is applied between the collector or drain 22 and the emitter or source 21 by way of DC source 26. Inductors 27 and 28 are provided to block RF signals. The DC source 32 controls the bias current and the DC source 26 controls the bias voltage across the collector or drain 22 and the emitter or source 21 of the transistor 20. The DC blocks 29, 30, 34 are provided to isolate the ports P2, P3, P1 from the biasing signals.

[0081] To achieve high linearity and simultaneous transmit and receive, the functional transistors in the NIC are preferably biased in a Class-A (linear) bias condition.

[0082] FIG. 13 shows a first embodiment, comprising a transistor sub-circuit 9, 10 based around a transistor 20. The sub-circuit comprises a transistor 20 having an emitter or source 21, a collector or drain 22 and a base or gate 23. The base or gate 23 of the transistor 20 is connected to port P1 by way of a DC block 34. A first DC biasing signal is applied to the gate 23 by a DC source 32. The first biasing signal passes through a first resistor 35, a first diode 36, an inductor 37, a second diode 38 and a second resistor 39 to ground. A first capacitor 40 connects the input to the first diode 36 to ground, and a second capacitor 41 is connected in parallel with the first diode 36. The first and second diodes 36, 38 have the same polarity. Resistors 35 and 39 are configured as a potential divider and can be adjusted so as to vary the first biasing signal as required, together with the diodes 36, 38. The first diode 36 and the capacitors 40, 41 help to promote RF power linearization. The emitter or source 21 is connected to port P3 by way of a DC block 30, and the collector or drain 22 is connected to port P2 by way of a DC block 29. A second DC biasing signal is applied between the drain 22 and the source 21 by way of DC source 26. Inductors 27 and 28 are provided to block RF signals. The DC source 32 controls the bias current and the DC source 26 controls the bias voltage. The DC blocks 29, 30, 34 are provided to isolate the ports P2, P3, P1 from the biasing signals.

[0083] In the embodiment of FIG. 13, the first and second diodes 36, 38 only have a DC connection to the base or gate 23 of the transistor 20 rather than to the collector or drain 22 due to the DC block capacitors 29, 34. The two diodes 36, 38 form a voltage divider to provide DC voltage to the base or gate 23. In addition, a coupling capacitor 40 is used to couple the input signal power and to provide voltage rectification with the first diode 36. This applies also to the embodiments of FIGS. 12 and 13.

[0084] FIG. 14 shows an alternative implementation of the FIG. 13 embodiment, in which the second diode 38 is replaced with a further transistor 42.

[0085] A further alternative implementation of the FIG. 13 embodiment is shown in FIG. 15, where both the first and second diodes 36, 38 are replaced with a third transistor 43 and a further transistor 44.

[0086] The three biasing circuits shown in FIGS. 12 (prior art), 13 (two diodes) and 14 (one diode, one transistor) were tested with the two main RF transistors in the NIC 4 biased at 40 mA and 2.5V. FIG. 16 shows a plot of gain against power (in) for the different biasing circuits, with the plot for the FIG. 12 circuit identified at 45, the plot for the FIG. 13 embodiment identified at 46, and the plot for the FIG. 14 embodiment identified at 47.

[0087] Table 1 below gives the values for IMD3 (in dBc) for the different biasing circuits of FIGS. 12, 13 and 14.

TABLE-US-00001 TABLE 1 821 MHz 851 MHz 881 MHz Pin (dBm) 0 5 10 15 20 0 5 10 15 20 0 5 10 15 20 FIG. 12 50 38 23 18 17 52 39 24 20 18 57 44 27 23 22 FIG. 13 44 41 42 45 43 38 38 41 45 37 36 37 40 45 37 FIG. 14 77 55 42 41 40 71 43 36 42 35 60 39 34 36 33

[0088] FIG. 17 shows an NIC similar to that of FIG. 8, but provided with an impedance adjustment network in accordance with the third aspect. The NIC comprises first and second biased transistors 51, 52 connected in a crossover configuration. The NIC may comprise field effect transistors, in which case the transistors 51, 52 will have a source 55, 55, a drain 54, 54 and a gate 53, 53. Alternatively, the NIC may comprise bipolar junction transistors, in which case the transistors 51, 52 will have an emitter 55, 55, a collector 54, 54 and a base 53, 53.

[0089] The collector or drain 54 of the first transistor 51 is connected to the base or gate 53 of the second transistor 52, and the collector or drain 54 of the second transistor 52 is connected to the base or gate 53 of the first transistor 51. A predetermined impedance is provided between the respective collectors or drains 54, 54 on the one hand, and the respective bases or gates 53, 53 on the other hand, of the first and second transistors 51, 52. The predetermined impedance determines the negative impedance that the NIC applies to an RF signal passing between the input port 100 and the output port 101. The predetermined impedance is represented by a resistor 56, an inductor 57 and a capacitor 58 connected in series between the respective collectors or drains 54, 54.

[0090] An impedance adjustment network is provided in the form of first and second parallel resistor-capacitor banks 62, 63 connected in series to form a two terminal network. The impedance adjustment network is connected between the sources or emitters 55, 55 of the first and second transistors 51, 52 as shown. The first resistor-capacitor bank 62 comprises a resistor 64 and a capacitor 65 connected in parallel, and the second resistor-capacitor bank 63 comprises a resistor 66 and a capacitor 67 connected in parallel.

[0091] FIG. 18 shows how the NIC with impedance adjustment network of FIG. 17 can be implemented as a non-Foster matching circuit for an electrically small antenna 59. An external inductor 60 is connected between the antenna 59 and the source or emitter 55 of the second transistor 52. The negative impedance generated by the NIC is used to neutralise the reactance of the external inductor 60 and the antenna 59. An external capacitor 61 is connected to the source or emitter 55 of the first transistor 51 so as to transform the neutralised impedance to 50 at the RF output port 101 of the NIC. The first and second parallel resistor-capacitor banks 62, 63 constitute the passive impedance adjustment network.

[0092] FIG. 19 shows the arrangement of FIG. 18 in more general block form. An NIC 200 includes an impedance represented here by a series inductor 201, capacitor 202 and resistor 203, this impedance determining the negative impedance applied by the NIC 200. A passive impedance adjustment network 204 as described above is connected in parallel with the NIC 200. An electrically small antenna 205 is connected to the RF output 206 of the NIC 200 by way of a passive impedance transformation network 207. An antenna feeding port 208 is connected to the RF input 209 of the NIC 200 by way of another passive impedance transformation network 210.

[0093] To demonstrate the surprising technical benefits obtained by the impedance adjustment network of present embodiments, reference shall now be made to FIG. 20, which shows the input impedance of the conventional NIC of FIG. 8 compared to the input impedance of the NIC with the impedance adjustment network of FIG. 17 across a range of frequencies. From FIG. 20, it can be seen that in the conventional NIC, the real part of the impedance decreases monotonically from a value of 54.37 (significantly higher than 50) at 856.9 MHz to a value of 46.12 (significantly lower than 50) at 1030 MHz. This means that the total efficiency is degraded at lower frequencies and that stability is a potential problem. In contrast, when the impedance adjustment network is implemented, the real part of the impedance has a local minimum of 48.73 at around 900 MHz, and is 50 at both 856.9 MHz and 976.6 MHz. At 1030 MHz, the real part of the impedance is 53.56. It can also be seen that the imaginary part of the impedance has much slower variation when the impedance adjustment network is implemented. As a consequence, the impedance adjustment network improves the matching performance and stability of the whole circuit.

[0094] FIG. 21 shows how the matching performance of the circuit of FIG. 9 is improved by provision of the impedance adjustment network as shown in FIG. 18. In the conventional NIC circuit of FIG. 9, the S-parameter curves have uneven shapes, and at some frequency points, both high total efficiency and high return loss occur simultaneously. By providing an impedance adjustment network as hereinbefore described, the shapes of the S-parameter curves assume more well-behaved shapes, and high total efficiency corresponds appropriately to a low return loss.

[0095] The resistor/capacitor banks 62, 63 may be replaced by a single capacitor, or several capacitors. What is important is that the passive impedance adjustment network 204 is configured to compensate for parasitic capacitance in the transistors 51, 52. In some embodiments, this may be achieved by configuring the passive impedance adjustment network to have a capacitance substantially equal to the parasitic capacitance in the transistors 51, 52.

[0096] Throughout the description and claims of this specification, the words comprise and contain and variations of them mean including but not limited to, and they are not intended to (and do not) exclude other moieties, additives, components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.

[0097] Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

[0098] The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.