LED DISPLAY APPARATUS AND MANUFACTURING METHOD OF THE SAME

Abstract

An LED display apparatus with a simplified manufacturing process is provided. The LED display apparatus includes a common electrode layer on a first substrate, a second substrate including a first pixel driving device and a second pixel driving device, and a first light emitting device and a second light emitting device on the common electrode layer. The first light emitting device includes a first n-type semiconductor layer, a first active layer, and a first p-type semiconductor layer. The second light emitting device includes a second n-type semiconductor layer, a second active layer, and a second p-type semiconductor layer. As such, it is possible to provide an LED display apparatus with improved manufacturing reliability having at least one unit pixel composed of pixels by using at least one light emitting device integrated with the common electrode layer and at least two individual light emitting devices.

Claims

1. A light emitting diode (LED) display apparatus, comprising a common electrode layer on a first substrate; a second substrate including a first pixel driving device and a second pixel driving device; a first light emitting device on the common electrode layer, the first light emitting device including a first n-type semiconductor layer, a first active layer, and a first p-type semiconductor layer; a second light emitting device on the common electrode layer, the second light emitting device including a second n-type semiconductor layer, a second active layer, and a second p-type semiconductor layer; a first connection electrode configured to connect the first p-type semiconductor layer to the first pixel driving device; and a second connection electrode configured to connect the second p-type semiconductor layer to the second pixel driving device, wherein the common electrode layer is made of a same material as the first n-type semiconductor layer and is directly connected to the first n-type semiconductor layer, and wherein the LED display apparatus further comprises a third connection electrode configured to connect the common electrode layer to the second n-type semiconductor layer.

2. The LED display apparatus of claim 1, wherein the common electrode layer is disposed on the entire area of the first substrate.

3. The LED display apparatus of claim 1, wherein the first active layer and the second active layer are configured to emit light of different wavelengths.

4. The LED display apparatus of claim 1, wherein the first active layer is configured to emit light of a blue wavelength or a green wavelength.

5. The LED display apparatus of claim 1, further comprising a buffer layer configured to buffer a lattice constant between two layers of the first substrate and the common electrode layer, wherein the common electrode layer is grown on the first substrate by an epitaxy process.

6. The LED display apparatus of claim 1, wherein the first substrate is a sapphire substrate.

7. The LED display apparatus of claim 1, wherein the common electrode layer is an nGaN layer doped with Si.

8. The LED display apparatus of claim 1, further comprising a black matrix disposed between the first light emitting device and the second light emitting device.

9. The LED display apparatus of claim 1, further comprising a light mixing preventing layer disposed between the first light emitting device and the second light emitting device.

10. The LED display apparatus of claim 9, wherein the light mixing preventing layer is a light guide layer made of a conductive material for reflecting light.

11. The LED display apparatus of claim 1, further comprising a third light emitting device on the common electrode layer, wherein the first light emitting device, the second light emitting device, and the third light emitting device emit light of different wavelengths.

12. A method of manufacturing a light emitting diode (LED) display apparatus, the method comprising: forming a common electrode layer on a first substrate and subsequently growing a first light emitting device including a first n-type semiconductor layer, a first active layer, and a first p-type semiconductor layer; disposing a first pixel driving device and a second pixel driving device on a second substrate; transferring a second light emitting device including a second n-type semiconductor layer, a second active layer, and a second p-type semiconductor layer on the common electrode layer; bonding the first substrate and the second substrate to each other; disposing a first connection electrode to connect the first p-type semiconductor layer to the first pixel driving device; and disposing a second connection electrode to connect the second p-type semiconductor layer to the second pixel driving device.

13. The method of claim 12, wherein the forming the common electrode layer and the growing the first light emitting device on the first substrate include growing continuously a semiconductor layer and etching thereof to form the first light emitting device.

14. The method of claim 12, wherein the forming the common electrode on the first substrate further includes forming a buffer layer to buffer a lattice constant on the first substrate.

15. The method of claim 12, wherein the transferring the second light emitting device on the common electrode layer further includes: providing the second light emitting device grown on a third substrate; and disposing an adhere layer on the common electrode layer to attach the second light emitting device thereto.

16. The method of claim 12, wherein the transferring the second light emitting device on the common electrode includes disposing a third connection electrode on the common electrode layer to connect the second light emitting device thereto.

17. The method of claim 12, wherein the common electrode layer is an nGaN layer doped with Si.

18. The method of claim 12, further comprising: forming a black matrix between the first light emitting device and the second light emitting device.

19. The method of claim 12, further comprising: forming a light mixing preventing layer between the first light emitting device and the second light emitting device.

20. The method of claim 19, wherein the light mixing preventing layer is a light guide layer made of a conductive material for reflecting light.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0046] FIG. 1 is a view showing a schematic configuration of an LED display apparatus 100 according to an embodiment of the present disclosure.

[0047] FIG. 2 is a schematic diagram for explaining a circuit structure of pixels arranged in the LED display apparatus 100 according to an embodiment of the present disclosure.

[0048] FIG. 3 is a schematic cross-sectional view for explaining the configuration of the pixel of the LED display apparatus 100 according to an embodiment of the present disclosure.

[0049] FIG. 4 is a schematic flowchart for explaining a method of manufacturing the LED display apparatus 100 according to an embodiment of the present disclosure.

BEST MODE OF THE INVENTION

[0050] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood that the present invention is not limited to the following embodiments and may be embodied in different ways, and that the embodiments are given to provide complete disclosure of the present invention and to provide thorough understanding of the present invention to those skilled in the art. The scope of the present invention is limited only by the accompanying claims and equivalents thereof.

[0051] In the drawings, the shapes, sizes, ratios, angles, and the number of components are provided for illustration only and do not limit the scope of the present invention. The same components will be denoted by the same reference numerals throughout the specification. Detailed description of known functions and constructions which can unnecessarily obscure the subject matter of the present invention will be omitted. The terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups there. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0052] Unless stated otherwise, a margin of error is considered in analysis of components.

[0053] In description with spatially relative terms, for example, when an element is referred to as being disposed “on,” “above,” “below,” or “beside” another element or layer, the element can be directly “on,” “above,” “below,” or “beside” the other element or intervening elements may be present, unless stated otherwise.

[0054] In description of operations with temporal terms, for example, “after,” “subsequent to,” “before,” or “followed by”, the operations may be continuously or discontinuously performed, unless stated otherwise.

[0055] In description of the signal flow relationship, for example, even in the case of ‘a signal is transmitted from node A to node B’, unless ‘directly’ or ‘directly’ is used, it may include a case in which a signal is transmitted from node A to node B via another node.

[0056] Although the terms “first”, “second”, “A”, “B”, etc. may be used herein to describe various elements, components and/or regions, these elements, components and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component or region from another element, component or region. Thus, a “first” element or component discussed below could also be termed a “second” element or component, or vice versa, without departing from the scope of the present invention.

[0057] Features of various embodiments of the present invention can be partially or entirely coupled to or combined with each other to realize various technical associations and operations and can be realized independently of each other or in association with each other.

[0058] Hereinafter, various embodiments will be described with reference to the accompanying drawings.

[0059] Referring to FIG. 1, the LED display apparatus 100 according to embodiments of the present invention can includes a display panel 101 in which a plurality of sub pixels SP including micro light emitting diodes μLED are arranged, a gate driving circuit 120 for driving the display panel 101, a data driving circuit 130, and a controller 140.

[0060] In the display panel 101, a plurality of gate lines GL and a plurality of data lines DL are disposed, and the sub pixel SP is disposed in the region where the gate line GL and the data line DL are intersected. Each of these sub-pixels SP may include a micro light emitting diode μLED, and one pixel P may include two or more sub-pixels SP.

[0061] The gate driving circuit 120 is controlled by the controller 140 and the scan signal is sequentially output to the plurality of gate lines GL in the display panel 101 to control a driving timing of the plurality of sub pixels.

[0062] The gate driving circuit 120 may include one or more gate driver integrated circuits (GDIC), and may be located on only one side or both sides of the display panel 101 depending on the driving method. Or, the gate driving circuit 120 may be located on the rear surface of the display panel 101.

[0063] The data driving circuit 130 receives the image data from the controller 140 and converts the image data into the analog data voltages. Further, the data voltage is output to each data line DL according to the timing when the scan signal is applied through the gate line GL, so that each sub pixel SP displays brightness according to image data.

[0064] The data driving circuit 130 may include one or more source driver integrated circuits SDICs.

[0065] The controller 140 supplies the various signal to the gate driving circuit 120 and the data driving circuit 130 and controls the operation of the gate driving circuit 120 and the data driving circuit 130.

[0066] The controller 140 causes the gate driving circuit 120 to output a scan signal according to the timing implemented in each frame, and converts externally received image data to match the data signal format used by the data driving circuit 130 and outputs the converted image data to the data driving circuit 130.

[0067] The various timing signals including the image data, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable signal (DE, Data Enable), and a clock signal (CLK) is applied to the controller 140 from the outside (e.g., a host system)

[0068] The controller 140 may generate various control signals using various timing signals received from the outside and output them to the gate driving circuit 120 and the data driving circuit 130.

[0069] For example, the controller 140 outputs various gate controlling signals including a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE) etc. in order to control the gate driving circuit 120.

[0070] Here, the gate start pulse (GSP) controls the driving start timing of one or more gate driver integrated circuits of the gate driving circuit 120. The gate shift clock (GSC), which is a clock signal commonly input to one or more gate driver integrated circuits, controls shift timing of the scan signal. The gate output enable signal (GOE) specifies timing information of one or more gate driver integrated circuits.

[0071] Further, the controller 140 outputs various data controlling signals including a source start pulse (SSP), a source sampling clock (SSC), and a source output enable (SOE) etc. to control the data driving circuit 130.

[0072] Here, the source start pulse (SSP) controls the data sampling start timing of one or more source driver integrated circuits of the data driving circuit 130. The source sampling clock (SSC) is the clock signal that controls sampling timing of data in each of the source driver integrated circuits. The source output enable signal (SOE) controls the output timing of the data driving circuit 130.

[0073] The LED display apparatus 100 may further include a power management integrated circuit for supplying the various voltages or the current to the display panel 101, gate driving circuit 120, and the data driving circuit 130 and controlling these voltages or the current

[0074] A voltage line for supplying various signals or voltages may be disposed in the display panel 101 in addition to the gate line GL and the data line DL, and the micro light emitting diode μLED and the transistor for driving thereof may be disposed in each sub pixel SP.

[0075] FIG. 2 shows an example of the circuit structure of the sub pixel SP of the LED display apparatus 100 according to embodiments of the present invention, wherein one pixel P includes three sub pixels SP.

[0076] Referring to FIG. 2, in addition to the gate line GL for supplying the scan signal and the data line DL for supplying data voltage Vdata, a driving voltage line DVL for supplying the driving voltage Vdd and a common voltage line CVL for supplying the common voltage Vcom may be disposed in the display panel 101.

[0077] Further, the sub pixels SP displaying red (R), green (G), and blue (B) colors are disposed in the intersection region of the gate line GL and the data line DL.

[0078] In each pixel SP, the micro light emitting diode μLED, one or more transistors for driving the micro light emitting diode μLED, and the capacitors may be disposed.

[0079] For example, the micro light emitting diode μLED for emitting red light, a first driving transistor DRT1 for driving the micro light emitting diode μLED, and a first switching transistor SWT1 for controlling a driving timing of the first driving transistor DRT1 may be disposed in the red sub pixel SP(R) at the intersect region of the first data line DL1 and the gate line GL.

[0080] Here, the first driving transistor DRT1 may be connected to the anode electrode of the micro light emitting diode μLED as shown in FIG. 2, but may also be connected to the cathode electrode of the micro light emitting diode μLED.

[0081] And, the storage capacitor for maintaining the data voltage Vdata for one image frame may be further disposed between the gate electrode and the source electrode (or drain electrode) of the first driving transistor DRT1.

[0082] When the scan signal Scan is applied through the gate line GL, the first switching transistor SWT1 is turned on, and then the first data voltage Vdata1 supplied through the first data line DL is applied to the gate electrode of the first driving transistor DRT1. Further, the driving voltage Vdd is applied to the anode electrode of the micro light emitting diode μLED according to the first data voltage Vdata1 and the common voltage Vcom is applied to the cathode electrode of the micro light emitting diode μLED. A micro light emitting diode (μLED) emits light according to the difference of the voltages applied to the anode electrode and the cathode electrode to express brightness.

[0083] The micro light emitting diodes μLEDs disposed in the green sub pixel SP(G) and the blue sub pixel SP(B) are driven in the same manner to display green (G) and blue (B) colors in the corresponding sub pixels SP.

[0084] Meanwhile, each of the micro light emitting diodes μLED disposed in the red sub pixel SP(R), the green sub pixel SP(G), and the blue sub pixel SP(B) are grown on separate wafer substrates corresponding thereto, and then the grown micro light emitting diodes μLED are transferred and positioned on the display panel 101.

[0085] Hereinafter, the configuration of the common electrode layer integrated micro light emitting diode μLED according to the embodiment of the present specification in which the number of micro light emitting diodes μLED grown on separate wafer substrates is minimized will be described in detail.

[0086] FIG. 3 is the schematic cross-sectional view for explaining the structure of the pixel of the LED display apparatus 100 according to the embodiment of the present specification. Referring to FIG. 3, the display panel 101 of the LED display apparatus 100 may include a first substrate 110a and a second substrate 110b.

[0087] The first substrate 110a includes a first light emitting device 160 and a second light emitting device 170 that are micro light emitting diodes μLED. The first light emitting device 160 is integral with the common electrode layer 160a, and one unit pixel P may include at least one first light emitting device 160. Meanwhile, the second light emitting device 170 is the micro light emitting diode that is grown on the separate semiconductor substrate and then transferred onto the common electrode layer 160a through the transfer process, and one unit pixel P may include at least one second light emitting device 170.

[0088] The second substrate 110b facing the first substrate 110a on which the micro light emitting diode is disposed includes a first pixel driving device 150a and a second pixel driving device 150b that are driving transistors.

[0089] The first substrate 110a and the second substrate 110b may be separately manufactured and bonded to each other, and an adhesive layer such as resin may be filled between the first substrate 110a and the second substrate 110b to bond the first substrate 110a and the second substrate 110b.

[0090] Hereinafter, each structure disposed on the first substrate 110a and the second substrate 110b will be described in more detail.

[0091] A common electrode layer 160a is disposed on the first substrate 110a. The first substrate 110a is a substrate such as sapphire on which the semiconductor layer can be substantially grown, and may further include a buffer layer for growing the semiconductor layer.

[0092] Further, the buffer layer is a low-temperature buffer layer which may be formed of material such as AlN or low-temperature GaN. The common electrode layer 160a on the first substrate 110a is an n-type semiconductor layer in which silicon (Si) is doped. As described above, the n-type semiconductor layer doped with silicon can form the common electrode layer 160a as a conductor.

[0093] The first light emitting device 160 is disposed on the common electrode layer 160a. The first light emitting device 160 has a structure in which a GaN-based compound semiconductor is grown in the form of a pn junction diode, each layer is a layer grown by inheriting the crystallinity of the underlying layer, and the first light emitting device 160 includes a first n-type semiconductor layer 161, a first active layer 162, a first p-type semiconductor layer 163, and a first device electrode 164a on the first p-type semiconductor layer 163.

[0094] As described above, since the first light emitting device 160 is sequentially grown (epi-growth) from the common electrode layer 160a on the first substrate 110a, a separate transferring process onto the common electrode layer 160a is not necessary.

[0095] Meanwhile, the second light emitting device 170 is disposed on the common electrode layer 160a. The unit pixel P is composed of at least one sub pixel SP, and each sub pixel SP is configured to emit the light of different wavelengths.

[0096] The second light emitting device 170 is the light emitting device that emits light having the wavelength different from that of the first light emitting device 160, and is grown on a separate semiconductor growth substrate (e.g., semiconductor substrate) and then disposed on the common electrode layer 160a through the transferring process.

[0097] However, in another embodiment of the present invention, the method of configuring the unit pixel P only with the plurality of first light emitting devices 160 may be used without the second light emitting device 170 grown on the separate semiconductor growth substrate, and in this case a color conversion layer corresponding to each of the first light emitting devices 160 may be further included. If the light emitting device grown on the separate semiconductor growth substrate is not used, the transferring process for transferring the light emitting device may not be required at all.

[0098] The first light emitting device 160 may be the light emitting device grown according to the lattice constant of the first substrate 110a based on the sapphire substrate, and the second light emitting device 170 may be the light emitting device grown on the separate semiconductor growth substrate base on the gallium arsenide (GaAs) substrate.

[0099] The second light emitting device 170 includes a second n-type semiconductor layer 171, a second active layer 172, a second p-type semiconductor layer 173, and a second device electrode 174a on the second p-type semiconductor layer 173, a third device electrode 175a may be formed on the first n-type semiconductor layer 171 to connect electrically the second light emitting device 170 to the common electrode layer 160a, and the second light emitting device 170 may be fixed on the common electrode layer 160a by a adhesive layer adh.

[0100] The second light emitting device 170 is electrically connected to the common electrode layer 160a through the third connection electrode 175, and the third connection electrode 175 may include the third device electrode 175a disposed on the first n-type semiconductor layer 171 and a third bonding electrode 175b including a conductive ball.

[0101] Meanwhile, the common electrode layer 160a may further include a light guide 180 to prevent color mixing of the light emitted from each of the first light emitting device 160 and the second light emitting device 170. The light guide 180 may be formed of an opaque conductive metal or the like for reflecting light, and may be formed by etching the surface of the common electrode layer 160a and then disposing above described metal in the etched surface.

[0102] In addition, a black matrix BM may be disposed between the first light emitting device 160 and the second light emitting device 170 to further prevent color mixing.

[0103] In the above configuration, although each of the first n-type semiconductor layer 161, the second n-type semiconductor layer 171, the first p-type semiconductor layer 163, and the second p-type semiconductor layer 173 are formed in the n-type semiconductor layer and p-type semiconductor layer, these layers may be formed in the p-type semiconductor layer and n-type semiconductor layer

[0104] The first p-type semiconductor layer 163 and the second p-type semiconductor layer 173 are respectively disposed on the first active layer 162 and the second active layer 172 to supply respectively holes to the first active layer 162 and the second active layer 172. The first p-type semiconductor layer 163 and the second p-type semiconductor layer 173 according to the embodiment of the present specification may be formed of a p-GaN based semiconductor material, and the p-GaN based semiconductor material includes GaN and AlGaN, InGaN, or AlInGaN. Here, as an impurity used for doping the first p-type semiconductor layer 163 and the second p-type semiconductor layer 173, Mg, Zn, Be, or the like may be used.

[0105] The first n-type semiconductor layer 161 and the second n-type semiconductor layer 171 are respectively disposed on the first active layer 162 and the second active layer 172 to supply respectively electrons to the first active layer 162 and the second active layer 172. The first n-type semiconductor layer 161 and the second n-type semiconductor layer 171 according to the embodiment of the present specification may be formed of a-GaN based semiconductor material, and the n-GaN based semiconductor material includes GaN and AlGaN, InGaN, or AlInGaN. Here, as an impurity used for doping the first n-type semiconductor layer 161 and the second n-type semiconductor layer 171, Si, GE, Se, Te, C or the like may be used.

[0106] The first active layer 162 and the second active layer 172 are disposed on the first n-type semiconductor layer 161 and the second n-type semiconductor layer 171. The light emitting layers of the first active layer 162 and the second active layer 172 include a multi quantum well (MQW) structure having a well layer and a barrier layer having a higher band gap than the well layer. The first active layer 162 and the second active layer 172 according to the embodiment of the present invention may include the multi-quantum well structure such as InGaN/GaN.

[0107] Each of the first device electrode 164a, the second device electrode 174a, and the third device electrode 175a according to the embodiment of the present invention may be made of metal such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti. or Cr and an alloy including one or more of these metal, but is not limited thereto.

[0108] As described above, according to the exemplary embodiment of the present specification, the second substrate 110b includes the first pixel driving device 150a and the second pixel driving device 150b that are driving transistor.

[0109] Each of the first pixel driving device 150a and the second pixel driving device 150b includes an active layer 151, a gate electrode 152, a source electrode 153, and a drain electrode 154. Each of the first pixel driving device 150a and the second pixel driving device 150b according to the embodiment of the present specification is the thin film transistor using a poly silicon material as the active layer 151, that is, a low temperature poly silicon (LTPS) thin film transistor using low temperature poly silicon.

[0110] Since the poly silicon material has high mobility, energy consumption is low and reliability is excellent. The active layer 151 of the LTPS thin film transistor (hereinafter, the thin film transistor, the first pixel driving device 150a and the second pixel driving device 150b) includes a channel region 151a, in which a channel is formed when the thin film transistor is driven, and a source and drain region 151b and 151c on both sides of the channel region 151a.

[0111] The channel region 151a, the source region 151b, and the drain region 151c are defined by ion doping (impurity doping). A gate insulating layer 111 is disposed on the active layer 151, and the gate insulating layer 111 can be composed of a single layer such as silicon nitride (SiNx) or silicon oxide (SiOx), or multi layers including silicon nitride (SiNx) and silicon oxide(SiOx).

[0112] On the gate insulating layer 111, the gate electrode 152 is disposed so as to overlap the channel region 151a of the active layer 151. The gate electrode 152 may formed in a single layer structure made of any one of aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), and molybdenum titanium (MoTi) having low resistance characteristics, the gate electrode 152 may formed in a double layer structure or triple layer structure composed of two or more layers.

[0113] Further, the first insulating layer 112 is disposed on the gate electrode 152, hydrogen contained in the first insulating layer 112 made of silicon nitride (SiNx) is diffused into the active layer 151 during a hydrogenation process for stabilizing the active layer 151 since the first insulating layer 112 is made of the silicon nitride (SiNx).

[0114] A passivation layer 113 is disposed on the first insulating layer 112, the passivation layer 113 may be made of the same material as the first insulating layer 112 or may be made of the organic insulating material for planarization.

[0115] For example, the passivation layer 113 may be made of one and more of materials such as polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, poly-phenylenethers resin, polyphenylenesulfides resin, and benzocyclobutene, but is not limited thereto. The passivation layer 117 may be formed as a single layer, double layers, or multiple layers.

[0116] A source electrode 153 and a drain electrode 154 connected to the source region 151b and the drain region 151c, respectively, are disposed on the first insulating layer 112. The source electrode 153 and the drain electrode 154 are made of any one or two or more materials of low resistance properties such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum titanium (MoTi), chromium (Cr), and titanium (Ti).

[0117] First and second pixel electrodes 155a and 155b are disposed on the passivation layer 113. The first and second pixel electrodes 155a and 155b may be formed of the metal having high reflectance, such as a stacked structure of aluminum (Ti) and titanium (Ti) (Ti/Al/Ti), a stacked structure of aluminum (Al) and ITO (ITO/Al/ITO), an APC alloy (Ag/Pd/Cu), and a stacked structure of an APC alloy and ITO (ITO/APC/ITO).

[0118] In the above description, a first connection electrode 164 may be disposed on the first light emitting device 160 for electrical connection with the first pixel driving device 150a. The first connection electrode 164 may include the first device electrode 164a and the first bonding electrode 164b including the conductive ball, and is electrically connected to the first pixel electrode 155a so as to be connected electrically to the first pixel driving device 150a.

[0119] In the above description, a second connection electrode 174 may be disposed on the second light emitting device 170 for electrical connection with the second pixel driving device 150b. The second connection electrode 174 may include the second device electrode 174a and the second bonding electrode 174b including the conductive ball, and is electrically connected to the second pixel electrode 155b so as to be connected electrically to the first pixel driving device 150a.

[0120] FIG. 4 is a schematic flowchart for explaining the method of manufacturing the LED display apparatus 100 according to the embodiment of the present specification.

[0121] The first substrate may be the sapphire wafer substrate on which the semiconductor may be grown. After the nGaN based common electrode layer is formed on the first substrate, the first light emitting device including the first n-type semiconductor layer, the first active layer, and the first p-type semiconductor layer is continuously epi-grown on the first substrate (S110). The first light emitting device may be configured as an individual light emitting device by etching the epitaxially grown semiconductor layer. In this case, the buffer layer for buffering the lattice constant may be further formed on the first substrate.

[0122] Meanwhile, the first pixel driving device and the second pixel driving device are disposed on the second substrate (S120). The first pixel driving device and the second pixel driving device are thin film transistors, and are disposed to be electrically connected to the driving circuit for driving the pixel.

[0123] Subsequently, the second light emitting device including the second n-type semiconductor layer, the second active layer, and the second p-type semiconductor layer is transferred onto the common electrode layer on the first substrate (S130). The second light emitting device, which may be the light emitting device grown on the separate semiconductor growth substrate, is disposed on the common electrode layer through the transferring process, and in this case the step of disposing and bonding an adhesive layer and connection electrode may be further included.

[0124] Subsequently, the first and second substrates are bonded to each other (S140), the first p-type semiconductor layer and the first pixel driving device are electrically connected by disposing the first connection electrode and the second p-type semiconductor layer and the second pixel driving device are electrically connected by disposing the second connection electrode when the first substrate and the second substrate are bonded to each other (S150), thereby the LED display apparatus is manufactured. As described above, it is possible to provide the method of manufacturing the LED display apparatus in which the transferring process for transferring the light emitting device is minimized by using the method in which the common electrode layer and the first light emitting device are grown on the first substrate to use as the light emitting device.

[0125] Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.