Bypass techniques to protect noise sensitive circuits within integrated circuit chips

Abstract

Bypass techniques are provided herein to protect noise sensitive circuits from both internal and external noise sources. According to one embodiment, an integrated circuit (IC) chip may include a noise sensitive circuit coupled between a power supply pad and a first ground pad of the IC chip. In order to protect the first ground pad of the noise sensitive circuit, two distinct bypass paths are provided to route noise current around the noise sensitive circuit. Each bypass path terminates in its own ground pad (e.g., a second ground pad and third ground pad), which is separate from the first ground pad of the noise sensitive circuit.

Claims

1. An integrated circuit (IC) chip, comprising: a circuit coupled between a power supply pad and a first ground pad of the IC chip; a first bypass path coupled between the power supply pad and a second ground pad of the IC chip, the first bypass path providing a path for noise current around the circuit; and a second bypass path coupled between the power supply pad and a third ground pad of the IC chip, the second bypass path providing a path for noise current around the circuit; wherein the second and third ground pads are separate from the first ground pad.

2. The integrated circuit chip as recited in claim 1, wherein the IC chip further comprises an additional circuit coupled to the circuit, the additional circuit being a source of the noise current, which is generated within the IC chip and routed around the circuit via the first and second bypass paths.

3. The integrated circuit chip as recited in claim 1, wherein the first and second bypass paths each comprise a low impedance circuit, which is configured to present a low impedance to the noise current.

4. The integrated circuit chip as recited in claim 3, wherein the second and third ground pads of the IC chip are configured to be coupled to a ground conductor on a printed circuit board by separate bond wires, and wherein the low impedance provided by the low impedance circuits is at least 10 times less than an impedance of the bond wires.

5. The integrated circuit chip as recited in claim 3, further comprising a high impedance circuit, which is coupled between the first and second bypass paths and coupled in series between the power supply pad and a power supply input of the circuit, wherein the high impedance circuit is configured to present a high impedance to the noise current.

6. The integrated circuit chip as recited in claim 5, wherein the high impedance provided by the high impedance circuit is about 10 times to about 100 times larger than the low impedance provided by the low impedance circuits.

7. The integrated circuit chip as recited in claim 5, wherein the low impedance circuit of the first bypass path comprises a first capacitor coupled between a first node of the high impedance circuit and the second ground pad, and wherein the low impedance circuit of the second bypass path comprises a second capacitor coupled between a second node of the high impedance circuit and the third ground pad.

8. The integrated circuit chip as recited in claim 7, wherein the high impedance circuit is coupled between the first and second capacitors, and comprises a resistor or an inductor.

9. The integrated circuit chip as recited in claim 7, wherein the low impedance circuit of the first bypass path further comprises a first inductor coupled in series with the first capacitor to form a first LC resonant circuit, and wherein the low impedance circuit of the second bypass path further comprises a second inductor coupled in series with the second capacitor to form a second LC resonant circuit.

10. The integrated circuit chip as recited in claim 9, wherein the high impedance circuit is coupled between the first and second LC resonant circuits, and wherein the high impedance circuit comprises a third inductor coupled in parallel with a third capacitor to form a third LC resonant circuit.

11. An electronic system, comprising: a printed circuit board having at least one power conductor and at least one ground conductor; at least one integrated circuit (IC) chip mounted onto the printed circuit board, wherein the at least one IC chip comprises: a power supply pad coupled to the at least one power conductor; a first ground pad, a second ground pad and a third ground pad, each separately coupled to the at least one ground conductor; a circuit coupled between the power supply pad and the first ground pad; a first bypass path coupled between the power supply pad and the second ground pad, the first bypass path providing a path for noise current around the circuit to the second ground pad; and a second bypass path coupled between the power supply pad and the third ground pad, the second bypass path providing a path for noise current around the circuit to the third ground pad.

12. The electronic system as recited in claim 11, wherein the IC chip further comprises an additional circuit coupled to the circuit, the additional circuit being a source of noise current within the IC chip.

13. The electronic system as recited in claim 12, wherein the additional circuit comprises a voltage regulator coupled between the power supply pad and a power supply input of the circuit, and wherein the voltage regulator generates at least a portion of the noise current.

14. The electronic system as recited in claim 12, wherein the first bypass path is coupled between an output of the additional circuit and the second ground pad, and wherein the second bypass path is coupled between the power supply input of the circuit and the third ground pad.

15. The electronic system as recited in claim 14, wherein the first and second bypass paths each comprise a low impedance circuit, which is configured to present a low impedance to the noise current.

16. The electronic system as recited in claim 15, wherein the IC chip further comprises a high impedance circuit, which is coupled between the first and second bypass paths, coupled in series between the output of the additional circuit and the power supply input of the circuit, and configured to present a high impedance to the noise current.

17. The electronic system as recited in claim 16, wherein the high impedance provided by the high impedance circuit is about 10 times to about 100 times larger than the low impedance provided by the low impedance circuits.

18. The electronic system as recited in claim 16, wherein the second and third ground pads are coupled to the at least one ground conductor of the printed circuit board by separate bond wires, and wherein the low impedance provided by the low impedance circuits is at least 10 times less than an impedance of the bond wires.

19. The electronic system as recited in claim 16, wherein the low impedance circuit of the first bypass path comprises a first capacitor coupled between a first node of the high impedance circuit and the second ground pad, and wherein the low impedance circuit of the second bypass path comprises a second capacitor coupled between a second node of the high impedance circuit and the third ground pad, and wherein the high impedance circuit is coupled between the first and second capacitors, and comprises a resistor or an inductor.

20. The electronic system as recited in claim 19, wherein the low impedance circuit of the first bypass path further comprises a first inductor coupled in series with the first capacitor to form a first LC resonant circuit, and wherein the low impedance circuit of the second bypass path further comprises a second inductor coupled in series with the second capacitor to form a second LC resonant circuit.

21. The electronic system as recited in claim 20, wherein the high impedance circuit is coupled between the first and second LC resonant circuits, and wherein the high impedance circuit comprises a third inductor coupled in parallel with a third capacitor to form a third LC resonant circuit.

22. The electronic system as recited in claim 11, wherein the IC chip comprises a radio frequency (RF) or analog front end, and wherein the circuit comprises a single-ended amplifier.

23. The electronic system as recited in claim 22, wherein the circuit comprises a single-ended Low Noise Amplifier (LNA).

24. A method to bypass noise in an integrated circuit (IC) chip, comprising: operating an integrated circuit (IC) chip, the IC chip including a circuit coupled between a power supply pad and a first ground pad of the IC chip, a first bypass path coupled between the power supply pad and a second ground pad of the IC chip, and a second bypass path coupled between the power supply pad and a third ground pad of the IC chip; receiving noise current associated with operation of the IC chip; and bypassing the noise current around the circuit using the first bypass path and the second bypass path.

25. The method as recited in claim 24, further comprising operating an additional circuit coupled to the circuit within the IC chip, the additional circuit being a source of the noise current.

26. The method as recited in claim 24, wherein the first and second bypass paths each comprise a low impedance circuit, which is configured to present a low impedance to the noise current.

27. The method as recited in claim 26, wherein the second and third ground pads of the IC chip are configured to be coupled to a ground conductor on a printed circuit board by separate bond wires, and wherein the low impedance provided by the low impedance circuits is at least 10 times less than an impedance of the bond wires.

28. The method as recited in claim 26, wherein the IC chip further comprises a high impedance circuit coupled between the first and second bypass paths and coupled in series between the power supply pad and a power supply input of the circuit, wherein the high impedance circuit is configured to present a high impedance to the noise current.

29. The method as recited in claim 28, wherein the high impedance provided by the high impedance circuit is about 10 times to about 100 times larger than the low impedance provided by the low impedance circuits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other objects and advantages of the inventions will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.

(2) FIG. 1 (Prior Art) is a block diagram illustrating an exemplary electronic system including a plurality of integrated circuit (IC) chips mounted onto a printed circuit board (PCB), wherein each IC chip is provided with an external bypass capacitor for protecting the IC chip from some external noise sources;

(3) FIG. 2 (Prior Art) is a block diagram illustrating IC chip 20 and external bypass capacitor 70 of the electronic system shown in FIG. 1, further illustrating a conventional bypass technique commonly used to protect noise sensitive circuits residing within the IC chip from internal and/or external noise sources;

(4) FIG. 3 illustrates a general embodiment of an improved bypass technique disclosed herein to protect noise sensitive circuits residing within IC chip 20 from internal and/or external noise sources;

(5) FIG. 4 illustrates a first embodiment for improved bypass circuitry that may be used to protect a particular noise sensitive circuit (e.g., a single-ended, common source, CMOS Low Noise Amplifier, LNA) residing with IC chip 20 from internal and/or external noise sources;

(6) FIG. 5 illustrates a second embodiment for improved bypass circuitry that may be used to protect a noise sensitive circuit residing with IC chip 20 from internal and/or external noise sources;

(7) FIG. 6 illustrates a third embodiment for improved bypass circuitry that may be used to protect a noise sensitive circuit residing with IC chip 20 from internal and/or external noise sources; and

(8) FIG. 7 illustrates a fourth embodiment for improved bypass circuitry that may be used to protect a noise sensitive circuit residing with IC chip 20 from internal and/or external noise sources.

(9) While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the present disclosure to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(10) FIGS. 3-7 illustrate exemplary embodiments of improved bypass techniques that may be included within an integrated circuit to protect noise sensitive circuits from both internal and external noise sources. As used herein, an internal noise source is one which originates from within an electronic circuit (e.g., an integrated circuit chip) comprising the noise sensitive circuit. Likewise, an external noise source is one that originates from outside of the electronic circuit. Non-limiting examples of internal noise sources include thermal noise of a linear regulator supplying the noise sensitive circuit, and clock spurs due to switching regulators and/or switched bias circuits. Non-limiting examples of external noise sources include thermal noise and escape currents (due to clock and/or data activity) from other on-chip circuits connected to the power supply pad. Although power supply and ground noise are discussed herein as examples of external noise sources, and thermal noise generated across a voltage regulator is provided as an example of an internal noise source, it is understood that the improved bypass circuit embodiments described herein could be used to protect a noise sensitive circuit from many other types of internal and external noise sources. As such, the noise sources discussed herein are provided merely for illustrative purposes.

(11) A circuit whose performance is significantly affected and/or degraded by noise generated by other on-chip circuits and/or external sources may be referred to herein as a noise sensitive circuit. A noise sensitive circuit may encompass many different types of circuits, which may be used to receive, condition, and/or amplify relatively small signals, including but not limited to, signals in the microvolts to millivolts range. Non-limiting examples of noise sensitive circuits include low-level analog circuits (including but not limited to amplifiers, analog-to-digital converters, and sensors), wireless receivers (including but not limited to GSM, CDMA, LTE, Bluetooth, GPS, Wi-Fi, HD/FM radio, and satellite receivers) and wireline receivers (including but not limited to cable TV receivers, cable modems and disk drive read circuits).

(12) According to one exemplary embodiment, a noise sensitive circuit may be a single-ended, common-source, CMOS Low-Noise Amplifier (LNA), which is configured for operation in the GHz frequency range (e.g., about 1-10 GHz), as shown in FIG. 4 and discussed in more detail below. In such an embodiment, the electronic circuit (or IC chip) containing the LNA may be a low-noise radio frequency (RF) amplifier front-end. However, the embodiments disclosed herein are not strictly limited to any particular noise sensitive circuit, or any particular operating frequency range. Furthermore, the embodiments disclosed herein may be implemented within other types of electronic circuits (or IC chips), non-limiting examples of which include wireless receivers, wireline receivers, and sensor and analog front ends.

(13) FIG. 3 is a block diagram illustrating a portion 100 of an exemplary electronic system 10, similar to that shown in FIGS. 1-2 (Prior Art). In the exemplary system shown in FIG. 3, IC chip 20 and external bypass capacitor (C.sub.BYP.sub._.sub.EXT) 70 are coupled between a PCB power conductor 50 and PCB ground conductor 60. The power and ground conductors 50, 60 may include individual traces or planes, which are printed on and/or sandwiched between layers of a printed circuit board (PCB, not shown). As shown in FIG. 3, IC chip 20 may include a noise sensitive circuit 22, which is generally coupled between a power supply pad (V.sub.DD) 24 and a first ground pad (GND1) 26 of IC chip 20. The V.sub.DD pad 24 and GND1 pad 26 are respectively connected to PCB power and ground conductors 50 and 60 through some finite impedance (such as a bond wire).

(14) In some embodiments, an on-chip voltage regulator 28 may be coupled between V.sub.DD pad 24 and the power supply input of noise sensitive circuit 22 for regulating the supply voltage provided to circuit 22. In the illustrated embodiment, voltage regulator 28 represents an example of an internal noise source that may adversely affect noise sensitive circuit 22 by forwarding the thermal noise generated across the voltage regulator to the supply and ground inputs of the sensitive circuit. Although thermal noise across voltage regulator 28 is discussed herein, the disclosed bypass circuitry can also be used to protect noise sensitive circuit 22 from other types of noise (e.g., clock spurs) and/or from other types of internal noise sources (e.g., switching regulators and/or switched bias circuits). As such, voltage regulator 28 is included within IC chip 20 merely as an example of an internal noise source, and may not be included within IC chip 20 in all embodiments.

(15) As noted above, the most common approach for protecting a noise sensitive circuit from internal noise sources is to couple a relative large on-chip capacitor (e.g., C.sub.BYP.sub._.sub.IN 32, FIG. 2) between the output of the noise source (e.g., voltage regulator 28) and the GND1 pad 26 of the noise sensitive circuit to provide a bypass path for shunting noise current to ground. Unfortunately, this arrangement allows noise current to flow through the finite impedance connecting the GND1 pad 26 of the noise sensitive circuit 22 to the PCB ground conductor 60, thereby, creating voltage noise on the GND1 pad 26, as shown in FIG. 2. Since the input (IN) pad 34 of the noise sensitive circuit 22 is referenced directly to the PCB ground potential, any voltage noise on the GND1 pad 26 is interpreted as an input by the noise sensitive circuit. A portion of the noise current from external noise source(s) may also appear on the GND1 pad 26 by the same mechanism, and may also be seen as an input by the noise sensitive circuit. Depending on the type of noise sensitive circuit, voltage noise at the GND1 pad 26 may be amplified at the output (OUT) of the noise sensitive circuit, or may produce other undesirable results. Unfortunately, coupling a large on-chip bypass capacitor 32 as shown in FIG. 2 for bypassing the supply input of a circuit to the circuit's own GND1 pad 26 cannot be used to adequately protect noise sensitive circuits (e.g., single-ended amplifiers and receivers) from both internal and external noise sources.

(16) FIG. 3 illustrates an embodiment of an improved bypass technique that addresses problems associated with the conventional bypass circuits shown in FIGS. 1-2 by providing two distinct bypass paths 42, 44 for noise current to flow around noise sensitive circuit 22. Each bypass path terminates in its own ground pad 36, 38 (labeled GND2 and GND3), which is separate and distinct from the ground (GND1) pad 26 of the noise sensitive circuit 22. In some embodiments, the improved bypass circuitry may be implemented by adding two new ground pads 36 and 38 to the IC chip 20. GND1 pad 26 (i.e., a first ground pad), GND2 pad 36 (i.e., a second ground pad) and GND3 pad 38 (i.e., a third ground pad) are separately connected to PCB ground conductor 60 by some finite impedance (such as a bond wire). It is noted that the first, second and third ground pads may be connected to PCB ground conductor 60 in a variety of different ways (e.g., including direct bonding to a ground paddle within the package for the IC chip 20, bonded to one or more pins within the package for the IC chip 20, and/or other bonding techniques).

(17) The IC chip 20 shown in FIG. 3 includes a first bypass path 42 coupled between the output of voltage regulator 28 and the second (GND2) pad 36 for routing noise current around noise sensitive circuit 22 to the second ground pad, and a second bypass path 44 coupled between the supply input 25 of the noise sensitive circuit 22 and the third (GND3) pad 38 for routing noise current around the noise sensitive circuit 22 to the third ground pad. The noise current routed around noise sensitive circuit 22 by the first and second bypass paths 42, 44 may be generated by one or more internal noise sources residing within IC chip 20, and/or by one or more external noise sources residing outside of IC chip 20, yet coupled to the IC chip via a radiative and/or a conductive path. Examples of potential internal and external noise sources are discussed above. In the illustrated embodiment, voltage regulator 28 represents an example of an internal noise source that generates at least a portion of the noise currents. Since voltage regulator 28 is provided merely as an exemplary internal noise source, and not actually part of the bypass circuit embodiments disclosed herein, the voltage regulator may not be included in all embodiments of the IC chip. In such embodiments, bypass path 42 may be coupled to the output of another internal noise source, or may be coupled for receiving an unregulated supply voltage from the power supply pad 24.

(18) In the general embodiment shown in FIG. 3, a low impedance circuit 14, 16 (Z.sub.L1 and Z.sub.L2) is included within each bypass path 42, 44. A high impedance circuit 12 (Z.sub.H) is coupled between bypass paths 42 and 44, and coupled in series between the output of voltage regulator 28 and the power supply input 25 of the noise sensitive circuit 22. In general, the low impedance circuits 14, 16 (Z.sub.L1 and Z.sub.L2) are configured to present a low impedance, and the high impedance circuit 12 (Z.sub.H) is configured to present a high impedance, to the noise current (I.sub.noise) generated by the internal and external noise sources. Since the impedance of Z.sub.L1, Z.sub.L2, and Z.sub.H is frequency dependent, Z.sub.L1 and Z.sub.L2 should be configured to present a low impedance, and Z.sub.H should be configured to present a high impedance, at a frequency (or frequency range) of interest to the circuit designer. The noise frequencies of interest are generally dependent on the circuit being affected by noise (e.g., noise sensitive circuit 22). In circuits where noise is additive, the noise frequencies of interest may be similar to the frequency of the input (IN) signal received by the noise sensitive circuit 22. In circuits where noise is multiplicative, the noise frequency of interest may be different from the input signal frequency. One skilled in the art would understand how to determine the noise frequencies of interest for a particular circuit design, and how to configure a low impedance circuit and a high impedance circuit for the noise frequencies of interest.

(19) Although example impedances are discussed below for an exemplary GHz frequency range, the bypass circuit embodiments described herein is not limited to any particular frequency or frequency range. As such, the impedances of the Z.sub.L1, Z.sub.L2, and Z.sub.H circuits may be more accurately described as a ratio or multiple of one another. In one example, the high impedance provided by the high impedance circuit 12 (Z.sub.H) may be about 10 times to about 100 times larger than the low impedance provided by the low impedance circuits 14, 16 (Z.sub.L1 and Z.sub.L2). In some cases, the impedance of the low impedance circuits (Z.sub.L1 and Z.sub.L2) may also be dependent on the finite impedance connecting IC chip 20 to ground. In one example, the low impedance provided by the low impedance circuits (Z.sub.L1 and Z.sub.L2) may be at least 10 times less than the impedance (e.g., +j1 to +j100 ohms at commonly used RF frequencies) of the respective bond wires connecting the GND2 and GND3 pads to PCB ground conductor 60.

(20) With the improved bypass circuitry shown in FIG. 3, noise current (I.sub.X) generated by both internal and external noise sources is split between GND2 pad 36 and GND3 pad 38 according to the equations below:

(21) $\begin{array}{cc}{I}_{\mathrm{GND}2}=I_X\frac{Z_H+Z_{L2}}{Z_H+Z_{L2}+Z_{L1}}& \mathrm{EQ}.1\end{array}$

(22) $\begin{array}{cc}{I}_{\mathrm{GND}3}=I_X\frac{Z_{L1}}{Z_H+Z_{L2}+Z_{L1}}& \mathrm{EQ}.2\end{array}$
As evidenced by EQ. 1 and EQ. 2, a majority of the noise current (I.sub.GND2) will flow through the first bypass path 42 (and Z.sub.L1) to GND2 pad 36, while a smaller fraction of the noise current (I.sub.GND3) flows through the second bypass path 44 (and Z.sub.L2) to GND3 pad 38. This prevents voltage noise from appearing at the GND1 pad 26 of the noise sensitive circuit 22, and instead, pushes it out to the GND2 pad 36 and to the GND3 pad 38 (albeit to a smaller extent). It is noted that noise on the GND1 pad 26 of the noise sensitive circuit 22 looks like an input to the noise sensitive circuit, whereas noise on GND2 pad 36 and GND3 pad 38 does not. In this manner, the improved bypass circuitry prevents noise from appearing at the GND1 pad 26 of the noise sensitive circuit.

(23) Although illustrated as generic impedances in FIG. 3, it will be understood that the low impedance circuits 14, 16 (Z.sub.L1 and Z.sub.L2) and the high impedance circuit 12 (Z.sub.H) may be implemented in a variety of different ways. FIGS. 4-7 illustrate various embodiments of the bypass techniques described herein. A first embodiment of the bypass circuitry shown generically in FIG. 3 is illustrated in FIG. 4. In the first embodiment, the low impedance circuit 14 within bypass path 42 includes a first capacitor (C.sub.L1) coupled between a first node of the high impedance circuit 12 and GND2 pad 36, the low impedance circuit 16 within bypass path 44 includes a second capacitor (C.sub.L2) coupled between a second node of the high impedance circuit 12 and GND3 pad 38, and the high impedance circuit 12 includes a resistor (R.sub.H), which is coupled between the first and second capacitors. In one example, the resistor (R.sub.H) included within high impedance circuit 12 may be selected to provide a relatively high impedance of about 10 to about 1000.

(24) A second embodiment 200 of the bypass techniques described herein is illustrated in FIG. 5. In the second embodiment, the high impedance circuit 12 may be implemented with an inductor (L.sub.H), instead of a resistor (R.sub.H), when the noise sensitive circuit 22 is configured for operating at higher operating frequencies. In one example, an inductor with an inductance of about 1 nH to about 100 nH may be used in the second embodiment to provide a relatively high impedance at higher operating frequencies (including, but not limited to, GHz frequencies). In the second embodiment, an inductor may be preferred over a resistor, since inductors typically require less voltage headroom than resistors to achieve the same amount of filtering at higher operating frequencies. However, since inductors consume more area than resistors, the second embodiment may only be preferred when voltage headroom is a concern and operating frequencies are high (e.g., GHz frequencies).

(25) In the first and second embodiments illustrated in FIGS. 4 and 5, the capacitance of the first and second capacitors (C.sub.L1 and C.sub.L2) for the low impedance circuits 14, 16 may be selected to present a relatively low impedance to the noise current at the noise frequency (or frequencies) of interest. As noted above, the noise frequency (or frequency range) of interest is generally dependent on the circuit being affected by the noise current. In some embodiments, the noise frequency (or frequency range) may be similar to the operating frequency (or frequency range) of the noise sensitive circuit 22, while in other embodiments, the noise frequency range may be different.

(26) In the first and second embodiments, the capacitance of the first and second capacitors (C.sub.L1 and C.sub.L2) is selected to present a relatively low impedance to the noise current at the operating frequency range of the noise sensitive circuit 22. As known in the art, capacitive reactance (i.e., the imaginary part of impedance) is inversely proportional to both capacitance and frequency, according to the equation below.

(27) $\begin{array}{cc}{X}_c=\frac{1}{2\mathrm{fC}}& \mathrm{EQ}.3\end{array}$

(28) In EQ. 3, X.sub.c is the capacitive reactance, C is the capacitance and f is the frequency of operation of the noise sensitive circuit. When noise sensitive circuit 22 is configured for operation in a GHz frequency range (e.g., about 2.4 GHz to about 2.6 GHz), the first and second capacitors (C.sub.L1 and C.sub.L2) may be implemented with 1 pF to 1 nF capacitors to present a relatively low impedance of about 1-10 to the noise current. Selecting the capacitance based on the operating frequency of the noise sensitive circuit enables noise current frequencies similar to the operating frequency of the noise sensitive circuit to be routed around the noise sensitive circuit via the first and second bypass paths 42, 44.

(29) A third embodiment 300 of the bypass techniques described herein is illustrated in FIG. 6. In the third embodiment, the low impedance circuits 14, 16 within bypass paths 42, 44 are implemented with capacitors (C.sub.L1 and C.sub.L2), while the high impedance circuit 12 is implemented with a resistor or an inductor (depicted generically as Z.sub.H). Unlike the first and second embodiments, the capacitance of the first and second capacitors (C.sub.L1 and C.sub.L2) is selected in the third embodiment to present a relatively low impedance to the noise current at a frequency range, which differs from the operating frequency range of the noise sensitive circuit 22.

(30) For example, the capacitance of the first and second capacitors (C.sub.L1 and C.sub.L2) may be chosen, in the third embodiment, to resonate with the inductance (L.sub.BW2 and L.sub.BW3) of the bond wires 15, 17 connecting GND2 pad 36 and GND3 pad 38 to the PCB ground conductor 60. In this embodiment, the series LC resonance provided by each capacitor (C.sub.L1 and C.sub.L2) and ground bond wire inductance (L.sub.BW2 and L.sub.BW3) creates a very low impedance, which depends on the package and bond wire geometry. More specifically, the inductive reactance is proportional to the inductance of the bond wires and the resonant frequency of the LC resonant circuit, according to the equation below.
X.sub.L=2fLEQ. 4
In EQ. 4, X.sub.L is the inductive reactance, L is the inductance of the ground bond wires and f is frequency. As known in the art, resonance occurs in a series LC resonant circuit when:
X.sub.L=X.sub.cEQ. 5
Since the inductance (L.sub.BW2 and L.sub.BW3) of the bond wires is known and dependent on the geometry of the bond wires used to connect the GND2 and GND3 pads to the PCB ground conductor, the capacitance of the first and second capacitors (C.sub.L1 and C.sub.L2) may be chosen in the third embodiment, according to EQS. 3-5 above, and the frequency f can be set to the operating frequency of the noise sensitive circuit or any other desired frequency of interest. In one example, the first and second capacitors may be implemented with 0.1 pF to 100 pF capacitors when the ground bond wire inductances range between about 0.1 nH to about 10 nH to present a relatively low impedance of about 0.1 to about 10 to the noise current.

(31) A fourth embodiment 400 of the bypass techniques described herein is illustrated in FIG. 6. In the fourth embodiment, the low impedance circuits 14, 16 may be implemented with series LC resonant circuits (L.sub.L1C.sub.L1 and L.sub.L2C.sub.L2), and the high impedance circuit 2 may be implemented with a parallel LC resonant circuit (L.sub.H//C.sub.H). Specifically, the low impedance circuit 14 within bypass path 42 may include a first inductor (L.sub.L1) coupled in series with the first capacitor (C.sub.L1) to form a first LC resonant circuit, which is coupled in series with GND2 pad 36. The low impedance circuit 16 within bypass path 44 may include a second inductor (L.sub.L2) coupled in series with the second capacitor (C.sub.L2) to form a second LC resonant circuit, which is coupled in series with GND3 pad 38. The high impedance circuit 12 may include a third inductor (L.sub.H) coupled in parallel with a third capacitor (C.sub.H) to form a third LC resonant circuit, which is coupled between bypass paths 42 and 44.

(32) In the fourth embodiment, the first, second and third LC resonant circuits may each be tuned to the operating frequency of the noise sensitive circuit 22, which enables noise current frequencies similar to the operating frequency of the noise sensitive circuit to be routed around the noise sensitive circuit via the bypass paths 42, 44. In one example, the first and second capacitors (C.sub.L1 and C.sub.L2) may be implemented with 50 fF to 5 pF capacitors, and the first and second inductors (L.sub.L1 and L.sub.L2) may be implemented with 100 nH to 1 nH inductors, to present a relatively low impedance of about 1 to about 100 to the noise current when noise sensitive circuit 22 is configured for operating in a GHz frequency range (e.g., about 2.4 GHz to about 2.6 GHz). In such an example, the third capacitor (C.sub.H) may be implemented with a 50 fF to 5 pF capacitor, and the third inductor (L.sub.H) may be implemented with a 100 nH to 1 nH inductor, to present a relatively high impedance of about 10 to about 1000 to the noise current in the same frequency range.

(33) Although the fourth embodiment has the potential for providing bypass paths 42 and 44 with near zero impedances, it does so over a narrow frequency range. In addition, inductors used in the first, second and third LC resonant circuits increase the area consumed by the Z.sub.L1, Z.sub.L2 and Z.sub.H circuits. For this reason, the embodiment as illustrated in FIG. 4 may be preferred, in at least one embodiment, so as to reduce costs, free up board space, avoid the use of on-chip inductors and improve the frequency response.

(34) In the embodiment shown in FIG. 4, noise sensitive circuit 22 is a single-ended, common-source, CMOS Low Noise Amplifier (LNA) operating in a GHz frequency range. In this particular embodiment, source terminals of the NMOS and PMOS transistors need to be protected against noise sources, such as but not limited to the exemplary internal and external noise sources shown in FIG. 4 and discussed above. In order to do so, a first bypass path 42 having a relatively low impedance is coupled between the output of voltage regulator 28 and GND2 pad 36, and a second bypass path 44 having a relative low impedance is coupled between the power supply input of LNA 22 and GND3 pad 38. In addition, a high impedance circuit 12 is coupled between the first and second bypass paths 42, 44, and further coupled in series between the output of voltage regulator 28 and the power supply input of LNA 22.

(35) In the illustrated embodiment, on-chip capacitors (C.sub.L1 and C.sub.L2) are used within the first and second bypass paths 42, 44 to implement the low impedance circuits 14, 16, and a resistor (R.sub.H) is used to implement the high impedance circuit 12, which is coupled between bypass paths 42 and 44. In one example, the on-chip capacitors (C.sub.L1 and C.sub.L2) may be implemented with 1 pF to 1 nF capacitors to provide a relatively low impedance of about 100 to about 0.1 to the noise current, and resistor (R.sub.H) may be configured to provide a relatively high impedance of about 10 to about 1000 to the noise current, when LNA 22 is configured for operation at about 2.4 GHz. Other values of capacitance and resistance may be used at other operating frequencies.

(36) As shown in FIG. 4, the source terminal of the NMOS input device of the LNA is connected to GND1 pad 26, while the source terminal of the PMOS device is bypassed to GND3 pad 38 through capacitor C.sub.L2. The output of the voltage regulator 28 is bypassed to GND2 pad 36 through capacitor C.sub.L1. With this arrangement, the noise current generated by internal and external noise sources is divided among the first and second bypass paths 42 and 44 according to EQS. 1 and 2 above. Thus, noise current is largely diverted to GND2 pad 36 by the combined action of R.sub.H and C.sub.L1. A much smaller fraction of the noise current bypasses LNA 22 to GND3 pad 38. Ripple on the power supply pad, V.sub.DD 24, is rejected by the same mechanism and is diverted to GND2 pad 36 and GND3 pad 38 (albeit to a much smaller extent), thereby protecting the sensitive GND1 pad 26 of LNA 22 from the noise current.

(37) In principle, no noise current should flow into the sensitive GND1 pad 26 of LNA 22 when the bypass techniques described herein is utilized. Without the disclosed bypass techniques, noise currents would be allowed to flow into the GND1 pad 26 of the LNA 22 (either directly through LNA 22, or through the C.sub.BYP.sub._.sub.IN capacitor shown in FIG. 2), which would result in a significant degradation in the Noise Figure (NF) of the single-ended LNA (since thermal noise on GND1 pad 26 looks like an input and gets amplified by the LNA). The magnitude of this noise relative to the LNA's intrinsic thermal noise is proportional to the square of the transconductance (G.sub.m) of the LNA. For this reason, high current LNAs suffer acutely from this problem, unless the bypass techniques as disclosed herein are used.

(38) It will be appreciated to those skilled in the art having the benefit of this disclosure that this disclosure is believed to provide improved bypass circuitry that may be included within an electronic circuit (e.g., an IC chip) to protect on-chip noise sensitive circuits from both internal and external noise sources. Further modifications and alternative embodiments of various aspects of the disclosure will be apparent to those skilled in the art in view of this description. It is to be understood that the various embodiments of the disclosed bypass techniques shown and described herein are to be taken as the presently preferred embodiments. It will be further understood that although particular values of capacitance, inductance, resistance and impedance are discussed herein, these values are provided for explanatory purposes only, and to provide an exemplary range of values for the relative terminology (e.g., low/high impedance) used herein. One skilled in the art would understand how alternative values of capacitance, inductance and/or resistance may be used to implement the improved bypass circuit embodiments shown in FIGS. 3-7 and described herein, and how such values may differ for different noise frequencies.

(39) Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the disclosed embodiments may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this disclosure. It is intended, therefore, that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.