PSEUDO RESISTANCE CIRCUIT AND CHARGE DETECTION CIRCUIT

Abstract

A pseudo resistance circuit is disclosed that is capable of suppressing fluctuation in resistance value with fluctuation in process or temperature and facilitating adjustment. The pseudo resistance circuit includes a first MOSFET, a second MOSFET, a first current source which generates a first current substantially proportional to absolute temperature, and voltage source which generates a first voltage, which is a substantially linear function of absolute temperature. The gate of the first MOSFET and the gate of the second MOSFET are connected together, the second MOSFET is diode-connected, the first current is supplied to the drain of the second MOSFET, the first voltage is applied to the source of the second MOSFET, and a resistor having a resistance value according to the gate voltage of the first MOSFET is formed between the drain and the source of the first MOSFET.

Claims

1. A pseudo resistance circuit comprising: a first MOSFET having a drain, a source and a gate; a second MOSFET having a drain, a source and a gate that is coupled to the gate of the first MOSFET, the second MOSFET being diode-connected; a first current source coupled to the drain of the second MOSFET and configured to generate a first current substantially proportional to absolute temperature; and a voltage source coupled to the source of the second MOSFET and configured to generate a first voltage, which is a substantially linear function of absolute temperature, wherein a resistor is formed between the drain and the source of the first MOSFET that has a resistance value based on the gate voltage of the first MOSFET.

2. The pseudo resistance circuit according to claim 1, wherein the first voltage generated by the voltage source is substantially equal to the source voltage of the first MOSFET at absolute zero.

3. The pseudo resistance circuit according to claim 2, wherein the voltage source includes: a first resistor having a first end and a second end where a second voltage is applied to the first end of the first resistor; and a second current source coupled between the second end of the first resistor and ground, the second current source being configured to generate a second current that is substantially proportional to absolute temperature.

4. The pseudo resistance circuit according to claim 3, wherein the voltage source is configured to output the first voltage on the second end of the first resistor.

5. The pseudo resistance circuit according to claim 4, wherein the first current source includes a third current source configured to generate a third current substantially proportional to absolute temperature.

6. The pseudo resistance circuit according to claim 5, wherein the first current source generates the first current based on the third current.

7. The pseudo resistance circuit according to claim 6, wherein the second current source generates the second current based on the third current.

8. The pseudo resistance circuit according to claim 7, wherein the second current source comprises: a third MOSFET having a drain, a source and a gate; a fourth MOSFET that is diode connected with a drain coupled to the drain of the third MOSFET and a source coupled to ground; and a fifth MOSFET with gate coupled to a gate of the fourth MOSFET, a drain coupled to the second end of the first resistor, and a source coupled to ground.

9. The pseudo resistance circuit according to claim 1, wherein the first current source comprises: a third MOSFET having a drain, a source and a gate; a fourth MOSFET having a drain, a source and a gate; a fifth MOSFET having a drain, a source and a gate; and a sixth MOSFET having a drain, a source and a gate.

10. The pseudo resistance circuit according to claim 9, wherein a power supply voltage is applied to the source of the third MOSFET.

11. The pseudo resistance circuit according to claim 10, wherein the fourth MOSFET is diode connected with the drain of the fourth MOSFET coupled to the drain of the third MOSFET.

12. The pseudo resistance circuit according to claim 11, wherein the fifth MOSFET is diode connected with the power supply voltage applied to the source of the fifth MOSFET and the gate of the fifth MOSFET coupled to the gate of the third MOSFET.

13. The pseudo resistance circuit according to claim 12, wherein the drain of the sixth MOSFET is coupled to the drain of the fifth MOSFET, the gate of the sixth MOSFET is coupled to the gate of the fourth MOSFET, and the source of the sixth MOSFET is coupled to a first resistor that is coupled to ground.

14. A charge detection circuit comprising: the pseudo resistance circuit according to claim 1; a capacitor connected in parallel with the resistor of the pseudo resistance circuit; and an operational amplifier having an output terminal coupled to a first end of the resistor and to a first end of the capacitor and an inverting input terminal coupled to a second end of the resistor and to a second end of the capacitor.

15. The charge detection circuit according to claim 14, wherein a voltage, based on an electric charge input to the inverting input terminal of the operational amplifier, is output from the output terminal of the operational amplifier.

16. The charge detection circuit according to claim 14, wherein a non-inverting input of the operational amplifier is coupled to ground.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 is a diagram illustrating a configuration example of a pseudo resistance circuit according to an embodiment of the invention.

[0015] FIG. 2 is a diagram illustrating configuration examples of a current source and a voltage source of the circuit shown in FIG. 1.

[0016] FIG. 3 is a diagram illustrating a resistance value when focusing only on an N-channel MOSFET.

[0017] FIG. 4 is a diagram illustrating a resistance value when focusing on an N-channel MOSFET and a current source.

[0018] FIG. 5 is a diagram illustrating a configuration example of a charge detection circuit according to an embodiment of the invention.

[0019] It is noted that the figures are not necessarily drawn to scale and that elements of similar structures or functions are generally represented by like reference numerals for illustrative purposes throughout the figures. It also should be noted that the figures are only intended to facilitate the description of the various embodiments described herein. The figures do not describe every aspect of the teachings disclosed herein and do not limit the scope of the claims.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0020] In the following description, for purposes of explanation only, specific nomenclature is set forth to provide a thorough understanding of the various embodiments described herein. However, it will be apparent to one skilled in the art that these specific details are not required to practice the concepts described herein.

[0021] FIG. 1 is a diagram illustrating a configuration example of a pseudo resistance circuit according to an embodiment of the invention. A pseudo resistance circuit 100 includes N-channel MOSFETs 110 and 120, a current source 130, and a voltage source 140.

[0022] The N-channel MOSFET 110 (second MOSFET) is diode-connected, and the gate thereof is connected to the gate of the N-channel MOSFET 120. A current I.sub.PTAT from the current source 130 is supplied to the drain of the N-channel MOSFET 110. A voltage V.sub.bias from the voltage source 140 is applied to the source of the N-channel MOSFET 110.

[0023] The gate of the N-channel MOSFET 120 (first MOSFET) is connected to the gate of the N-channel MOSFET 110. In the pseudo resistance circuit 100, the N-channel MOSFET 120 operates in a weak inversion region, whereby a resistor having a resistance value R.sub.eff according to a gate voltage V.sub.G is formed between the drain and the source of the N-channel MOSFET 120.

[0024] The current source 130 generates the current I.sub.PTAT (first current) substantially proportional to absolute temperature. A configuration example of the current source 130 will be described below.

[0025] The voltage source 140 generates the voltage V.sub.bias (first voltage), which is a substantially linear function of absolute temperature. In this embodiment, if the source voltage V.sub.S of the N-channel MOSFET 120=V.sub.CM, the relationship of V.sub.bias=V.sub.CMA.Math.T is established. Here, A is a constant, and T is absolute temperature. A configuration example of the voltage source 140 will be described below.

[0026] FIG. 2 is a diagram illustrating configuration examples of the current source 130 and the voltage source 140 of the circuit 100 shown in FIG. 1.

[0027] As shown, the current source 130 includes a current source 210 and a P-channel MOSFET 220. In the current source 130, the current I.sub.PTAT is output from the drain of the P-channel MOSFET 220.

[0028] The current source 210 (third current source) includes N-channel MOSFETs 230 and 231, P-channel MOSFETs 232 and 233, and a resistor 234. An output current of the current source 210 is a current I.sub.DS2 (third current) of the N-channel MOSFET 231.

[0029] As further shown, the N-channel MOSFET 230 is diode-connected, and the source thereof is grounded. The gate of the N-channel MOSFET 231 is connected to the gate of the N-channel MOSFET 230, and the source of the N-channel MOSFET 231 is grounded through the resistor 234. The size ratio of the N-channel MOSFETs 230 and 231 is, for example, 1:n.sub.PTAT.

[0030] The P-channel MOSFET 232 is configured such that a power supply voltage V.sub.DD is applied to the source, the drain is connected to the drain of the N-channel MOSFET 230, and the gate is connected to the gate of the P-channel MOSFET 233. The P-channel MOSFET 233 is diode-connected and is configured such that the power supply voltage V.sub.DD is applied to the source, and the drain is connected to the drain of the N-channel MOSFET 231. The P-channel MOSFET 220 is configured such that the power supply voltage V.sub.DD is applied to the source, and the gate is connected to the gate of the P-channel MOSFET 233. The size ratio of the P-channel MOSFETs 232, 233, and 220 is, for example, 1:1:1/n.

[0031] In the current source 130, the gate-source voltage V.sub.GS1 of the N-channel MOSFET 230 is expressed by Expression (1).

[00001]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.1\right]& \\ V_{\mathrm{GS}.Math..Math.1}=\frac{\mathrm{kT}}{q}.Math.\frac{1}{}.Math.\ln \left(\frac{I_{\mathrm{DS}.Math..Math.1}}{I_{0.Math..Math.S.Math..Math.1}}\right)& \left(1\right)\end{array}$

[0032] Here, k is a Boltzmann constant, T is absolute temperature, q is an electronic charge, and is a approximated parameter. I.sub.DS1 is a current which flows in the N-channel MOSFET 230, and I.sub.0S1 is a current according to the size of the N-channel MOSFET 230.

[0033] The voltage V.sub.GS1 is also the gate voltage of the N-channel MOSFET 231 and can be thus expressed by Expression (2).

[Equation 2]

V.sub.GS1=V.sub.GS2+I.sub.DS2R.sub.PTAT(2)

[0034] Here, V.sub.GS2 is the gate-source voltage of the N-channel MOSFET 231. I.sub.DS2 is a current which flows in the N-channel MOSFET 231, that is, an output current of the current source 210. R.sub.PTAT is the resistance value of the resistor 234.

[0035] Expression (3) is derived from Expressions (1) and (2).

[00002]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.3\right]& \\ \frac{\mathrm{kT}}{q}.Math.\frac{1}{}.Math.\ln \left(\frac{I_{\mathrm{DS}.Math..Math.1}}{I_{0.Math..Math.S.Math..Math.1}}\right)=\frac{\mathrm{kT}}{q}.Math.\frac{1}{}.Math.\ln \left(\frac{I_{\mathrm{DS}.Math..Math.2}}{I_{0.Math..Math.S.Math..Math.2}}\right)+I_{\mathrm{DS}.Math..Math.2}.Math.R_{\mathrm{PTAT}}& \left(3\right)\end{array}$

[0036] Here, I.sub.0S2 is a current according to the size of the N-channel MOSFET 231.

[0037] I.sub.DS2 is expressed by Expression (4).

[00003]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.4\right]& \\ I_{\mathrm{DS}.Math..Math.2}=\frac{1}{R_{\mathrm{PTAT}}}.Math.\frac{\mathrm{kT}}{q}.Math.\frac{1}{}.Math.\ln \left(\frac{I_{0.Math..Math.S.Math..Math.2}}{I_{0.Math..Math.S.Math..Math.1}}\right)=\frac{1}{R_{\mathrm{PTAT}}}.Math.\frac{\mathrm{kT}}{q}.Math.\frac{1}{}.Math.\ln \left(n_{\mathrm{PTAT}}\right)& \left(4\right)\end{array}$

[0038] In the current source 130, a current which flows in the N-channel MOSFET 231 is I.sub.DS2. The P-channel MOSFET 220 is connected to the P-channel MOSFET 233 in a current mirror configuration, and thus the current I.sub.PTAT is expressed by Expression (5).

[00004]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.5\right]& \\ I_{\mathrm{PTAT}}=\frac{1}{n}.Math.I_{\mathrm{DS}.Math..Math.2}=\frac{1}{{\mathrm{nR}}_{\mathrm{PTAT}}}.Math.\frac{\mathrm{kT}}{q}.Math.\frac{1}{}.Math.\ln \left(n_{\mathrm{PTAT}}\right)=B.Math.T& \left(5\right)\end{array}$

[0039] Here, B is a constant. From Expression (5), the current I.sub.PTAT which is output from the current source 130 is a current which is substantially proportional to absolute temperature.

[0040] The voltage source 140 includes a resistor 240 and a current source 250. In the voltage source 140, the voltage V.sub.bias is output between the resistor 240 and the current source 250.

[0041] The resistor 240 (first resistor) is configured such that a voltage V.sub.CM (second voltage: the substantially same voltage as the source voltage of the N-channel MOSFET 120) is applied to one end, and the other end is connected to the drain of the N-channel MOSFET 261.

[0042] As further shown, the current source 250 (second current source) includes N-channel MOSFETs 260 and 261, and a P-channel MOSFET 262. In the current source 250, a current which flows in the N-channel MOSFET 261 becomes an output current I.sub.PTAT2 (second current).

[0043] The N-channel MOSFET 260 is diode-connected and is configured such that the drain is connected to the drain of the P-channel MOSFET 262, and the source is grounded. The N-channel MOSFET 261 is configured such that the gate is connected to the gate of the N-channel MOSFET 260, and the source is grounded. The size ratio of the N-channel MOSFETs 260 and 261 is, for example, 1:1/n.sub.bias.

[0044] The P-channel MOSFET 262 is configured such that the power supply voltage V.sub.DD is applied to the source, and the gate is connected to the gate of the P-channel MOSFET 233. The size ratio of the P-channel MOSFETs 233 and 262 is, for example, 1:1.

[0045] Similarly to the current source 130, the current source 250 generates the current I.sub.PTAT2 substantially proportional to the absolute temperature. In this embodiment, I.sub.PTAT2=(1/n.sub.bias)I.sub.DS2. Accordingly, if the resistance value of the resistor 240 is R.sub.bias, the voltage V.sub.bias is expressed by Expression (6).

[Equation 6]

V.sub.bias=V.sub.CMR.sub.biasI.sub.PTAT 2=V.sub.CMA.Math.T(6)

[0046] Here, A is a constant.

[0047] Next, the resistance value R.sub.eff in the pseudo resistance circuit 100 shown in FIG. 1 will be described.

[0048] First, as shown in FIG. 3, description will be provided focusing only on the N-channel MOSFET 120. When the N-channel MOSFET 120 operates in a weak inversion region, a current IDS which flows in the N-channel MOSFET 120 is expressed by Expression (7).

[00005]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.7\right]& \\ I_{\mathrm{DS}}=I_{0.Math..Math.S}.Math.\exp \left(.Math.\frac{{\mathrm{qV}}_{\mathrm{GS}}}{\mathrm{kT}}\right).Math.\left(1-\exp \left(-\frac{{\mathrm{qV}}_{\mathrm{DS}}}{\mathrm{kT}}\right)\right)& \left(7\right)\end{array}$

[0049] Here, V.sub.GS is the gate-source voltage of the N-channel MOSFET 120, and V.sub.DS is the drain-source voltage of the N-channel MOSFET 120. I.sub.0S is a current according to the size of the N-channel MOSFET 120 and is expressed by Expression (8).

[00006]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.8\right]& \\ I_{0.Math..Math.S}=.Math..Math.C_{\mathrm{ox}}.Math.\frac{W}{L}.Math.{\left(\frac{\mathrm{kT}}{q}\right)}^2.Math.\frac{1-{}_{\mathrm{sa}}}{{}_{\mathrm{sa}}}.Math.\exp \left(-.Math.\frac{{\mathrm{qV}}_{\mathrm{TS}}}{\mathrm{kT}}\right)& \left(8\right)\end{array}$

[0050] Here, is electron mobility, C.sub.ox is oxide capacity per unit area, W is a channel width, L is a channel length, and .sub.sa is a approximated parameter in a weak inversion region. V.sub.TS is a threshold voltage.

[0051] From Expressions (7) and (8), the resistance value R.sub.eff between the drain and the source of the N-channel MOSFET 120 is expressed by Expression (9).

[00007]$\begin{array}{cc}.Math.\left[\mathrm{Equation}.Math..Math.9\right]& \\ R_{\mathrm{eff}}={\left(\frac{{\mathrm{dI}}_{\mathrm{DS}}}{{\mathrm{dV}}_{\mathrm{DS}}}\right)}^{-1}=\frac{1}{.Math..Math.C_{\mathrm{ox}}}.Math.\frac{L}{W}.Math.\frac{q}{\mathrm{kT}}.Math.\frac{{}_{\mathrm{sa}}}{1-{}_{\mathrm{sa}}}.Math.\exp \left[\frac{q}{\mathrm{kT}}.Math.\left\{.Math..Math.V_{\mathrm{TS}}-\left(V_G-V_{\mathrm{CM}}+V_{\mathrm{DS}}\right)\right\}\right]& \left(9\right)\end{array}$

[0052] Expression (9) includes temperature T. Expression (9) also includes a threshold voltage V.sub.TS which fluctuates with a process. Accordingly, in the pseudo resistance circuit 100 of this embodiment, as described below, fluctuation in resistance value R.sub.eff with fluctuation in process and temperature is suppressed by the current source 130 and the voltage source 140.

[0053] First, as shown in FIG. 4, description will be provided focusing on the action of the current source 130. When the N-channel MOSFET 120 operates in a weak inversion region, the voltage V.sub.G is expressed by Expression (10).

[00008]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.10\right]& \\ V_G=\frac{\mathrm{kT}}{q}.Math.\frac{1}{}.Math.\ln \left(\frac{I_{\mathrm{PTAT}}}{I_{0.Math..Math.S}}\right)+V_{\mathrm{bias}}& \left(10\right)\end{array}$

[0054] In Expression (7), since V.sub.GS=V.sub.GV.sub.CM, if V.sub.G of Expression (10) is substituted in Expression (7), the current IDS is expressed by Expression (11).

[00009]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.11\right]& \\ I_{\mathrm{DS}}=I_{\mathrm{PTAT}}.Math.\exp .Math.\left\{.Math.\frac{q}{\mathrm{kT}}.Math.\left(V_{\mathrm{bias}}-V_{\mathrm{CM}}\right)\right\}.Math.\left\{1-\exp \left(-\frac{q}{\mathrm{kT}}.Math.V_{\mathrm{DS}}\right)\right\}& \left(11\right)\end{array}$

[0055] From Expression (11), the resistance value R.sub.eff is expressed by Expression (12).

[00010]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.12\right]& \\ R_{\mathrm{eff}}=\frac{\mathrm{kT}}{q}.Math.\frac{1}{I_{\mathrm{PTAT}}}.Math.\exp \left[\frac{q}{\mathrm{kT}}.Math.\left\{V_{\mathrm{DS}}+\left(V_{\mathrm{CM}}-V_{\mathrm{bias}}\right)\right\}\right]& \left(12\right)\end{array}$

[0056] If the current I.sub.PTAT of Expression (5) is substituted in Expression (12), the resistance value R.sub.eff is expressed by Expression (13).

[00011]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.13\right]& \\ R_{\mathrm{eff}}=\frac{k}{q}.Math.\frac{1}{B}.Math.\exp \left[\frac{q}{\mathrm{kT}}.Math.\left\{V_{\mathrm{DS}}+\left(V_{\mathrm{CM}}-V_{\mathrm{bias}}\right)\right\}\right]& \left(13\right)\end{array}$

[0057] Expression (13) does not include the threshold voltage V.sub.TS. More specifically, due to the action of the current source 130, the influence of fluctuation in process on the resistance value R.sub.eff is suppressed. However, Expression (13) still includes temperature T. In this embodiment, with the action of the voltage source 140, fluctuation in resistance value R.sub.eff with fluctuation in temperature is suppressed.

[0058] If V.sub.bias of Expression (6) is substituted in Expression (13), the resistance value R.sub.eff is expressed by Expression (14).

[00012]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.14\right]& \\ R_{\mathrm{eff}}=\frac{k}{q}.Math.\frac{1}{B}.Math.\exp \left[\frac{q}{\mathrm{kT}}.Math.\left\{V_{\mathrm{DS}}+.Math.A.Math.T\right)\right\}& \left(14\right)\end{array}$

[0059] Here, in the N-channel MOSFET 120, Expression (15) is assumed.

[Equation 15]

V.sub.DS0(15)

[0060] Accordingly, from Expression (14) and Expression (15), the resistance value R.sub.eff is expressed by Expression (16).

[00013]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.16\right]& \\ R_{\mathrm{eff}}=\frac{k}{q}.Math.\frac{1}{B}.Math.\exp \left(\frac{q}{k}.Math..Math..Math.A\right)& \left(16\right)\end{array}$

[0061] The voltage V.sub.bias can be expressed by Expression (17).

[00014]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.17\right]& \\ \begin{array}{c}{V}_{\mathrm{bias}}=.Math.V_{\mathrm{CM}}-R_{\mathrm{bias}}.Math.I_{\mathrm{PTAT}.Math..Math.2}\\ =.Math.V_{\mathrm{CM}}-R_{\mathrm{bias}}.Math.\frac{1}{n_{\mathrm{bias}}.Math.R_{\mathrm{PTAT}}}.Math.\frac{\mathrm{kT}}{q}.Math.\frac{1}{}.Math.\ln \left(n_{\mathrm{PTAT}}\right)\end{array}& \left(17\right)\end{array}$

[0062] Accordingly, considering Expression (5) and Expression (17), the resistance value R.sub.eff may be expressed by Expression (18).

[00015]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.18\right]& \\ R_{\mathrm{eff}}=\frac{{\mathrm{nR}}_{\mathrm{PTAT}}}{\ln \left(n_{\mathrm{PTAT}}\right)}.Math.\exp .Math.\left\{\frac{q}{\mathrm{kT}}.Math.V_{\mathrm{DS}}+\frac{.Math..Math.R_{\mathrm{bias}}}{n_{\mathrm{bias}}.Math.R_{\mathrm{PTAT}}}.Math.\ln \left(n_{\mathrm{PTAT}}\right)\right\}& \left(18\right)\end{array}$

[0063] Then, applying Expression (15), the resistance value R.sub.eff can be expressed by Expression (19).

[00016]$\begin{array}{cc}\left[\mathrm{Equation}.Math..Math.19\right]& \\ R_{\mathrm{eff}}=\frac{{\mathrm{nR}}_{\mathrm{PTAT}}}{\ln \left(n_{\mathrm{PTAT}}\right)}.Math.\exp .Math.\left\{\frac{.Math..Math.R_{\mathrm{bias}}}{n_{\mathrm{bias}}.Math.R_{\mathrm{PTAT}}}.Math.\ln \left(n_{\mathrm{PTAT}}\right)\right\}& \left(19\right)\end{array}$

[0064] Expression (16) and Expression (19) do not include the threshold voltage V.sub.TS and temperature T. Accordingly, in the pseudo resistance circuit 100 shown in FIG. 1, fluctuation in resistance value R.sub.eff with fluctuation in process and temperature is suppressed by the current source 130 and the voltage source 140.

[0065] As described above, in the pseudo resistance circuit 100 of this embodiment, as shown in Expression (13), it is possible to suppress fluctuation in resistance value R.sub.eff with fluctuation in process by the current source 130 which generates the current I.sub.PTAT substantially proportional to absolute temperature and the voltage source 140 which generates the voltage V.sub.bias, which is a substantially linear function of absolute temperature.

[0066] In the pseudo resistance circuit 100 of the exemplary embodiment as shown in FIG. 1, the voltage V.sub.bias generated by the voltage source is substantially equal to the source voltage of the N-channel MOSFET 120 at absolute zero (that is, V.sub.bias=V.sub.CMA.Math.T), whereby it is possible to suppress fluctuation in resistance value R.sub.eff with fluctuation in temperature.

[0067] Accordingly, in the pseudo resistance circuit 100, in order to suppress fluctuation in resistance value R.sub.eff with fluctuation in process or temperature, it is not necessary to accurately set a plurality of parameters experimentally found, and adjustment is facilitated.

[0068] In the pseudo resistance circuit 100 of the exemplary embodiment, the current generation in the current source 130 and the current source 250 is performed based on the same current source 210. Accordingly, as shown in Expression (19), it is possible to adjust the resistance value R.sub.eff by the resistance ratio and the current ratio in the current source 130 and the current source 250.

[0069] FIG. 5 is a diagram illustrating an example of a charge detection circuit according to an exemplary embodiment. A charge detection circuit 500 includes the pseudo resistance circuit 100 shown in FIG. 1, an operational amplifier 510, and a capacitor 520.

[0070] The operational amplifier 510 is configured such that the non-inverting input terminal is grounded, and an electric charge Q.sub.IN is input to the inverting input terminal. The electric charge Q.sub.IN is, for example, an electric charge which is output from a sensing element. The pseudo resistance circuit 100 is connected between the output terminal and the inverting input terminal of the operational amplifier 510. The capacitor 520 is connected in parallel with the pseudo resistance circuit 100.

[0071] The charge detection circuit 500 outputs an output voltage V.sub.OUT according to the electric charge Q.sub.IN input to the inverting input terminal from the output terminal of the operational amplifier 510. In the charge detection circuit 500, the pseudo resistance circuit 100 uses a weak inversion region of a MOSFET making it possible for the resistance value of the pseudo resistance circuit 100 to be a large value of, for example, about 10 T. Accordingly, the charge detection circuit 500 is suitable for detecting a signal having a comparatively low frequency, such as a biological signal. As described above, in the pseudo resistance circuit 100, fluctuation in resistance value with fluctuation in process or temperature is suppressed. Accordingly, it becomes possible to suppress fluctuation in the output voltage of the charge detection circuit 500 with fluctuation in process or temperature.

[0072] Although various embodiments have been described with respect to specific examples and subsystems, it will be apparent to those of ordinary skill in the art that the embodiment is simply for ease of understanding of the invention, and is not in any way to be construed as limiting the invention. The invention may be altered or improved without departing from the spirit and encompass equivalents thereof.

DESCRIPTION OF REFERENCE NUMERALS

[0073] 100: pseudo resistance circuit [0074] 110, 120, 230, 231, 260, 261: N-channel MOSFET [0075] 130, 210, 250: current source [0076] 140: voltage source [0077] 220, 232, 233, 362: P-channel MOSFET [0078] 234, 240: resistor [0079] 500: charge detection circuit [0080] 510: operational amplifier [0081] 520: capacitor