Matching circuit for matching an impedance value and a corresponding system and method

Abstract

The invention relates to a matching circuit for matching impedance values comprising an impedance element with an impedance value, which corresponds to a required total impedance value of the matching circuit, a structurally determined parasitic unit with a parasitic impedance value and a compensation unit with at least one first compensation element. The first compensation element provides a compensation impedance value which is the dual impedance value of the parasitic impedance value. Furthermore, a system comprising a first circuit unit and a second circuit unit with a matching circuit serving for the matching is provided. Also, a method for the compensation of parasitic units for matching purposes is provided.

Claims

1. A matching circuit for matching an impedance value comprising: an impedance element with an impedance value, which corresponds to a required total impedance value of the matching circuit; a structurally determined parasitic unit with a parasitic impedance value; and a compensation unit with at least one first compensation element, wherein the first compensation element provides a compensation impedance value, which is the dual impedance value of the parasitic impedance value, wherein the compensation unit provides a second compensation element, and wherein the second compensation element provides an impedance value which corresponds to the required total impedance value.

2. The matching circuit according to claim 1, wherein the impedance element is arranged in series configuration with the parasitic unit, and wherein the compensation unit is arranged in parallel configuration to this series configuration.

3. The matching circuit according to claim 2, wherein the compensation unit is a series configuration comprising the first compensation element and the second compensation element.

4. The matching circuit according to claim 1, wherein the impedance element is arranged in parallel configuration with the parasitic unit, and wherein the compensation unit is arranged in series configuration to this parallel configuration.

5. The matching circuit according to claim 4, wherein the compensation unit is a parallel configuration comprising the first compensation element and the second compensation element.

6. The matching circuit according to claim 1, wherein the dual impedance value of the first compensation element is referenced to the required total impedance value.

7. The matching circuit according to claim 1, wherein the dual impedance value of the first compensation element is equal to the quotient of the square of the impedance value and the parasitic impedance value.

8. The matching circuit according to claim 1, wherein the impedance element is an ohmic resistance element, especially with an impedance value of 50 ohms.

9. The matching circuit according to claim 1, wherein, in each case, the parasitic unit and the first compensation element is a line with identical propagation constant and identical length.

10. The matching circuit according to claim 1, wherein the parasitic unit is formed from a capacitance element, an inductance element and/or an ohmic resistance.

11. A system comprising a first circuit unit and a second circuit unit, wherein a matching circuit according to the claim 1 is present for the electrical matching of the first circuit unit to the second circuit unit.

12. The system according to claim 11, wherein the second circuit unit and the matching circuit is an integral component of a measuring device, especially of a digital storage oscilloscope.

13. A method for compensating parasitic units for matching purposes with the method steps: checking the presence of a parasitic unit in series configuration or in parallel configuration to an impedance element, wherein the impedance element provides a required total impedance value; introduction of a compensation unit corresponding to the result of the checking step, wherein: in the presence of a parasitic unit in series configuration to the impedance element, the compensation unit is placed in parallel configuration to the series configuration; or in the presence of a parasitic unit in parallel configuration to the impedance element, the compensation unit is placed in series configuration to the parallel configuration; repetition of the checking step; and repetition of the placing step in the case of a presence of a further parasitic unit.

14. The method according to claim 13, wherein the parasitic unit provides a parasitic impedance value; wherein the compensation unit provides at least one first compensation element; and wherein the first compensation element provides a compensation impedance value, which, in the case of a series-connected parasitic unit, is a series configuration of an impedance value and of the dual impedance value of the parasitic impedance value, or which, in the case of a parallel-connected parasitic unit, is a parallel configuration of an impedance value and of the dual impedance value of the parasitic impedance value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the following, the invention is explained by way of example with reference to the drawings. Identical reference numbers refer to identical elements in the drawings. The individual elements may have been illustrated in an exaggerated scale or respectively in an oversimplified manner. The Figures of the drawings show:

(2) FIG. 1a a resistance element as a matching element in series to an input transistor, according to one embodiment;

(3) FIG. 1b a resistance element as a matching element in parallel to an input transistor, according to one embodiment;

(4) FIG. 2a a resistance element as a matching element in series with a transmission line as connecting element to an input transistor, according to one embodiment;

(5) FIG. 2b an equivalent circuit diagram of the circuit shown in FIG. 2a, according to one embodiment;

(6) FIG. 3 a first embodiment of a matching circuit according to one embodiment;

(7) FIG. 4 a second embodiment of a matching circuit according to one embodiment;

(8) FIG. 5 a third embodiment of a matching circuit according to one embodiment;

(9) FIG. 6 a fourth embodiment of a matching circuit according to one embodiment;

(10) FIG. 7 an exemplary of the invention for the iterative provision of a matching circuit for a plurality of parasitic units, according to one embodiment;

(11) FIG. 8 a matching circuit for compensation of the parasitic units illustrated in FIG. 7, according to one embodiment;

(12) FIGS. 9a-h exemplary circuit elements and their corresponding dual circuit elements, according to one embodiment.

DETAILED DESCRIPTION OF THE DRAWINGS

(13) FIG. 1a and FIG. 1b have already been described. In FIG. 1a, a transmission line TL with an impedance of Z.sub.C=50 ohms is connected as a first circuit unit to a downstream second circuit arrangement. This second circuit arrangement is, for example, a measuring instrument with a measurement input, to which the transmission line TL must be connected. Now, to allow a reflection-free and power-matched transmission of high-frequency signals from the transmission line TL to the measuring instrument, the line impedance value of Z.sub.C=50 ohms must be compensated. This takes place according to FIG. 1a through a series impedance R.sub.T to an input transistor in such a manner that the series impedance R.sub.T is connected to a reference potential. This takes place according to FIG. 1b through a parallel impedance R.sub.T to an input transistor in such a manner that the parallel impedance R.sub.T is connected to a high-ohmic potential.

(14) In both cases, such a matching element R.sub.T is not adequate, since parasitic elements are non-ideal through the connecting element between impedance R.sub.T and transistor T and also the transistors T are non-ideal in the case of input signals in the high-frequency range and cause fluctuations in the magnitude of the frequency response of the input of the second circuit unit because of their frequency dependence and temperature dependence. The frequency dependence and the temperature dependence must be compensated.

(15) FIG. 2a shows a resistance element R.sub.T as a matching element in series with a line L as a connecting element to an input transistor T. Reference is made to the fact that, as the connecting element, the line L according to the following drawings is not the transmission line TL shown in FIGS. 1a and 1b. The line L represents a structurally determined parasitic unit 2, while the transmission line TL represents a circuit unit.

(16) The input transistor T is connected to a series configuration comprising an impedance element R.sub.T followed by a parasitic unit 2 consisting of the line L with a line impedance Z.sub.C, a propagation constant and a length l.

(17) According to the equivalent circuit diagram shown in FIG. 2b of the construction from FIG. 2a, the input node of the transistor T can be regarded as a virtual reference potential. Accordingly, the resistor R.sub.T does not act alone at the input terminal, but rather, an impedance element Z.sub.in comprising a series configuration made from a resistance element R.sub.T and a parasitic impedance value Z.sub.1 of the shorted line L acts as connecting element. The parasitic impedance value Z.sub.1 at the input of the shorted line L is obtained from the following:
Z.sub.1=j.Math.Z.sub.C.Math.tan(.Math.l).(1)

(18) The input impedance Z.sub.in is obtained on the basis of the series configuration from the following:
Z.sub.in=R.sub.T+Z.sub.1.(2)

(19) In this context, the line L represents a structurally determined parasitic unit 2. The parasitic unit 2 is frequency dependent and temperature unstable and must therefore be compensated in order to achieve an ideal transmission behavior from DC voltage through to voltages of high-frequency. Accordingly, a compensation impedance Z.sub.match must be found, which achieves a temperature-independent and frequency-stable matching resistance R.sub.T. In this context, the following applies:

(20) $\begin{array}{cc}{R}_T=\frac{1}{\frac{1}{R_T+Z_1}+\frac{1}{Z_{\mathrm{match}}}}& \left(3\right)\end{array}$

(21) To obtain the compensation impedance Z.sub.match, the following therefore applies:

(22) $\begin{array}{cc}{Z}_{\mathrm{match}}=R_T+\frac{R_T^2}{Z_1}& \left(4\right)\end{array}$

(23) If the parasitic impedance value Z.sub.1 of the shorted line L is substituted according to equation (1), the following is obtained:

(24) $\begin{array}{cc}{Z}_{\mathrm{match}}=R_T-j.Math.\frac{R_T^2}{Z_C}.Math.\cot \left(.Math.l\right)& \left(5\right)\end{array}$

(25) The compensation impedance Z.sub.match obtained in equation (5) can be realized through a series configuration of a resistance element R.sub.T and an open-ended line L with a characteristic line impedance R.sub.T.sup.2/Z.sub.C, a propagation constant and a length l, as illustrated in FIG. 4.

(26) Initially, an explanation will be given of the general idea of the invention with reference to FIG. 3. FIG. 3 shows an impedance element 1 in series with a parasitic unit 2. Now, the parasitic unit 2 is to be completely compensated by the compensation unit 3, so that a frequency-independent and temperature stable matching circuit is obtained.

(27) A compensation of the parasitic unit 2 is implemented through the embodiment of a dual compensation unit 3 relative to the parasitic unit 2, wherein the compensation unit 3 comprises a series configuration of a first compensation element 32 and a second compensation element 31. In this context, the second compensation element 31 is dual relative to the parasitic unit 2. Since the parasitic unit 2 is connected in series to the impedance element 1, the compensation unit 3 must be arranged in a parallel configuration to the series configuration comprising parasitic unit 2 and impedance element 1.

(28) The compensation unit 3 according to FIG. 3 provides a first compensation element 31 in series with a second compensation element 32, thereby providing the compensation impedance Z.sub.match. The input impedance Z.sub.in corresponds to equation (2). For the compensation of parasitic unit 2, a dual impedance value R.sub.t.sup.2/Z.sub.1 relative to the parasitic impedance value Z.sub.1 is formed. The dual impedance value R.sub.t.sup.2/Z.sub.1 can be expressed through formation of the quotient of the square of the impedance value R.sub.T and the parasitic impedance value Z.sub.1. This dual impedance value R.sub.t.sup.2/Z.sub.1 is an admittance value which corresponds to the reciprocal of the parasitic impedance value Z.sub.1 of the parasitic unit 2 and is scaled to the impedance value R.sub.T.

(29) The matching circuit shown in FIG. 3 causes the parasitic impedance value Z.sub.1 to be compensated completely and in a frequency-independent manner by the compensation unit 3.

(30) In FIG. 4, the shorted line Lillustrated in FIG. 2bis compensated. In this context, the shorted line L is regarded as a parasitic unit 2. For the compensation of this parasitic unit 2, it is suggested according to FIG. 4 that an open line L with a line impedance R.sub.T.sup.2/Z.sub.C is used, wherein the propagation constant and the length l of the shorted line L are identical to the open line L.

(31) FIG. 5 proposes a matching network which compensates the parallel configurationshown in principle in FIG. 1bof a resistance element R.sub.T and a parasitic unit 2 with a parasitic impedance value Z.sub.1. In this context, the impedance value R.sub.T of the impedance element 1 is illustrated in parallel to the parasitic unit 2. A compensation of the parallel configuration of impedance element 1 and parasitic unit 2 is achieved by a compensation unit 3 connected in series. The compensation unit 3 provides a first compensation element 31 parallel to a second compensation element 32, wherein the second compensation element 32 provides the impedance value R.sub.T, and the first compensation element 31 provides the dual impedance value R.sub.t.sup.2/Z.sub.1. In this context, the following applies:

(32) $\begin{array}{cc}{R}_T=Z_{\mathrm{match}}+\frac{1}{\frac{1}{R_T}+\frac{1}{Z_1}}& \left(6\right)\end{array}$

(33) Now, in order to obtain the compensation impedance Z.sub.match, the following applies

(34) $\begin{array}{cc}{Z}_{\mathrm{match}}=\frac{1}{\frac{1}{R_T}+\frac{Z_1}{R_T^2}}& \left(7\right)\end{array}$

(35) wherein the required impedance value R.sub.T is arranged parallel to the first compensation element 31 with a dual impedance value R.sub.t.sup.2/Z.sub.1.

(36) FIG. 6 shows a further exemplary embodiment of a matching circuit in which a plurality of parasitic elements is introduced into a parasitic unit 2. In this context, a connecting element is embodied as the line L and, between the terminal resistor R.sub.T and a downstream transistor Tnot illustratedarranged as an input amplifier. The line L in turn is illustrated by a line shorted in a lossless manner through its line impedance Z.sub.C, a propagation constant and a length l as a parasitic element of the parasitic unit 2. Furthermore, an inductance L.sub.Bond and a capacitance value C.sub.Ball are arranged as further parasitic elements in the parasitic unit 2.

(37) According to our aspect of the invention, a compensation of all three parasitic elements comprising line L, connection capacitance C.sub.Ball and connection impedance L.sub.Bond is implemented through a compensation unit 3. The parallel-connected parasitic capacitance C.sub.Ball is compensated through a series-connected inductance with the inductance value R.sub.T.sup.2.Math.C.sub.Ball. The series-connected parasitic inductance L.sub.Bond is compensated through a parallel-connected parasitic capacitance with the capacitance value L.sub.Bond/T.sub.T.sup.2.

(38) FIG. 7 shows a circuit network, wherein, by way of distinction from the exemplary embodiments previously shown, several parasitic units 2 are embodied. For example, the first parasitic unit Z.sub.1 can image the parasitic unit 2 shown in FIGS. 3 to 6. Furthermore, a second parasitic unit 2 is present as Z.sub.2 parallel to the series configuration comprising R.sub.T and Z.sub.1. Furthermore, a third parasitic unit 2 is present as Z.sub.3 in series configuration to the previously named elements Z.sub.2, R.sub.T, Z.sub.1.

(39) The method according to the invention is used for the compensation of such a network, wherein the total result of the compensation is illustrated in FIG. 8.

(40) In the method according to the invention, the presence of a parasitic unit 2 is first checked, wherein it is determined during the checking step whether the parasitic unit 2 is arranged in series configuration or in parallel configuration to an impedance element R.sub.T. In the present case as shown in FIG. 7, a first parasitic unit 2 is arranged in series with an impedance element 1 with the impedance value R.sub.T. For the compensation, a first compensation unit 3 is introduced, which is arranged correspondingly in parallel with the series-connected impedance element 1 and parasitic unit 2. This is shown as step 1 in FIG. 7. Since further parasitic units Z.sub.2, Z.sub.3 are present within the network, the method has not been completed at this point. Accordingly, a further check is performed to determine whether further parasitic units Z.sub.2, Z.sub.3 are present in series configuration or in parallel configuration to the now compensated impedance value. If a parasitic unit 2 is first detected in series with an impedance element 1, all parasitic units 2 disposed in series are compensated together for compensation in the first step 1. Correspondingly, in the case of a detection of a parasitic unit 2 connected in parallel to an impedance element 1, all parallel arranged parasitic units 2 are compensated together in the first step 1.

(41) If a series configuration was compensated first, a parallel configuration of parasitic units 2 is compensated in the following step 2. Alternatively, if a parallel configuration was compensated in the preceding step 1, a series configuration is compensated in the following step 2. A series configuration and a parallel configuration therefore alternate from one compensation step to the next compensation step.

(42) According to FIG. 7, a parasitic unit 2 with an impedance value Z.sub.2 is arranged in parallel. According to FIG. 8, a compensation unit 3 which is arranged in series to a parallel configuration is introduced for the compensation. This is indicated by step 2 in FIG. 7.

(43) The method is not yet concluded with step 2, since a third compensation element 3 is necessary in order to compensate a third parasitic unit 2 with an impedance value Z.sub.3, see step 3 in FIG. 7. Because of the series configuration of Z.sub.3 to the remaining circuit, a parallel configuration of a compensation unit 3 will have to be provided, see FIG. 8.

(44) In FIG. 9a-FIG. 9e, the dual element corresponding to every conventional element of network theory is shown. The value of every dual element has been calculated on the basis of a scaling impedance R.sub.T.

(45) FIG. 9a shows that an ohmic resistor with a resistance value R can be compensated by a resistor with a resistance value R.sub.T.sup.2/R as dual circuit element.

(46) FIG. 9b shows that a capacitance element with a capacitance value C can be compensated by an inductance element with an inductance value R.sub.T.sup.2.Math.C as dual circuit element.

(47) FIG. 9c shows that an inductance element with an inductance value L can be compensated by a capacitance element with a capacitance value L/R.sub.T.sup.2 as dual circuit element.

(48) FIG. 9d shows that an ideal voltage source with a voltage V can be compensated by an ideal current source with a current V/R.sub.T as dual circuit element.

(49) FIG. 9e shows that an ideal current source with a current I can be compensated by an ideal voltage source with a voltage I.Math.R.sub.T as dual circuit element.

(50) FIG. 9f shows that a series configuration comprising two elements can be compensated by a parallel configuration of the two elements as dual circuit element.

(51) FIG. 9g shows that a parallel configuration comprising two elements can be compensated by a series configuration of the two elements as dual circuit element.

(52) FIG. 9h shows the dual network to a transmission line with characteristic impedance Z.sub.C, which is terminated by an impedance Z.sub.L. The dual network is a transmission line with characteristic impedance R.sub.T.sup.2/Z.sub.C which is terminated by an impedance with an impedance value R.sub.T.sup.2/Z.sub.L. The length l and the propagation constant of both transmission lines are identical.

(53) All of the features illustrated, claimed or described can be combined with one another according to the invention. In particular, it is provided that networks with different parasitic units are connected to corresponding dual networks, in order to form the compensation units. Furthermore, a system comprising a first circuit unit and a second circuit unit is provided, wherein a matching circuit according to the invention is provided in order to achieve a reflection-free and power-matched signal transmission from a first circuit unit to the second circuit unit.

(54) It is understood that, while the detailed drawings, specific examples, and particular component values given describe preferred embodiments of the present invention, they serve the purpose of illustration only. The apparatus of the invention is not limited to the precise details and conditions disclosed. Other substitutions, modifications, changes, and omissions may be made in the design, operating conditions, and arrangement of the preferred embodiments without departing from the spirit of the invention as expressed in the appended claims.