Transient voltage suppressor apparatus

Abstract

A transient voltage suppressor (TVS) apparatus includes a plurality of input/output (I/O) pins, a plurality of ground pins, and a substrate. The substrate includes a plurality of division parts and a carrier part. The carrier part carries a chip. The division parts are disposed between each of the I/O pins and the ground pins. The chip is electrically connected to the I/O pins and the ground pins, and the division parts are electrically insulated from the I/O pins and the ground pins.

Claims

1. A transient voltage suppressor apparatus comprising: a plurality of input/output pins; a plurality of ground pins; and a substrate comprising: a carrier part carrying a chip; and a plurality of division parts extending from the carrier part, each of the division parts being disposed between one of the input/output pins and one of the ground pins, wherein the chip is electrically connected to the input/output pins and the ground pins, and the division parts are electrically insulated from the input/output pins and the ground pins.

2. The transient voltage suppressor apparatus according to claim 1, wherein at least one first capacitor is formed between each of the input/output pins and a corresponding division part of the division parts, a plurality of second capacitors are formed between each of the ground pins and a corresponding division part of the division parts, and the at least one first capacitor and the second capacitors are serially coupled.

3. The transient voltage suppressor apparatus according to claim 1, wherein the substrate further comprises a ground part, and parts of the ground pins and the ground part are integrally formed.

4. The transient voltage suppressor apparatus according to claim 1, wherein the chip has a plurality of input/output solder pads and a plurality of ground solder pads, and the input/output solder pads and the ground solder pads are electrically connected to the input/output pins and the ground pins through wire bonding.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

(2) FIG. 1 illustrates a chip package structure according to the related art.

(3) FIG. 2 is a schematic diagram of a transient voltage suppressor (TVS) apparatus according to an embodiment of the invention.

(4) FIG. 3A is a schematic diagram illustrating a parasitic capacitor in the TVS apparatus 200 according to the embodiment depicted in FIG. 2.

(5) FIG. 3B is a cross-sectional view taken along a line segment A-A in FIG. 3A.

(6) FIG. 4 is a schematic diagram illustrating a manufacturing method of the TVS apparatus 200 according to the embodiment depicted in FIG. 2 and FIG. 3.

(7) FIG. 5A is a schematic diagram of a TVS apparatus according to another embodiment of the invention.

(8) FIG. 5B is a cross-sectional view taken along a line segment B-B in FIG. 5A.

DESCRIPTION OF EMBODIMENTS

(9) Please refer to FIG. 2. FIG. 2 is a schematic diagram of a TVS apparatus according to an embodiment of the invention. The TVS apparatus 200 includes a plurality of I/O pins IO1-IO4, a plurality of ground pins GP1-GP6, and a substrate 210. The substrate 210 includes a carrier part 211 and a plurality of division parts 212. The carrier part 211 is configured to carry a chip 220. In the present embodiment, the substrate 210 may be a conductive substrate or a lead frame, and the chip 220 may be a TVS chip. The division parts 212 are arranged between the I/O pins IO1-IO4 and the ground pins GP1-GP6. The division parts 212 are in a floated state. While the division parts 212 are in the so-called floated state, voltages in any form are not applied to the division parts 212.

(10) In the present embodiment, the division parts 212 and the carrier part 211 are coupled, and the division parts 212 extend outwardly from the carrier part 211. The division parts 212 are arranged in a multi-finger manner (or in a herringbone-like manner) between the I/O pins IO1-IO4 and the adjacent ground pins GP1-GP6. For instance, the division parts 212 are located between the I/O pin IO1 and the adjacent ground pins GP1 and GP2 for separating the I/O pin IO1 and the adjacent ground pins GP1 and GP2. The division parts 212 are electrically insulated from the I/O pins IO1-IO4 and electrically insulated from the ground pins GP1-GP6.

(11) The chip 220 is disposed on the carrier part 211, and the substrate of the chip 220 can be electrically insulated from the carrier part 211. A plurality of solder pads are located on a first surface of the chip 220, ground solder pads PD1-PD4 are electrically coupled to the ground pins GP1, GP2, GP3, and GP5 through a plurality of packaging wires, and I/O solder pads PD5-PD8 are electrically coupled to the I/O pins IO1-IO4 through a plurality of packaging wires.

(12) The TVS apparatus 200 may include a package cover to cover the I/O pins IO1-IO4, the ground pins GP1-GP6, the conductive substrate 10, and the chip 220.

(13) Please refer to FIG. 3A and FIG. 3B. FIG. 3A is a schematic diagram illustrating a parasitic capacitor in the TVS apparatus 200 according to the embodiment depicted in FIG. 2. FIG. 3B is a cross-sectional view taken along a line segment A-A in FIG. 3A. As shown in FIG. 3A, by the division parts 212-1-212-4 which have potential different form the I/O pins IO1-IO4 and the ground pins GP1-GP6, a plurality of parasitic capacitors are formed between the I/O pins IO1-IO4 and the adjacent division parts 212-1-212-4 and between the ground pins GP1-GP6 and the adjacent division parts 212-1-212-4.

(14) As shown by the line segment A-A in FIG. 3B, the parasitic capacitor C1 is formed between the ground pin GP6 and the division part 212-1, the parasitic capacitor C2 is formed between the I/O pin IO3 and the division part 212-1, the parasitic capacitor C3 is formed between the I/O pin IO3 and the division part 212-2, the parasitic capacitor C4 is formed between the ground pin GP5 and the division part 212-2, the parasitic capacitor C5 is formed between the ground pin GP5 and the division part 212-3, the parasitic capacitor C6 is formed between the I/O pin IO4 and the division part 212-3, the parasitic capacitor C7 is formed between the I/O pin IO4 and the division part 212-4, and the parasitic capacitor C8 is formed between the ground pin GP4 and the division part 212-4.

(15) Since the potential of the division parts is different from the potential of the I/O pins and the potential of the ground pins (e.g., floated), the arrangement of the division parts between the I/O pins and the ground pins allows the parasitic capacitors between the I/O pins and the adjacent ground pins to become serially coupled parasitic capacitors. For instance, two serially coupled parasitic capacitors C2 and C1 are located between the I/O pin IO3 and the ground pin GP6, and two serially coupled parasitic capacitors C3 and C4 are located between the I/O pin IO3 and the ground pin GP5. The equivalent capacitance CE between the I/O pin IO3 and the ground pin may be represented as:

(16) $\mathrm{CE}=\frac{1}{\frac{1}{C1}+\frac{1}{C2}}+\frac{1}{\frac{1}{C3}+\frac{1}{C4}}+C_{\mathrm{DIE}},$
wherein C.sub.DIE is the parasitic capacitance provided by the chip 220.

(17) As provided above, the equivalent capacitance of the parasitic capacitors between the I/O pins IO1-IO4 and the ground pins can be effectively decreased, and signal distortion (caused by the parasitic capacitors) on the I/O pins IO1-IO4 can be significantly reduced.

(18) From another perspective, to reduce the number of the packaging wires between the chip 220 and the ground pins GP1-GP6, one or more ground parts 221 and 222 may be arranged in the TVS apparatus 200 according to an embodiment of the invention. Some of the pins GP1-GP6 (e.g., the ground pins GP1 and GP6) may be connected to the ground part 221, and other ground pins (e.g., the ground pins GP3 and GP4) are connected to the ground part 222. If the ground solder pads on the chip 220 are required to be electrically connected to the ground pins GP1 and GP6, the ground solder pads may be connected to the ground part 221 through one packaging wire, and thereby the ground solder pads on the chip 220 can be electrically coupled to the ground pins GP1 and GP6 through one packaging wire. Owing to the ground parts 221 and 222, the connectible range of the ground pins GP1 and GP6 and the ground pins GP3 and GP4 can be expanded. Thereby, the length of the packaging wires connected to the ground pins GP1, GP6, GP3, and GP4 can be reduced, and thus possible inductance resulting from the packaging wire may be prevented to a better extent.

(19) In the TVS apparatus 200, the ground part 221 and the ground pins GP1 and GP6 may be formed by one conductive metal layer made of one material and may be integrally formed. The ground part 222 and the ground pins GP3 and GP4 may be formed by one conductive metal layer made of one material and may be integrally formed. In other words, the arrangement of the ground parts 221 and 222 does not complicate the manufacture of the TVS apparatus 200.

(20) Please refer to FIG. 4. FIG. 4 is a schematic diagram illustrating a manufacturing method of the TVS apparatus according to the embodiment depicted in FIG. 2 and FIG. 3. In FIG. 4, a lead frame array includes a plurality of lead frames 401-404. During the process of manufacturing the TVS apparatus, a plurality of chips are held by the lead frames 401-404. A wire bonding process and a compound molding process are implemented, and a cutting process is performed along cutting way SW (shown by dotted lines in FIG. 4) to obtain a plurality of TVS apparatuses.

(21) Please refer to FIG. 5A and FIG. 5B. FIG. 5A is a schematic diagram illustrating a TVS apparatus according to another embodiment of the invention, and FIG. 5B is a cross-sectional view taken along a line segment B-B in FIG. 5A. In FIG. 5A, the chip 520 is formed in the TVS apparatus 500 through flip-chip packaging. Flip-chip packaging is a packaging technology through which the chip can be directly connected to the substrate. During the packaging process, the chip is turned upside down, such that the solder pads on the active surface of the chip are directly connected to the circuit patterns (e.g., printed circuits of a printed circuit board) on the substrate.

(22) The TVS apparatus 500 includes a substrate 510, and the substrate 510 includes a plurality of I/O pins IO1-IO4, a plurality of ground pins GP1-GP6, and a division part 512. The division part 512 includes branches 512-1-512-4. The I/O pins IO1-IO4 are respectively separated from the adjacent ground pins GP1-GP6 through the branches 512-1-512-4. Each of the branches 512-1-512-4 is electrically insulated from the I/O pins IO1-IO4 and electrically insulated from the ground pins GP1-GP6 and is in the floated state because no voltage is applied in any form to the branches 512-1-512-4. Thereby, the equivalent capacitance provided by the parasitic capacitors between the I/O pins IO1-IO4 and the ground pins GP1-GP6 can be reduced.

(23) The I/O solder pads PD5-PD8 and the solder pads PD1-PD4, PD9, and PD10 on the chip 520 are bonded to the ground pins GP1-GP6 and the I/O pins IO1-IO4. As shown by the line segment B-B in FIG. 5B, the ground solder pad PD10, the I/O solder pad PD8, the ground solder pad PD4, the I/O solder pad PD7, and the ground solder pad PD9 are electrically coupled to the ground pin GP6, the I/O pin IO3, the ground pin GP5, the I/O pin IO4, and the ground pin GP4 through conductive bumps B-1-B-4, respectively.

(24) In the present embodiment, the parasitic capacitor C1 is formed between the ground pin GP6 and the branch 512-1, the parasitic capacitor C2 is formed between the I/O pin IO3 and the branch 512-1, the parasitic capacitor C3 is formed between the I/O pin IO3 and the branch 512-2, the parasitic capacitor C4 is formed between the ground pin GP5 and the branch 512-2, the parasitic capacitor C5 is formed between the ground pin GP5 and the branch 512-3, the parasitic capacitor C6 is formed between the I/O pin IO4 and the branch 512-3, the parasitic capacitor C7 is formed between the I/O pin IO4 and the branch 512-4, and the parasitic capacitor C8 is formed between the ground pin GP4 and the branch 512-4. That is, two serially connected parasitic capacitors may be located between any of the I/O pins and the adjacent ground pins, so as to reduce the equivalent capacitance provided by the parasitic capacitors between any of the I/O pins and the adjacent ground pins.

(25) The conductive bumps B1-B4 may be gold bumps, tin-lead balls, or the conductive bumps that are made of any material and may be configured to perform electrical connection in flip-chip packaging, as known to people having ordinary skill in the pertinent art.

(26) To sum up, the floated division parts are configured between each of the I/O pins and the adjacent ground pin. Since the potential of the (e.g., floated) division parts is different from the potential of the I/O pins and the potential of the ground pins, the arrangement of the division parts between the I/O pins and the ground pins allows the parasitic capacitors between the I/O pins and the adjacent ground pins to become serially coupled parasitic capacitors, and the equivalent capacitance provided by the parasitic capacitors between the I/O pins and the ground pins can be effectively reduced. As such, the impact of the parasitic capacitors on distortion of signals transmitted on the I/O pins can be lessened, and the signal transmission accuracy can be enhanced.

(27) It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it should be mentioned that the invention covers modifications and variations of this disclosure provided that they fall within the scope of the following claims and their equivalents.