Charge measuring device with integrated FET, capacitor, and charge accumulation device

Abstract

A charge measuring device detects focused ion beam attacks on an integrated semiconductor circuit with a capacitor, a field effect transistor, and a charge collecting device all manufactured in the integrated semiconductor circuit and insulated from additional circuit elements. A first pole of the capacitor is conductively connected to the charge collecting device and a gate of the field effect transistor. When a voltage is applied to the second pole of the capacitor, a drain source current flows through the field effect transistor, and a relationship between the voltage and the drain source current is ascertained. A comparison of the relationship with a previously ascertained relationship indicates a change of the charge quantity stored in the capacitor by the charge collecting device.

Claims

1. A charge measuring device, comprising: a capacitor having a first pole and a second pole; a field-effect transistor having a source connection, a drain connection and a gate connection; a charge accumulation device, and an amplifier coupled back via said capacitor and said field-effect transistor to obtain a preset setpoint drain-source current, with a result that a voltage present at said second pole, in comparison with a reference voltage, is a measure for a change in a charge on said capacitor based on a charge stored during a reference voltage detection; wherein said capacitor, said field-effect transistor and said charge accumulation device are manufactured jointly in an integrated semiconductor circuit; wherein said first pole of said capacitor is conductively connected to said charge accumulation device and to said gate connection of said field-effect transistor; and wherein said first pole of said capacitor, said gate connection and said charge accumulation device are all insulated from further circuit elements.

2. The charge measuring device according to claim 1, wherein said field-effect transistor is connected to a current measuring device measuring a drain-source current or a current regulating device determining the drain-source current, and said second pole of said capacitor is connected to a voltage source, which is actuable or is actuated such that a current is measured it said current measuring device or a current is preset by said current regulating device so that a relationship between a voltage present at said second pole of said capacitor and said drain-source current can be ascertained.

3. The charge measuring device according to claim 2, wherein said voltage source comprises an amplifier, which derives the voltage from the drain-source current flowing through said field-effect transistor.

4. The charge measuring device according to claim 1, wherein said second pole of said capacitor is coupled to a security circuit on the integrated semiconductor circuit, said security circuit is configured to selectively implement or not implement a security function during operation in which the voltage is provided at said second pole by an amplifier which is coupled back via said capacitor and said field-effect transistor, depending on the voltage.

5. The charge measuring device according to claim 1, wherein a relationship between the voltage coupled in via the second pole of the capacitor and the drain-source current is changed due to a beam of charged particles or an electrical field with a high field strength being applied to the integrated semiconductor circuit.

6. The charge measuring device according to claim 1, wherein said capacitor, said field-effect transistor and said charge accumulation device are embodied using metal oxide semiconductor technology or complementary metal oxide semiconductor technology.

7. A method for measuring a charge quantity with an integrated semiconductor circuit having a charge measuring device, the method comprising: providing a charge measuring device, including: a capacitor having a first pole and a second pole, a field-effect transistor having a source connection, a drain connection and a gate connection, a charge accumulation device, and an amplifier coupled back via the capacitor and the field-effect transistor to obtain a preset setpoint drain-source current, with a result that a voltage present at the second pole, in comparison with a reference voltage, is a measure for a change in a charge on the capacitor based on a charge stored during a reference voltage detection, wherein the capacitor, the field-effect transistor and the charge accumulation device are manufactured jointly in an integrated semiconductor circuit, wherein the first pole of the capacitor is conductively connected to the charge accumulation device and to the gate connection of the field-effect transistor, and wherein the first pole of the capacitor, the gate connection and the charge accumulation device are all insulated from further circuit elements; operating the charge measuring device in such a way that a voltage is present at the second pole of the capacitor and a drain-source current flows through the field-effect transistor, and ascertaining with the charge measuring device a relationship between the voltage at the second pole of the capacitor and the drain-source current; comparing the relationship with a previously ascertained or calculated reference relationship between the voltage present at the second pole of the capacitor and the drain-source current and deriving a change in charge quantity stored in the capacitor via the charge accumulation device.

8. The method according to claim 7, which comprises deriving, with an amplifier, the voltage present at the second pole of the capacitor from a current flowing through the field-effect transistor.

9. The method according to claim 7, which comprises identifying an effect resulting from a beam of charged particles or as a result of an electrical field with a high field strength on the integrated semiconductor circuit by evaluating the change in the relationship between the voltage coupled in via the second pole of the capacitor and the drain-source current and identifying the change in charge thus ascertained as an effect caused by a beam of charged particles or an effect of an electrical field with a high field strength.

10. The method according to claim 7, wherein said capacitor, said field-effect transistor and said charge accumulation device are embodied using metal oxide semiconductor technology or complementary metal oxide semiconductor technology.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

(1) FIG. 1 shows a schematic illustration of a charge measuring device in accordance with a first embodiment;

(2) FIG. 2 shows a charge measuring device in accordance with a second embodiment;

(3) FIG. 3 shows a further embodiment of a charge measuring device; and

(4) FIG. 4 shows yet a further embodiment of a charge measuring device.

DESCRIPTION OF THE INVENTION

(5) FIG. 1 shows an embodiment of a charge measuring device 1. Such a charge measuring device comprises a capacitor 2 having a pole 3 and a further pole 4. In addition, the charge measuring device comprises a field-effect transistor 5 with a source connection 6, a drain connection 7 and a gate connection 8. In addition, the charge measuring device 1 comprises a charge accumulation device 9, which is in the form of an antenna, for example. Both the capacitor 2 and the field-effect transistor 5 and also the charge accumulation device 9 are formed jointly in an integrated semiconductor circuit. In this case, any known manufacturing technology can be used which is capable of forming field-effect transistors, capacitors and a charge accumulation device in the form of a metallic surface, for example. Preferably, the individual components, namely the capacitor 2, the field-effect transistor 5 and the charge accumulation device 9, are embodied using MOS (metal oxide semiconductor) technology or CMOS (complementary metal oxide semiconductor) technology. The field-effect transistor is in the form of a normally blocking n-type field-effect transistor on a silicon substrate, for example.

(6) The capacitor 2 can be formed by means of a so-called PIP technology or MIM technology or between two regular metal planes or as a transistor (varactor). In this case, the capacitor electrodes using PIP technology are structures produced from polysilicon which are insulated from one another by an insulator, for example composed of so-called interpolyoxide. Interpolyoxide is similar to silicon dioxide.

(7) In the case of MIM technology, the metallic structures are separated by an insulator. The electrodes can be produced, for example, from titanium nitride and the insulator can be produced from silicon nitride (Si.sub.3N.sub.4) or the like. Any other desired technologies can likewise be used to form the capacitor.

(8) When using two regular metal planes as capacitor, the electrodes are realized in two different or identical metal planes. In this case, the normal intermetal dielectric is used as dielectric. A capacitor in a plane can be realized, for example, by means of finger-like electrode structures meshing with one another.

(9) When using a transistor, the bulk or the trough is used as one electrode and the gate produced from polysilicon is used as the second electrode. The gate oxide performs the task of the dielectric. When using a transistor as capacitor, the polarity of the capacitor is critical: only the gate is highly insulated.

(10) The charge measuring device 1 in the jointly manufactured integrated semiconductor circuit is produced in such a way that one pole 3 of the capacitor 2, the charge accumulation device 9 and the gate connection 8 of the field-effect transistor 5 are conductively connected to one another and, at the same time, are insulated from all further elements in the integrated semiconductor circuit. A decisive advantage of this embodiment consists in that all of the components of the charge measuring device 1 can be produced in the normal manufacturing process of an integrated semiconductor circuit, in which field-effect transistors, capacitors and generally also electrically conductive surfaces or conductors which can act as charge accumulation device are formed. No further process steps are required, as is required for manufacturing storage cells, for example. The charge measuring device 1 can therefore be introduced into virtually any integrated circuit which is manufactured by means of a conventional technology without any notable additional expenditure.

(11) The charge accumulation device 9 is preferably in the form of a metallic surface, which is arranged in the interlevel insulator close to the surface of the integrated semiconductor circuit. In order to achieve sufficient insulation, the charge accumulation device 9 is completely surrounded by an insulator in a series of embodiments. In other embodiments, which are intended for an application in a vacuum, for example, the charge accumulation device 9 can be guided to the surface of the integrated circuit in order to be able to apply charges to the charge accumulation device.

(12) In the case of the charge measuring device shown in FIG. 1, charges can be accumulated via the charge accumulation device 9 and then stored in the capacitor 2. Since one pole 3 (in the same way as the charge accumulation device 9 and the gate connection 8 or the associated gate 12 of the field-effect transistor 5) are insulated, the charge cannot escape without any external influence and remains on the capacitor. If the field-effect transistor 5 is now integrated in a driver circuit and the further pole 4 of the capacitor 2 is interconnected like a gate connection of the field-effect transistor 5, the field-effect transistor 5 demonstrates a different response, depending on the charge stored in the capacitor 2, in comparison with circuitry in which the gate connection 8 would be actuated directly. During operation, therefore, a relationship results between the voltage U.sub.out 10 present at the further pole 4 and the drain-source current I.sub.DS 11 of the field-effect transistor 5 which is set for this purpose. It is possible to draw a conclusion in respect of the charge stored in the capacitor 2 from the relationship between the voltage U.sub.out 10 present at the further pole 4 and the drain-source current I.sub.DS 11 flowing through the field-effect transistor 5.

(13) In a simplified diagram, the capacitor 2 and the charge stored thereon can be regarded as a voltage source, which increases or decreases the voltage U.sub.out 10 present at the further pole 4 so that, for example, the threshold voltage of the field-effect transistor 5 which is intended to be applied to the further pole 4 of the capacitor 2 differs from the threshold voltage which would be applied to the gate connection 8 of the field-effect transistor 5 by the voltage which represents the charge stored on the capacitor owing to the capacitance of the capacitor.

(14) In order to determine the charge stored on the capacitor 2, therefore, in one embodiment the field-effect transistor 5 is connected in such a way that a current flow takes place therein. The drain-source current I.sub.DS 11 is set in relationship with the voltage U.sub.out 10 present at the further pole 4 of the capacitor 2. Therefore, the charge which is stored in the capacitor 2 can be ascertained via the measurement of this voltage U.sub.out 10 and the drain-source current I.sub.DS 11. For this purpose, knowledge of the capacitance of the capacitor 2 is necessary.

(15) In a preferred embodiment, the charge measuring device 1 is formed jointly with other circuits in a microchip in order to be used, for example, as a sensor for an FIB attack. For this purpose, the charge accumulation device 9 is designed, for example, in the form of a metallic surface close to a surface of the microchip in the interlevel insulation. Even in the case of weak ion currents which are used for scanning the microchip, positive charges accumulate on the surface of said microchip. In order to compensate for these charges, a charge transfer takes place in such a way that negative charges accumulate on the charge accumulation device 9, which acts as antenna. By virtue of this charge transfer, a voltage arises in the capacitor 2 and at the gate 12. Even in the case of very low ion currents, the voltages arising in the capacitor 2 and at the gate 12 are generally so high that they are above the tunnel threshold above which individual charge carriers can tunnel through the insulation of the gate 12 or the capacitor 2. Owing to the tunneling of the charges, the voltage present at the gate 12 or at the capacitor 2 is reduced. If the charges adhering to the surface of the microchip are neutralized, the mirror charges flow away from the charge accumulation device 9 (the antenna) again. However, the charges which have been tunneled in the capacitor 2 or at the gate 12 remain on the capacitor 2, with the result that a charge remains stored in the capacitor 2. This can also be proven after termination of the FIB attack at any time. A change in charge with respect to a reference state can therefore be determined at any time.

(16) In general, it is also impossible to compensate for the charge transferred to the capacitor by virtue of such a tunnel operation by the application of an opposite charge equal in size on the microchip via back-tunneling of the charge. Although a tunnel operation in the opposite direction can cause precise compensation to be effected, this would appear to be practically impossible, however. Owing to the insulation of the charge accumulation device 9, of one pole 3 of the capacitor 2 and of the gate 12 and of the gate connection 8, a direct discharge cannot be brought about. It is thus also possible in any case to retrospectively prove such an attack even when the attack took place while the microchip was not in operation.

(17) FIG. 2 shows a further embodiment of a charge measuring device 1. Identical technical features are identified by the same reference symbols and, when not described otherwise, have an identical or the same design as the features and components described in relation to other figures. In the embodiment illustrated in FIG. 2, the source connection 6 of the field-effect transistor 5 is connected in series with a current measuring or current regulating device 21.

(18) A current measuring/current regulating device 21 is in this case understood to mean an apparatus which either determines a current flowing through said current measuring/current regulating device or seeks to bring about a determined current flow through said current measuring/current regulating device.

(19) In addition, the charge measuring device 1 has an amplifier 22, whose output 23 is conductively connected to the further pole 4 of the capacitor 2. Depending on the drain-source current I.sub.DS 11 flowing in the current measuring/current regulating device 21, the voltage present at the further pole 4 of the capacitor 2 is derived by means of the amplifier 22. When considered otherwise, the amplifier is coupled-back via the capacitor 2 and the field-effect transistor 5. If the current measuring/current regulating device 21 is operated in such a way that a preset drain-source current I.sub.DS 11 flows through the field-effect transistor 5, the voltage U.sub.out 10 derived from this drain-source current I.sub.DS 11 via the amplifier 22 at the further pole 4 of the capacitor 2 indicates the relationship between the voltage U.sub.out 10 and the drain-source current I.sub.DS 11 directly. Therefore, U.sub.out 10, the voltage present at the further pole 4 of the capacitor 2, is a direct measure of the charge stored on the capacitor 2. This applies whenever the amplifier 22 is not being operated at saturation and when the gain of said amplifier is sufficiently great, as is the case, for example, in conventional operational amplifiers. The voltage U.sub.out 10 which is set is, in the case of a preset drain-source current I.sub.DS 11, preset by the capacitance 2 and the charge stored thereon. In the case of knowledge of the capacitance of the capacitor 2, the charge or the change in charge with respect to a reference state which is stored on the capacitor 2 can be calculated in relation to a reference voltage U.sub.out,Ref.

(20) FIG. 3 shows, schematically, a further embodiment of a charge measuring device 1 which is similar to that shown in FIG. 2. The embodiment shown in FIG. 3 differs from that shown in FIG. 2 in that the current measuring/current regulating device 21 is not arranged in the source branch, but in the drain branch of the circuit. This means that the drain connection 7 is connected to the current measuring/current regulating device 21. Otherwise, the mode of operation of the charge measuring device 1 is analogous to that shown in FIG. 2.

(21) The amplifier 22 and the current measuring/current regulating device 21 can each be embodied externally or entirely or partially within the semiconductor circuit in which the field-effect transistor 5, the capacitor 2 and the charge accumulation device 9 are also formed.

(22) FIG. 4 shows schematically, by way of example, possible circuitry. The source connection 6 of the field-effect transistor 5 of the charge measuring device is connected to ground 31. The gate connection 8 is connected to one pole 3 of the capacitor 2 and the charge accumulation device 9, in the form of an antenna. The gate 12 of the field-effect transistor 5, one pole 3 of the capacitor and the charge measuring device 1 are insulated with respect to other components of the integrated circuit.

(23) The field-effect transistor 5 and an identically designed, matched comparison transistor 32 are each arranged as load in a current mirror 35 formed by two field-effect transistors, denoted as mirror transistors 33, 34. Gate connections 37, 38 of the mirror transistors 33 and 34 are each at the same potential, which is derived from the potential present at the drain connection 39 of one mirror transistor 33. This ensures that the drain-source current I.sub.DS1 41 through one mirror transistor 33 and one branch 43 of the current mirror 35 is equal to the drain-source current I.sub.DS2 42 through the other mirror transistor 34 and the other branch 44.

(24) The comparison transistor 32 is part of a further current mirror 45 together with a field-effect transistor, denoted here as coupling-in transistor 46. A gate connection 47 of the comparison transistor 32 and a gate connection 48 of the coupling-in transistor 46 are conductively connected to one another, wherein the potential thereof is derived from that of the drain connection 49 of the coupling-in transistor 46. The coupling-in transistor 46 is fed a preset constant current I.sub.0 50. This predetermines that a current of the same magnitude as the constant current I.sub.0 flows through the comparison transistor 32, through which the mirror current I.sub.DS2 42 flows as well. Therefore, I.sub.DS2 is equal to I.sub.0. Owing to the current mirror 35, the same applies to the mirror current I.sub.DS1 41, which is kept identical to the mirror current I.sub.DS2 42 by virtue of the current mirror 35. Therefore, the drain-source current I.sub.DS 11 which flows through the field-effect transistor 5 is determined and specified by the constant current I.sub.0. In order to achieve this current flow through the field-effect transistor 5, it is necessary for a corresponding potential to be applied to the further pole 4 of the capacitor 2, which potential together with the possibly stored charge on the capacitor 2, as described above, then produces a corresponding gate voltage at the gate connection 8.

(25) The voltage U.sub.out 10 at the further pole 4 is produced by means of an amplifier 22 in the form of an operational amplifier, for example, the output 23 of said amplifier being connected to the further pole 4 of the capacitor 2. In this embodiment, the amplifier 22 is in the form of a differential amplifier and is actuated by the voltage drops across the field-effect transistor 5 and the comparison transistor 32 at the node 52, which corresponds to the drain connection 7 of the field-effect transistor 5, and at the node 53, which corresponds to the drain connection 54 of the comparison transistor 32. If the transistor 32 is matched optimally to the field-effect transistor 5, there is the same voltage drop across both transistors when the same current flows through the two transistors. This is brought about by virtue of the current mirror 35 if the operational amplifier produces a suitable voltage at its output 23. In the case of a sufficiently high gain of the amplifier 22 and in the case of operation in which the amplifier 22 is not at saturation, the suitable voltage U.sub.out 10 is set at the output, and this voltage is only dependent on the capacitance of the capacitor 2 and the charge stored thereon. The voltage U.sub.out 10 at the further pole 4 of the capacitor 2 which forms a voltage drop across the resistor 55 is a measure of the charge stored on the capacitor 2, as already explained above. Since an amplifier provides a low-resistance output, the voltage U.sub.out 10 can be measured without the circuit being influenced notably. Thus, precise measurement of the voltage U.sub.out 10 and, by virtue of this, the charge stored on the capacitor 2 is possible, wherein the capacitance of the capacitor 2 is included in the calculation of the precise charge.

(26) The embodiment described in accordance with FIG. 4 represents exemplary circuitry. The constant current used in the circuit can also be formed via suitable circuits in the integrated circuit in which the other elements of the charge measuring device 1 are formed.

(27) The described charge measuring devices can be used in a suitable manner for identifying an FIB attack on such an integrated circuit by virtue of the charge accumulation device 9, in the form of an antenna, being arranged at a suitable location close to the surface, for example the rear side of the integrated semiconductor circuit, i.e. above the components formed on the semiconductor substrate. It is likewise possible to evaluate the voltage level which is set at the further pole 4 in a further security circuit 56 and to perform, for example, decryption of cryptographically encrypted data only when the voltage level U.sub.out 10 which is set during operation corresponds to the reference voltage level which was measured in the finished charge measuring device 1 prior to an attack. This provides the advantage that, for example, after an FIB attack in which a node has become exposed at which the decrypted data could be tapped off, this attack is identified and decryption suppressed, with the result that no decrypted data can be read from the manipulated microchip, represented by the semiconductor circuit. The relationship between the voltage at the further pole 4 of the capacitor 2 and the drain-source current I.sub.DS 11 is therefore evaluated in the security circuit 56.

(28) It is obvious to the person skilled in the art that only exemplary configurations are specified here. The field-effect transistor whose gate is connected to one pole of the capacitor and of the charge accumulation device can be formed as an n-conducting or p-conducting depletion-mode or enhancement-mode transistor. The configuration of the amplifier is not described in more detail here. However, various configurations are well known to a person skilled in the art. In addition, a current regulating device is described here. However, it is also possible for other current regulating devices or current measuring devices to be used in order to measure the drain-source current through the transistor or to set it to a preset level in order to set the voltage present at the further pole 4 in relationship therewith.

LIST OF REFERENCE SYMBOLS

(29) 1 charge measuring device 2 capacitor 3 one pole of capacitor 4 further pole of capacitor 5 field-effect transistor 6 source connection 7 drain connection 8 gate connection 9 charge accumulation device 10 U.sub.out 11 drain-source current I.sub.DS 12 gate 21 current measuring/current regulating device 22 amplifier 23 output 31 ground 32 comparison transistor 33 mirror transistor 34 mirror transistor (other) 35 current mirror 37 gate connection of one mirror transistor (33) 38 gate connection of other mirror transistor (34) 39 drain connection of one mirror transistor (33) 41 first drain-source current I.sub.DS1 42 second drain-source current I.sub.DS2 43 one branch 44 another branch 45 further current mirror 46 coupling-in transistor 47 gate connection of comparison transistor (32) 48 gate connection of coupling-in transistor (46) 49 drain connection of coupling-in transistor (46) 50 constant current I.sub.0 52 node (equivalent to drain connection 7 of field-effect transistor 5) 53 node (equivalent to drain connection 54 of comparison transistor 32) 54 drain connection of comparison transistor (32) 55 resistor