Solar cell employing nanocrystalline superlattice material and amorphous structure and method of constructing the same
09947824 ยท 2018-04-17
Assignee
Inventors
- Gopal G. Pethuraja (Albany, NY, US)
- Roger E. Welser (Providence, RI, US)
- Elwood J. Egerton (Hot Springs, SD, US)
- Ashok K. Sood (Brookline, MA, US)
Cpc classification
H01L31/075
ELECTRICITY
H01L31/035254
ELECTRICITY
H01L31/1884
ELECTRICITY
H01L31/022441
ELECTRICITY
Y02P70/50
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H01L31/02327
ELECTRICITY
H01L31/022466
ELECTRICITY
H01L31/202
ELECTRICITY
H01L31/02168
ELECTRICITY
Y02E10/545
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y02E10/548
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H01L31/03921
ELECTRICITY
International classification
H01L21/00
ELECTRICITY
H01L31/20
ELECTRICITY
H01L31/0232
ELECTRICITY
H01L31/0352
ELECTRICITY
H01L31/18
ELECTRICITY
Abstract
A solar cell employing nanocrystalline superlattice material and amorphous structure and method of constructing the same provides improved efficiency when converting sunlight to power. The photovoltaic (PV) solar cell includes an intrinsic superlattice material deposited between the p-doped layer and the n-doped layer. The superlattice material is comprised of a plurality of sublayers which effectively create a graded band gap and multi-band gap for the superlattice material. The sublayers can include a nanocrystalline Si:H layer, an amorphous SiGe:H layer and an amorphous SiC:H layer. Varying the thickness of each layer results in an effective energy gap that is graded as desired for improved efficiency. Methods of constructing single junction and parallel configured two junction solar cells include depositing the various layers on a substrate such as stainless steel or glass.
Claims
1. A method of fabricating a photovoltaic (PV) device having 180 degree symmetry, comprising: (a) depositing a first transparent conductive oxide (TCO) layer on a first side of a substrate; (b) rotating the substrate by 180 degrees; (c) depositing a second TCO layer on the second side of the substrate; (d) depositing a first PIN structure on the second TCO layer; (e) rotating the substrate by 180 degrees; (f) depositing a second PIN structure on the first TCO layer; (g) depositing a third TCO layer on the second PIN structure; (h) rotating the substrate by 180 degrees; and (i) depositing a fourth TCO layer on the first PIN structure.
2. The method of claim 1, wherein the substrate is transparent.
3. The method of claim 1, wherein the substrate comprises glass.
4. The method of claim 1, further comprising: (j) depositing a back reflector on the fourth TCO layer; (k) rotating the substrate by 180 degrees; and (l) depositing an anti-reflective coating on the third TCO layer.
5. The method of claim 1, wherein (d) depositing a first PIN structure on the second TCO layer further comprises: (d1) depositing a bottom n layer; (d2) depositing an amorphous Si:H buffer layer; (d3) depositing a first nanocrystalline Si:H layer; (d4) depositing an amorphous SiGe:H layer; (d5) repeating (d3) and (d4) between 20-50 times; (d6) depositing a second nanocrystalline Si:H layer; (d7) depositing an amorphous SiC:H layer; (d8) repeating (d6) and (d7) between 20-50 times; and (d9) depositing a top p+ layer.
6. The method of claim 1, wherein the first PIN structure is identical to the second PIN structure.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The invention description below refers to the accompanying drawings, of which:
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DETAILED DESCRIPTION
(10) Improved efficiency of solar cells is achieved by employing a nanocrystalline superlattice material having a combination of sublayers. According to illustrative embodiments, the superlattice material has an effective energy gap that is graded from the collective combination of sublayers. The term nanocrystalline as used herein refers to the size of crystals or crystalline region being in the scale of nanometers. In an illustrative embodiment, in the nanocrystalline silicon layer, the silicon crystals are in the range of size from approximately 5 to 15 nm embedded in an amorphous silicon matrix.
(11) Reference is made to
(12) As shown in
(13) Reference is now made to
(14)
(15) A flow chart of a procedure 500 for fabricating or otherwise manufacturing a solar cell having an amorphous and nanocrystalline superlattice structure is illustrated in
(16) In the next stage of fabrication an nanocrystalline Si:H layer is fabricated at step 514 and next an amorphous SiC:H layer is fabricated fabricated at step 516, which creates quantum barrier. The steps 514 and 516 are repeated approximately 20 to 50 times that creates the second set of superlattice. The wider band gap barrier layer yields higher voltage.
(17) Finally at step 518 a p+ layer is deposited. The light from the sun is absorbed in the superlattice layer described herein. The quantum well and barrier induced mini and intermediate bands generates extra electron-hole pairs. Internal electrostatic force drive electrons to n+ layer and holes to p+ layer.
(18) In order to create an optimized solar cell device structure, there are several parameters to be considered in fabricating the device. In the superlattice layer, three different absorption coefficient layers are periodically stacked. The number of nanocrystalline layers are based on optical transmittance and absorption analysis, which results in approximately 40 nc-Si layers in the superlattice absorber. The nanocrystalline layer consists of nm sized crystals embedded in the amorphous matrix. In the nanocrystalline layer, amorphous and crystalline volume ratio of approximately 50% is optimal. A layer of ITO will serve as the top layer of the solar cell embodiment.
(19) Transport of charge carrier without loss is significant for realizing high efficiency device. An optimized a-SiC:H quantum barrier layer will yield a higher and uniform internal electric field and hence increases drift lengths (L.sub.drift=E) of charge carriers. For effective collection of charge carriers, thickness of intrinsic layer should be comparable to the drift length (t.sub.L-layer>L.sub.drift). The thickness of the intrinsic layer can be reduced to achieve optimal carrier collection. In single junction cell, reduction of intrinsic layer thickness leads higher light transmission without generating electron-hole pairs. Reference is made to
(20) With reference to
(21) At step 708 of the procedure, a TCO layer 612 top contact is deposited and the substrate is then rotated 180 degrees at step 709. Then at step 710 a TCO layer 614 is deposited and at step 711 the metal contacts and back reflector 616. The structure is again rotated 180 degrees at step 713 and the top AR coating 618 is deposited at step 714.
(22) Various illustrative embodiments and methods of constructions have now been described, and the structure and construction will be apparent to those having ordinary skill. The solar cell includes a superlattice material and can be any combination of sublayers to achieve solar cell efficiency as described herein. The applications and implementations should be readily apparent to those skilled in the art.
(23) The foregoing has been a detailed description of illustrative embodiments of the invention. Various modifications and additions can be made without departing from the spirit and scope of this invention. Each of the various embodiments described above may be combined with other described embodiments in order to provide multiple features. Furthermore, while the foregoing describes a number of separate embodiments of the apparatus and method of the present invention, what has been described herein is merely illustrative of the application of the principles of the present invention. For example, the illustrative embodiments can include additional layers to perform further functions or enhance existing, described functions. Likewise, while not shown, the electrical connectivity of the cell structure with other cells in an array and/or an external conduit is expressly contemplated and highly variable within ordinary skill. More generally, while some ranges of layer thickness and illustrative materials are described herein. It is expressly contemplated that additional layers, layers having differing thicknesses and/or material choices can be provided to achieve the functional advantages described herein. In addition, directional and locational terms such as top, bottom, center, front, back, above, and below should be taken as relative conventions only, and not as absolute. Furthermore, it is expressly contemplated that various semiconductor and thin films fabrication techniques can be employed to form the structures described herein. Accordingly, this description is meant to be taken only by way of example, and not to otherwise limit the scope of this invention.