DIGITAL HYBRID MODE POWER AMPLIFIER SYSTEM

Abstract

A RF-digital hybrid mode power amplifier system for achieving high efficiency and high linearity in wideband communication systems is disclosed. The present invention is based on the method of adaptive digital predistortion to linearize a power amplifier in the RF domain. The power amplifier characteristics such as variation of linearity and asymmetric distortion of the amplifier output signal are monitored by the narrowband feedback path and controlled by the adaptation algorithm in a digital module. Therefore, the present invention could compensate the nonlinearities as well as memory effects of the power amplifier systems and also improve performances, in terms of power added efficiency, adjacent channel leakage ratio and peak-to-average power ratio. The present disclosure enables a power amplifier system to be field reconfigurable and support multi-modulation schemes (modulation agnostic), multi-carriers and multi-channels. As a result, the digital hybrid mode power amplifier system is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems, where baseband I-Q signal information is not readily available.

Claims

1. (canceled)

2. A method of adaptive digital predistortion, the method comprising: receiving a digital signal at a reconfigurable digital module including a crest factor reduction (CFR) block and a digital predistorter; processing, by the CFR block, the digital signal to provide a peak reduced signal; processing, by the digital predistorter, the peak reduced signal to provide a predistorted signal; transmitting the predistorted signal to a power amplifier portion; outputting, by the power amplifier portion, one or more RF output signals; receiving, at a feedback portion, a part of the one or more RF output signals; converting, by the feedback portion, the part of the one or more RF output signals to a digital feedback signal; receiving, by the reconfigurable digital module, the digital feedback signal; and reconfiguring the reconfigurable digital module.

3. The method of claim 2 wherein processing, by the digital predistorter, includes utilizing a predistortion polynomial.

4. The method of claim 3 wherein reconfiguring the reconfigurable digital module further comprises updating the predistortion polynomial using the digital feedback signal.

5. The method of claim 4 wherein updating the predistortion polynomial further comprises: searching locations of a main channel signal; determining an adjacent channel power level or an adjacent channel power ratio using the main channel signal; and determining, using a multi-directional search algorithm, one or more coefficients associated with the predistortion polynomial using the adjacent channel power level or the adjacent channel power ratio.

6. The method of claim 2 wherein reconfiguring the reconfigurable digital module further comprises reconfiguring at least one of a digital field programmable gate array, digital-to-analog converters, analog-to-digital converters, and a phase-locked loop.

7. The method of claim 2 wherein the power amplifier portion is responsive to the predistorted signal.

8. The method of claim 2 wherein the one or more RF output signals corresponds to the predistorted signal.

9. The method of claim 2 wherein converting the part of the one or more RF output signals to the digital feedback signal further comprises: sampling, by a directional coupler, the part of the one or more RF output signals; converting the part of the one or more RF output signals to an intermediate frequency (IF) analog signal; and converting the IF analog signal to the digital feedback signal.

10. The method of claim 2 wherein the digital signal includes a plurality of digital data streams.

11. The method of claim 10 further comprising up-converting, by the reconfigurable digital module, the plurality of digital data streams to an intermediate frequency.

12. The method of claim 2 wherein the reconfigurable digital module further includes an analog to digital converter.

13. The method of claim 12 further comprising: receiving an analog signal at the reconfigurable digital module; and converting the analog signal to the digital signal.

14. A method of adaptive digital predistortion, the method comprising: receiving a digital signal at a reconfigurable digital module including a digital predistorter; processing, by the digital predistorter, the digital signal to provide a predistorted signal; transmitting the predistorted signal to a power amplifier portion; outputting, by the power amplifier portion, one or more RF output signals; receiving, at a feedback portion, a part of the one or more RF output signals; converting, by the feedback portion, the part of the one or more RF output signals to a digital feedback signal; receiving, by the reconfigurable digital module, the digital feedback signal; and reconfiguring the reconfigurable digital module.

15. The method of claim 14 further comprising processing, by a crest factor reduction (CFR) block configured to reduce peak to average power ratio in the reconfigurable digital module, the digital signal.

16. The method of claim 14 further comprising determining, by the reconfigurable digital module, a gate bias voltage of the power amplifier portion; and transmitting the gate bias voltage to the power amplifier portion.

17. The method of claim 16 wherein determining the gate bias voltage further comprises monitoring a temperature associated with the power amplifier portion.

18. The method of claim 14 further comprising: sweeping a local oscillation signal associated with the part of the one or more RF output signals; finding one or more main channels of the power amplifier portion; and detecting, for each of the one or more main channels, an adjacent channel power level or an adjacent channel power ratio.

19. The method of claim 14 further comprising: determining a clipping error; providing a clipping error restoration path coupling the reconfigurable digital module to an output of the power amplifier portion; and transmitting a clipping error restoration signal from the reconfigurable digital module to the output of the power amplifier portion.

20. The method of claim 14 wherein processing, by the digital predistorter, includes utilizing a predistortion polynomial.

21. The method of claim 20 wherein reconfiguring the reconfigurable digital module further comprises updating the predistortion polynomial using the digital feedback signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Further objects and advantages of the present invention can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings in which:

[0014] FIG. 1 is a block diagram showing the basic form of a digital hybrid mode power amplifier system.

[0015] FIG. 2 is a block diagram showing a simple digital hybrid mode power amplifier system according to one embodiment of the present invention.

[0016] FIG. 3 is a block diagram showing polynomial based predistortion in a digital hybrid mode power amplifier system of the present invention.

[0017] FIG. 4 is a flow chart of the multi-directional search algorithm applied for self-adaptation predistortion in a digital hybrid mode power amplifier system of the present invention.

[0018] FIG. 5 is a block diagram showing a digital hybrid mode power amplifier system implemented with optional or alternative multichannel digital input, DQM and UPC-based clipping restoration path according to another embodiment of the present invention.

[0019] FIG. 6 is a block diagram showing a digital hybrid mode power amplifier system implemented with DQM according to another embodiment of the present invention.

[0020] FIG. 7 is a block diagram showing a digital hybrid mode power amplifier system implemented with AQM according to another embodiment of the present invention.

[0021] FIG. 8 is a block diagram showing a digital hybrid mode power amplifier system implemented with DUO and UPC-based clipping error restoration path according to another embodiment of the present invention.

[0022] FIG. 9 is a block diagram showing a digital hybrid mode power amplifier system implemented with AQM and AQM-based clipping error restoration path according to another embodiment of the present invention.

[0023] FIG. 10 is a block diagram showing the analog quadrature modulator compensation structure.

DETAILED DESCRIPTION OF THE INVENTION

[0024] The present invention is a novel RF-in/RF-out PA system that utilizes an adaptive digital predistortion algorithm. The present invention is a hybrid system of digital and analog modules. The interplay of the digital and analog modules of the hybrid system both linearize the spectral regrowth and enhance the power efficiency of the PA while maintaining or increasing the wide bandwidth. The present invention, therefore, achieves higher efficiency and higher linearity for wideband complex modulation carriers.

[0025] FIG. 1 is a high level block diagram showing the basic system architecture which can be thought of, at least for some embodiments, as comprising digital and analog modules and a feedback path. The digital module is the digital predistortion controller 14 which comprises the PD algorithm, other auxiliary DSP algorithms, and related digital circuitries. The analog module is the main power amplifier 12, other auxiliary analog circuitries such as DPA, and related peripheral analog circuitries of the overall system. The present invention is a black box, plug-and-play type system because it accepts RF modulated signal 10 as its input, and provides a substantially identical but amplified RF signal 13 as its output, therefore, it is RF-in/RF-out. The feedback path essentially provides a representation of the output signal to the predistortion controller 14. The present invention is sometimes referred to as a digital hybrid mode power amplifier (DHMPA) system hereinafter.

[0026] FIG. 2. is a block diagram showing a simple digital hybrid mode power amplifier system according to one embodiment of the present invention. The embodiment in FIG. 2. is very similar to the architecture disclosed in U.S. patent application Ser. No. 11/799,239, incorporated here in by reference, except that (i) the RF modulated signal 10, VRF, only goes through the down converter 20, (ii) a digital multiplier 31 is used in lieu of analog multipliers, and (iii) the predistorted signal, V.sub.p, is up-converted to IF band, then converted into an analog IF signal by DAC 30, and finally modulated into V.sub.in RF signal by mixer 311 before being provided as an input to PA 12 for wireless transmission.

[0027] FIGS. 5-9 are block diagrams showing more sophisticated embodiments of DHMPA system, where like elements are indicated with like numerals. The five embodiments of FIGS. 5-9 apply crest factor reduction (CFR) prior to the PD with an adaptation algorithm in one digital processor, so as to reduce the PAPR, EVM and ACPR and compensate the memory effects and variation of the linearity due to the temperature changing of the PA. The digital processor can take nearly any form; for convenience, an FPGA implementation is shown as an example, but a general purpose processor is also acceptable in many embodiments. The CFR implemented in the digital module of the embodiments is based on the scaled iterative pulse cancellation presented in patent application U561/041,164, filed Mar. 31, 2008, entitled An Efficient Peak Cancellation Method For Reducing The Peak-To-Average Power Ratio In Wideband Communication Systems, incorporated herein by reference. The CFR is included to enhance performance and hence optional. The CFR can be removed from the embodiments without affecting the overall functionality.

[0028] FIG. 5 is a block diagram showing a DHMPA system according to one embodiment of the present invention (the FIG. 5. System). The FIG. 5. System has a dual mode of RF 500 and/or multi-carrier digital signal 505 at the input, and an RF signal at the output 510. The dual mode of signal input allows maximum flexibility: RF-in (the RF-in Mode) or baseband digital-in (the Baseband-in Mode). The FIG. 5. System comprises three key portions: a reconfigurable digital (hereinafter referred as FPGA-based Digital) module 515, a power amplifier module 520 and a feedback path 525.

[0029] The FPGA-based Digital part comprises a digital processor 530 (e.g. FPGA), digital-to-analog converters 535 (DACs), analog-to-digital converters 540 (ADCs), and a phase-locked loop (PLL) 545. Since the FIG. 5 System has a dual input mode, the digital processor has two paths of signal processing. For the RF signal input path, the digital processor has implemented a digital quadrature demodulator (DQDM), a CFR, a PD, and a digital quadrature modulator (DQM). For the baseband digital input path, a digital up-converter (DUG), CFR, PD, and a DQM are implemented.

[0030] The RF-in Mode of the FIG. 5. System has implemented a down converter (DNC) 550 prior to the FPGA-based Digital part and an ADC 540 prior to the FPGA. An analog down converted signal is provided to the FPGA-based Digital module and converted to a digital signal by the ADC 540. The digitally converted signal is demodulated by the DQDM to generate both real and imaginary signals and then PAPR of the signal is reduced by CFR. The peak reduced signal is predistorted to linearize the amplifier and is passed through a DQM to generate the real signal and then converted to an intermediate frequency (IF) analog signal by a DAC in the FPGA-based Digital part. However, it is not required in all embodiments to implement DQDM and DQM in the FPGA. If, as shown in FIGS. 7 and 9, a modulator and demodulator will not be used, then two ADC's 700 and 705 prior to the FPGA and two DAC's 710 and 715 behind the FPGA feeding AQM module 720 can be used to generate real and imaginary signals, respectively (the AQM Implementation). The embodiment of FIG. 9 differs from the embodiment of FIG. 7 by virtue of the addition of a clipping error restoration path, indicated by DAC's 900 and 905 together with second AQM logic 910, which feeds to the RF out signal in a manner similar to that shown in FIG. 5.

[0031] The Baseband-in Mode of FIG. 5. works slightly different from the RF-in Mode. Digital data streams from multi-channels as I-Q signals are coming to the FPGA-based Digital module and are digitally up-converted to digital IF signals by the DUO. From this point onwards, the Baseband-in Mode and RF-in Mode proceeds identically. These IF signals are then passed through the CFR block so as to reduce the signal's PAPR. This PAPR suppressed signal is digitally predistorted in order to pre-compensate for nonlinear distortions of the power amplifier.

[0032] In either input mode, the memory effects due to self-heating, bias networks, and frequency dependencies of the active device are compensated by the adaptation algorithm in the PD, as well. The coefficients of the PD are adapted by a narrowband feedback using a simple power detector in the feedback part as opposed to prior art predistortion techniques that use wideband feedback which requires a very high speed ADC. The predistorted signal is passed through a DQM in order to generate the real signal and then converted to an IF analog signal by the DAC 535 as shown. As disclosed above, the DQM is not required to be implemented in the FPGA, or at all, in all embodiments. If the DQM is not used in the FPGA, then the AQM Implementation can be implemented with two DACs to generate real and imaginary signals, respectively. The gate bias voltage 550 of the power amplifier is determined by the adaptation algorithm and then adjusted through the DACs 535 in order to stabilize the linearity fluctuations due to the temperature changes in the power amplifier. The PLL sweeps the local oscillation signal for the feedback part in order to, first, find the channel locations and then detect the adjacent channel power level or the adjacent channel power ratio (ACPR).

[0033] The power amplifier part comprises a UPC for a real signal (such as illustrated in the embodiments shown in FIGS. 5, 6, and 8), or an AQM for real and complex signals (such as depicted in the embodiments shown in FIGS. 7 and 9) from the FPGA-based Digital module, a high power amplifier with multi-stage drive amplifiers, and a temperature sensor. The predistorted baseband signals are up-converted by the UPC 555 and then amplified by the PA 560. In order to improve the efficiency performance of the DHMPA system, efficiency boosting techniques such as Doherty, Envelope Elimination and Restoration (EER), Envelope Tracking (ET), Envelope Following (EF), and Linear amplification using Nonlinear Components (LING) can be used, depending upon the embodiment. These power efficiency techniques can be mixed and matched and are optional features to the fundamental DHMPA system. One such Doherty power amplifier technique is presented in commonly assigned U.S. Provisional Patent Application 60/925,577, filed Apr. 23, 2007, entitled N-Way Doherty Distributed Power Amplifier, incorporated herein by reference. To stabilize the linearity performance of the amplifier, the temperature of the amplifier is monitored by the temperature sensor and then the gate bias of the amplifier is controlled by the FPGA-based Digital part.

[0034] The feedback portion comprises a directional coupler, a mixer, a low pass filter (LPF), gain amplifiers and, a band pass filter (BPF), detectors (DETs). Depending upon the embodiment, these analog components can be mixed and matched with other analog components. Part of the RF output signal of the amplifier is sampled by the directional coupler and then down converted to an IF analog signal by the local oscillation signal in the mixer. The IF analog signal is passing through the LPF, the gain amplifier, and the BPF (e.g., surface acoustic wave filter) which can capture different frequency portions of out-of-band distortions. The output of the BPF is provided to the detector and then to the ADCs of the FPGA-based Digital module in order to determine the dynamic parameters of the PD depending on output power levels and asymmetrical distortions due to the memory effects. In addition, temperature is also detected by the DET 580 to calculate the variation of linearity and then adjust gate bias voltage of the PA. More details of the PD algorithm and self-adaptation feedback algorithm can be appreciated from FIG. 3, which shows a polynomial-based predistortion algorithm and from FIG. 4, which shows in flow diagram form as steps 401 through 410 a multi-directional search algorithm which can be used in some embodiments of the invention.

[0035] In the case of a strict EVM requirement for broadband wireless access such as WiMAX or other OFDM based schemes (EVM<2.5%), the CFR in the FPGA-based Digital part is only able to achieve a small reduction of the PAPR in order to meet the strict EVM specification. In general circumstances, this means the CFR's power efficiency enhancement capability is limited. In some embodiments of the present invention, a novel technique is included to compensate the in-band distortions from CFR by use of a Clipping Error Restoration Path 590, hence maximizing the DHMPA system power efficiency in those strict EVM environments. As noted above, the Clipping Error Restoration Path has an additional DAC 520 in the FPGA-based Digital portion and an extra UPC in the power amplifier part (see FIGS. 5. & 8.). The Clipping Error Restoration Path can allow compensation of in-band distortions resulting from the CFR at the output of the power amplifier. Further, any delay mismatch between the main path and the Clipping Error Restoration Path can be aligned using digital delay in the FPGA.

[0036] FIG. 6. is a block diagram showing a DHMPA system implemented with DQM according to another embodiment of the present invention (the FIG. 6 System). It is identical to FIG. 5 System except that it does not have the Baseband-in Mode and the Clipping Error Restoration Path.

[0037] FIG. 7. is a block diagram showing a DHMPA system implemented with AQM according to another embodiment of the present invention (the FIG. 7 System). FIG. 7 System is similar to FIG. 6 System except that it has the AQM Implementation option discussed earlier. In addition, the digital processor of FIG. 7 System has implemented an analog quadrature demodulator corrector (AQDMC), a CFR, a PD, and an analog quadrature modulator corrector (AQMC).

[0038] In FIG. 7 System, the RF input signal is first down-converted to baseband digital signals, and then digitally up-converted to digital IF signals (7.5 MHz, 2.5 MHz, 2.5 MHz, 7.5 MHz). If FIG. 7 System has a Baseband-in Mode, then the digital data streams from multi-channels would be digitally up-converted to digital IF signals (7.5 MHz, 2.5 MHz, 2.5 MHz, 7.5 MHz) directly as they enter the digital processor. The CFR would then reduce the PAPR. The peak reduced signal is predistorted to linearize the DPA and is passing through two DACs for real and imaginary signals and finally through an AQM.

[0039] FIG. 10. is a block diagram showing the analog quadrature modulator compensation structure. The input signal is separated input an in-phase component X.sub.1 and a quadrature component X.sub.Q. The analog quadrature modulator compensation structure comprises four real filters {g11, g12, g21, g22} and two DC offset compensation parameters c1, c2. The DC offsets in the AQM will be compensated by the parameters c1, c2. The frequency dependence of the AQM will be compensated by the filters {g11, g12, g21, g22}. The order of the real filters is dependent on the level of compensation required. The output signals Y.sub.1 and Y.sub.Q will be presented to the AQM's in-phase and quadrature ports.

[0040] The configuration of the power amplifier part and the feedback part of FIG. 7 System are the same as FIG. 6 System.

[0041] FIG. 8. is a block diagram showing a DHMPA system implemented with DUO and the Clipping Error Restoration Path according to another embodiment of the present invention (the FIG. 8 System). FIG. 8 System is similar to FIG. 6 System except that it has the Clipping Error Restoration Path. In addition, the digital processor of FIG. 8 System has implemented a digital down converter (DDC), a CFR, a PD, and DUG.

[0042] In FIG. 8 System, the DNC frequency translates the RF signal into a low IF signal. The IF signal is then presented to the ADC whereupon it is digitally down-converted to baseband followed by CFR and PD. The output of the PD is a baseband signal which will then be digitally upconverted to an IF frequency and presented to the DAC. The output of the DAC is then further frequency translated to a RF frequency through the UPC. The configuration of the power amplifier part and the feedback part of FIG. 8 System are the same as FIG. 5 System.

[0043] FIG. 9. is a block diagram showing a DHMPA system implemented with AQM and AQM-based Clipping Error Restoration Path according to another embodiment of the present invention (the FIG. 9 System). FIG. 9 System is identical to FIG. 7 System except that FIG. 9 System has the Clipping Error Restoration Path. The Clipping Error Restoration Path in FIG. 9 System has two DACs in the FPGA-based Digital part and an AQM in lieu of the UPC in the power amplifier part (see FIGS. 5. & 8.).

[0044] FIG. 3. is a block diagram showing a predistortion (PD) part in the DHMPA system of the present invention. The PD in the present invention generally utilizes an adaptive LUT-based digital predistortion system. More specifically, the PD illustrated in FIG. 3 and in embodiments disclosed from FIG. 5 to FIG. 9 are processed in the digital processor by an adaptive algorithm, presented in U.S. patent application Ser. No. 11/961,969, entitled A Method for Baseband Predistortion Linearization in Multi-Channel Wideband Communication Systems. The PD for the DHMPA system in FIG. 3. has multiple finite impulse response (FIR) filters, that is, FIR1 301, FIR2 303, FIR3 305, and FIR4 307. The PD also contains the third order product generation block 302, the fifth order product generation block 304, and the seventh order product generation block 306. The output signals from FIR filters are combined in the summation block 308. Coefficients for multiple FIR filters are updated by the MDS algorithm based on the adjacent channel power level or the ACPR as an evaluation function.

[0045] FIG. 4. is a flow chart of a method for compensating for the PD in the DHMPA system of the present invention. It is the self-adaptation feedback part of the DHMPA system that utilizes the MDS algorithm. Operation of the predistortion compensating apparatus of FIG. 3 may be described with reference to this flow chart.

[0046] For purposes of simplicity, but not by way of limitation, WCDMA has been used as an example to illustrate the self-adaptation feedback part and the MDS algorithm. The present invention is by no means limited to WCDMA, since the present invention is standard and modulation agnostic. In WCDMA applications, 12 WCDMA channels are detected first by sweeping PLL in the feedback part (401) in order to search the activated and deactivated channels. Once channel locations are searched (402), the feedback part detects adjacent channel power level or ACPR (especially 5 MHz offset components) again by sweeping PLL (403). Then initialize predistortion and apply the MDS algorithm as follows:

[0047] At any iteration k, evaluate each coefficients set, then find the optimum set, a.sub.o.sup.k (404)

[0048] Rotation 405: rotate a.sub.o.sup.k and evaluate. If min{f(a.sub.ri.sup.k), i=1, . . . , n}<f(a.sub.o.sup.k) is achieved (406), then go to the Expansion 407; or else go to Contraction 409.

[0049] Expansion 407: expand a.sub.ri.sup.k and evaluate. If min{f(a.sub.ei.sup.k), i=1, . . . , n}<min{f(a.sub.ri.sup.k), i=1, . . . , n} is achieved (408), then set a.sub.o.sup.k=.sub.ei.sup.k; or else set a.sub.o.sup.k=a.sub.ri.sup.k and go to (1)

[0050] Contraction 409: contract a.sub.o.sup.k, evaluate, and set a.sub.o.sup.k=a.sub.ci.sup.k, then go to (1)

[0051] where, a is a vector of coefficients for multiple FIR filters, and f is the evaluation function, which is the adjacent channel power level or the ACPR.

[0052] The algorithm stops if the evaluation function is less than the minimum target value (410). This MDS algorithm is elegantly simple to be implemented.

[0053] In summary, the DHMPA system of the present invention could enhance the performance for the efficiency and linearity more effectively since the DHMPA system is able to implement CFR, DPD and adaptation algorithm in one digital processor, which subsequently saves hardware resources and processing time. The DHMPA system is also reconfigurable and field-programmable since the algorithms and power efficiency enhancing features can be adjusted like software in the digital processor at anytime.

[0054] Furthermore, since the DHMPA system accepts RF modulated signal as input, it is not necessary to use the coded I and Q channel signals in the baseband. Therefore, the performance of wireless base-station systems can be enhanced simply by replacing the existing PA modules with the DHMPA. The present invention allows a plug and play PA system solution such that existing base-station systems do not need to modify their structures and/or rebuild a new set of signal channels in order to benefit from high efficiency and high linearity PA system performance.

[0055] Moreover, the DHMPA system is agnostic to modulation schemes such as QPSK, QAM, OFDM, etc. in CDMA, GSM, WCDMA, CDMA2000, and wireless LAN systems. This means that the DHMPA system is capable of supporting multi-modulation schemes, multi-carriers and multi-channels. Other benefits of the DHMPA system includes correction of PA non-linearities in repeater or indoor coverage systems that do not have the necessary baseband signals information readily available.

[0056] Although the present invention has been described with reference to the preferred embodiments, it will be understood that the invention is not limited to the details described thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.

APPENDIX 1

Glossary of Terms

[0057] ACLR Adjacent Channel Leakage Ratio [0058] ACPR Adjacent Channel Power Ratio [0059] ADC Analog to Digital Converter [0060] AQDM Analog Quadrature Demodulator [0061] AQM Analog Quadrature Modulator [0062] AQDMC Analog Quadrature Demodulator Corrector [0063] AQMC Analog Quadrature Modulator Corrector [0064] BPF Bandpass Filter [0065] CDMA Code Division Multiple Access [0066] CFR Crest Factor Reduction [0067] DAC Digital to Analog Converter [0068] DET Detector [0069] DHMPA Digital Hybrid Mode Power Amplifier [0070] DDC Digital Down Converter [0071] DNC Down Converter [0072] DPA Doherty Power Amplifier [0073] DQDM Digital Quadrature Demodulator [0074] DQM Digital Quadrature Modulator [0075] DSP Digital Signal Processing [0076] DUC Digital Up Converter [0077] EER Envelope Elimination and Restoration [0078] EF Envelope Following [0079] ET Envelope Tracking [0080] EVM Error Vector Magnitude [0081] FFLPA Feedforward Linear Power Amplifier [0082] FIR Finite Impulse Response [0083] FPGA Field-Programmable Gate Array [0084] GSM Global System for Mobile communications [0085] I-Q In-phase/Quadrature [0086] IF Intermediate Frequency [0087] LINC Linear Amplification using Nonlinear Components [0088] LO Local Oscillator [0089] LPF Low Pass Filter [0090] MCPA Multi-Carrier Power Amplifier [0091] MDS Multi-Directional Search [0092] OFDM Orthogonal Frequency Division Multiplexing [0093] PA Power Amplifier [0094] PAPR Peak-to-Average Power Ratio [0095] PD Digital Baseband Predistortion [0096] PLL Phase Locked Loop [0097] QAM Quadrature Amplitude Modulation [0098] QPSK Quadrature Phase Shift Keying [0099] RF Radio Frequency [0100] SAW Surface Acoustic Wave Filter [0101] UMTS Universal Mobile Telecommunications System [0102] UPC Up Converter [0103] WCDMA Wideband Code Division Multiple Access [0104] WLAN Wireless Local Area Network