CIRCUIT ARRANGEMENT FOR CONTROLLING A TRANSISTOR

Abstract

A circuit arrangement for controlling a transistor with an insulated gate, a gate driver for generating a driver signal, and a capacitor parallel to the gate-source path of the transistor, wherein the gate driver is designed for generating a driver signal greater than or equal to zero volts, an inductor is provided for forming a resonant circuit with the capacitor, and a switching element is provided in the resonant circuit, which is designed for interrupting the resonant circuit after recharging the capacitor. The part of the circuit arrangement downstream of the gate driver is designed for exclusive voltage supply using the driver signal of the gate driver, and the switching element is formed by an additional transistor, a first freewheeling diode is arranged parallel to the switching element, and the inductor of the resonant circuit is arranged between the additional transistor and the gate of the transistor.

Claims

1. A circuit arrangement (1) for controlling a transistor (T1) with an insulated gate (3), with a gate driver (2) for generating a driver signal (U.sub.TR) between a positive pole (7) and a negative pole (6) with a first driver voltage (4) for activating the transistor (T1) during an activation phase (t.sub.ON) and a second driver voltage (5) for deactivating the transistor (T1) during a deactivation phase (t.sub.OFF), and with a capacitor (C) parallel to the gate (3)-source (8) junction of the transistor (T1), wherein the gate driver (2) is designed to generate a driver signal (U.sub.TR) greater than or equal to 0 V, an inductor (L) is provided for forming a resonant circuit (9) with the capacitor (C), wherein the resonant circuit (9) is designed to recharge the capacitor (C) to a negative gate-source voltage (U.sub.GS) lying below the second driver voltage (5) when deactivating the transistor (T1) with a change in the driver signal (U.sub.TR) to the second driver voltage (5), and a switching element (S) is provided in the resonant circuit (9), wherein the switching element (S) is designed to interrupt the resonant circuit (9) after recharging the capacitor (C), wherein the part of the circuit arrangement (1) downstream from the gate driver (2) is designed for exclusive voltage supply using the driver signal (U.sub.TR) of the gate driver (2), and that the switching element (S) is formed by an additional transistor (T2), and a first freewheeling diode (D1) is arranged parallel to the switching element (S), and the inductor (L) of the resonant circuit (9) is arranged between the additional transistor (T2) and gate (3) of the transistor (T1).

2. The circuit arrangement (1) according to claim 1, wherein the gate-source voltage (U.sub.GS) is negative during the entire deactivation phase (t.sub.OFF).

3. The circuit arrangement (1) according to claim 1, wherein the gate-source voltage (U.sub.GS) essentially corresponds to the first driver voltage (4) of the gate driver (2) during the activation phase (t.sub.ON).

4. The circuit arrangement (1) according to claim 1, wherein the second driver current (5) of the gate driver (2) measures 0 V.

5. The circuit arrangement (1) according to claim 1, wherein the switching element (S) is designed for activation at the first driver voltage (4) and for deactivation at the second driver voltage (5).

6. The circuit arrangement (1) according to claim 1, wherein the switching element (S) consists of a p-channel field effect transistor or PNP transistor.

7. The circuit arrangement (1) according to claim 1, wherein the gate or base terminal of the additional transistor (T2) is connected with the negative pole (6) of the gate driver (2) by means of a first resistor (R1), and the source or emitter terminal of the additional transistor (T2) is connected with the positive pole (7) of the gate driver (2).

8. The circuit arrangement (1) according to claim 1, wherein a second resistor (R2) is arranged between the inductor (L) and gate (3) of the transistor (T1).

9. The circuit arrangement (1) according to claim 8, wherein a third resistor (R3) is arranged in series with a second freewheeling diode (D2) parallel to the second resistor (R2).

10. The circuit arrangement (1) according to claim 1, wherein a fourth resistor (R4) is arranged parallel to the capacitor (C).

11. The circuit arrangement (1) according to claim 1, wherein two diametrically opposed Z-diodes (D3, D4) connected in series are arranged parallel to the capacitor (C).

Description

[0019] The present invention will be explained in greater detail below drawing reference to the figures, which exemplarily, schematically and unrestrictedly depict advantageous embodiments of the invention. Shown here on:

[0020] FIG. 1 is a circuit arrangement for controlling a transistor according to prior art,

[0021] FIG. 2 is a schematic sketch of a circuit arrangement according to the invention for controlling a transistor,

[0022] FIG. 3 is a specific configuration of a circuit arrangement according to the invention, and

[0023] FIG. 4 are the voltage progressions of the circuit arrangement according to FIG. 3 of the gate driver, and on the capacitor parallel to the gate-source junction of the transistor.

[0024] FIG. 2 shows a schematic sketch of a circuit arrangement 1 for controlling a transistor T1 with an isolated gate 3, in particular an IGBT, a MOSFET or a GaN FET or a SiC FET having a gate driver 2 for generating a driver signal U.sub.TR between a positive pole 7 and a negative pole 6. In order to control the transistor T1, the gate driver 2 outputs a driver signal U.sub.TR measuring greater than or equal to zero volts, so as to charge or discharge a capacitor C at the gate 3 of the transistor T1 to a gate-source voltage U.sub.GS. According to FIG. 4, the driver signal U.sub.TR to this end exhibits a first driver voltage 4 for activating and a second driver voltage 5 for deactivating the transistor T1. In order to reliably deactivate and lock the transistor T1, it is advantageous to charge the gate of the transistor T1 to a negative gate-source voltage U.sub.GS. Otherwise, already small voltage fluctuations or interferences can lead to an undesired activation or short-term gating of the transistor, which could also translate into a short circuit, depending on the application of the power electronic circuit (not shown).

[0025] According to the invention, this is why the capacitor C has connected to it parallel to the gate 3-source 8 junction of the transistor T1 an inductor L, which together with the capacitor C of the transistor T1 forms a resonant circuit 9. By correspondingly dimensioning the components, this resonant circuit 9, while deactivating the transistor T1, is designed to recharge the capacitor C parallel to the gate 3-source 8 junction of the transistor T1 to a negative gate-source voltage U.sub.GS lying below the second driver voltage 5. As the gate driver 2 is switched from the first 4 to the second driver voltage 5, the energy stored in the capacitor C is discharged, inducing a flow of current through the inductor L. Even if the capacitor C is discharged, this current flow is maintained, since sudden changes in current are prevented by the inductor L. The magnetic energy present in the inductor L thereby triggers a further discharging or recharging of the capacitor C to a negative gate-source voltage U.sub.GS lying below the second driver voltage 5. In addition, a switching element S is arranged in the resonant circuit 9, which makes it possible to separate the resonant circuit 9. The separated resonant circuit 9 prevents a renewed recharging of the capacitor C, so that the negative gate-source voltage U.sub.GS is maintained. In the shown circuit arrangement 1, this negative gate-source voltage U.sub.GS ensures the reliable deactivation and locking of the transistor T1. This effectively prevents an undesired activation or short-term gating of the transistor T1, which could potentially be caused by slight voltage fluctuations or interferences. The circuit arrangement 1 especially advantageously charges the capacitor C at the gate 3 of the transistor T1 to a negative voltage already at the first deactivation. Nonetheless, the complete positive first driver voltage 4 for activating the transistor T1 is available during the activation phase t.sub.ON of the transistor T1. In addition, this circuit arrangement 1 is simple in design with respect to circuit technology and inexpensive to manufacture owing to the few and simple components. In the depicted examples according to FIGS. 2 and 3, the transistor T1 is a self-locking n channel FET. Naturally, use for other transistor types is conceivable by correspondingly modifying the circuit arrangement.

[0026] In general, let it be stated that the inductor L need not absolutely be comprised of a discrete component, but rather can also consist of a line on a circuit board.

[0027] The depicted circuit arrangement 1 is also suitable for controlling transistors T1 of power electronic circuits with regularly repeating switching processes, such as in bridge circuits. Depending on the switching frequency, the deactivation phase t.sub.OFF of the transistor T1 measures a few s to several 100 ms. Given a suitable dimensioning of the resonant circuit 9, i.e., the inductor L, capacitor C and possibly present resistors, the gate-source voltage U.sub.GS remains negative during this entire deactivation phase t.sub.OFF. This not only ensures a reliable deactivation of the transistor T1, but also prevents an undesired reactivation of the transistor T1 during the deactivation phase t.sub.OFF.

[0028] As evident from the specific embodiment according to FIG. 3, the gate-source voltage U.sub.GS during the activation phase t.sub.ON essentially corresponds to the driver voltage 4. As a consequence, the entire voltage is available to the first drive voltage 4 for activating or charging the capacitor C parallel to the gate 3-source 8 junction of the transistor T1, thereby allowing fast and reliable switching processes. The slight deviations from the first driver voltage 4 are caused by the charging process of the capacitor C and potential losses in the circuit arrangement 1. By contrast, the second driver voltage 5 is 0 V, which enables an especially simple structural design for the gate driver 2, and thus the use of cost-effective gate drivers 2.

[0029] In addition, the part of the circuit arrangement 1 downstream from the gate driver 2 is designed for exclusive voltage supply using the driver signal U.sub.TB, as evident from FIGS. 2 and 3. Accordingly, only one voltage source not shown on the figures is needed for supplying voltage to the gate driver 2, so as to supply the entire circuit arrangement 1 with electrical energy. The gate driver 2 then supplies the downstream part of the circuit arrangement 1 with electrical energy via its driver signal U.sub.TR. Doing without an additional voltage supply reduces both the complexity of the entire circuit arrangement and its costs.

[0030] A first freewheeling diode D1 is arranged parallel to the switching element S in the circuit arrangement 1. Despite the open switching element S, the latter makes it possible to continue the recharging process up to a change in direction of the current flow. This change in direction of the current flow arises once the energy stored the inductor L has again been completely discharged. This corresponds to the desired end of the recharging process, since the voltage on the capacitor C lies in the range of its negative maximum at this point in time. Therefore, using the freewheeling electrode D1 makes it possible to open the switching element S at any point in time between the change from the first driver voltage 4 to the second driver voltage 5 and end of the recharging process of the capacitor C to the negative gate-source voltage U.sub.GS. This permits additional simplifications of the circuit arrangement 1, since the driver signal U.sub.TR can also be used directly to switch the switching element S.

[0031] Accordingly, the switching element S in the circuit arrangement 1 according to FIG. 3 is activated at the first driver voltage 4 of the driver signal U.sub.TR, and deactivated at the second driver voltage 5 of the driver signal U.sub.TR. As already mentioned above, no additional signal is thus required for switching the switching element S, which enables an easily realizable circuit arrangement 1.

[0032] The circuit arrangement 1 according to FIG. 3 has an especially simple design in terms of circuit technology, since the switching element S is comprised of an additional transistor T2. This makes it possible to arrange the additional transistor T2 between the inductor L and driver signal U.sub.TR, as well as to control the additional transistor T2 without additional components. While the additional transistor T2 consists of a P channel FET in the example shown, the use of a PNP transistor is also conceivable.

[0033] As shown on FIG. 3, the gate terminal of the additional transistor T2 is connected by way of a first resistor R1 with the negative pole 6 of the gate driver 2, and the source terminal is connected with the positive pole 7 of the gate driver 2. This limits the gate charging current of the additional transistor T2, while at the same time making it easy to control a P-channel FET using a low number of components. The connection between the negative pole 6 of the gate driver 2 and a ground terminal can be adjustable, but does not absolutely have to be.

[0034] It is further conceivable that no decided first freewheeling diode D1 be used, but rather that the first freewheeling diode D1 be comprised of the freewheeling diode integrated into the additional transistor T2, in particular the one integrated into the P channel FET. The component outlay for the circuit arrangement 1 can be further reduced in this way.

[0035] A second resistor R2 can be arranged between the inductor L and gate of the transistor T1. This resistor R2 determines the damping of the resonant circuit 9 for the activation process, and thus influences the charging process of the capacitor C parallel to the gate-source junction of the transistor T1. A suitable component dimensioning thereby prevents an overshoot of the gate-source voltage U.sub.GS while activating the transistor T1.

[0036] A third resistor R can be arranged in series with a second freewheeling diode D2 parallel to the second resistor R2. This third resistor R3 is used to set a varying damping for the resonant circuit 9 while deactivating the transistor T1. This makes it possible to achieve a reduction in the overshoot of the gate-source voltage U.sub.GS during deactivation and the recharging of the capacitor C associated therewith. The charging and discharging or recharging process can in this way be separately influenced, which allows optimizations in relation to the edge steepness and overshoot of the gate-source voltage U.sub.GS.

[0037] Additional simplifications arise when the capacitor C consists of the gate-source capacitor of the transistor T1. This eliminates the need for an additional capacitor C between the gate 3 and source 8.

[0038] A fourth resistor R4 can be arranged parallel to the capacitor C so as to still define the gate-source voltage U.sub.GS given no voltage supply for the gate driver 2, and thereby prevent the gate-source voltage U.sub.GS from floating.

[0039] In order to protect the gate 3 of the transistor T1 against too high a positive or negative gate-source voltage U.sub.GS, two diametrically opposed Z-diodes D3, D4 connected in series are arranged parallel to the capacitor C. In addition, the Z-diodes D3, D4 prevent an overshoot of the gate-source voltage U.sub.GS during the activation process of the transistor T1. This yields a correspondingly advantageous, steep leading edge of the gate-source voltage U.sub.GS while switching from the first driver voltage 4 to the second driver voltage 5.

[0040] In an exemplary dimensioning of components of the circuit arrangement 1 according to FIG. 3, an edge decay time from the positive gate-source voltage U.sub.GS to the negative gate-source voltage U.sub.GS is desirably less than or equal to 100 ns, so as to keep the deactivation losses of the transistor T1 low. At the same time, the edge steepness is to be less than half the period duration of the resonant circuit 9, since the process of recharging the capacitor C concludes within half a period, and a renewed overshoot is precluded by the locking behavior of the diode D1. In the dimensioning example below, a period duration T=140 ns (T=t.sub.ON+t.sub.OFF) is assumed.

[0041] A capacitor C of 5 nF, which roughly corresponds to a typical gate-source capacitor of a power FET, and an edge decay time of 70 ns correspondingly yield an inductance L of roughly 100 nH according to the formula

[00001]$L=\frac{T^2}{4.Math.{}^2.Math.C}$

[0042] Further exemplary dimensioning assumes a positive gate-source voltage U.sub.GS+ of 20 V and a negative gate-source voltage U.sub.GS of 5V. The formula

[00002]$R_{\mathrm{Ges}}=-\frac{2.Math.L.Math..Math.\ln .Math.\frac{U_{\mathrm{GS}-}}{U_{\mathrm{GS}+}}}{t},\mathrm{with}.Math..Math.t=\frac{T}{2}$

[0043] Yields an overall ohmic resistance, including all losses, for the resonant circuit of about 4 ohm. Since the gate drivers and flux voltage of the diodes must be considered in addition to the ohmic losses of the inductor and capacitor, the individual resistors must be given correspondingly smaller dimensions, or the resistor R4 parallel to the capacitor must be given larger dimensions. In an exemplary dimensioning of the resistors R2 with 3.3 ohm, this yields R3 with 1 ohm and R4 with 10 kohm.

[0044] Of course, the values actually used for the inductor, capacitor and resistors can deviate from the indicated exemplary dimensioning. Depending on the individual requirements placed on the circuit arrangement 1, as well as on the transistor T1 and gate driver 2, dimensions for components with the above exemplary values can conceivably be a power of ten higher or lower.