Radio communication

Abstract

A radio transmitter (4) comprises an encoder (5) that receives one or more variable message bits, and encodes each message bit that has a first value as a predetermined first binary chip sequence and encodes each message bit that has the opposite value as a predetermined second binary chip sequence. The radio transmitter (4) transmits data packets, each comprising (i) a predetermined synchronization portion, comprising one or more instances of the first binary chip sequence, and (ii) a variable data portion, comprising one or more encoded message bits output by the encoder. A radio receiver (9) receives such data packets. It uses the synchronization portion of a received data packet to perform a frequency and/or timing synchronization operation, and then decodes message bits from the data portion of the data packet.

Claims

1. A radio transmitter comprising an encoder configured to receive one or more variable message bits and to encode each message bit that has a first value as a predetermined first binary chip sequence and to encode each message bit that has the opposite value as a predetermined second binary chip sequence, wherein the radio transmitter is configured to transmit data packets, each comprising (i) a predetermined synchronisation portion, comprising one or more instances of the first binary chip sequence, and (ii) a variable data portion, comprising one or more encoded message bits output by the encoder; wherein the radio transmitter is configured to transmit the data packets modulated on a radio carrier signal using Gaussian frequency-shift-keying (GFSK), and wherein the modulation of the first and second binary chip sequences is such that, for each binary chip sequence of the first and second binary chip sequences, the respective phase of the radio carrier signal at the end of the binary chip sequence is the same as the respective phase of the radio carrier signal at the start of the binary chip sequence.

2. The radio transmitter of claim 1, wherein the GFSK modulation has a modulation index of approximately 0.5.

3. The radio transmitter of claim 1, wherein one or each of the first and second binary chip sequences has a bit-length that is an even number greater than or equal to four.

4. The radio transmitter of claim 1, wherein one or each of the first and second binary chip sequences consists of an equal number of zero bits and one bits.

5. The radio transmitter of claim 1, wherein the second binary chip sequence is identical to the first binary chip sequence except at a first bit position and a last bit position, at which the second binary chip sequence differs from the first binary chip sequence.

6. The radio transmitter of claim 1, wherein a first bit of the first binary chip sequence differs from a last bit of the first binary chip sequence.

7. The radio transmitter of claim 1, wherein the first binary chip sequence has maximum autocorrelation performance, over a set of all possible binary sequences having lengths equal to a length of the first binary chip sequence, subject to constraints that the sequences in the set must have an equal number of zero bits and one bits, and that each sequence in the set must have a first bit that differs in value from a last bit of the respective sequence of the set.

8. The radio transmitter of claim 1, wherein the first binary chip sequence has an autocorrelation quality of less than 0.26, determined as a ratio of a maximum sidelobe amplitude to a zero-lag peak amplitude when the first binary chip sequence is correlated with a pulse train of four sequence-repetitions.

9. The radio transmitter of claim 1, wherein the first binary chip sequence is a 16-bit sequence selected from the group consisting of: (0 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1), (1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 0), (1 1 1 0 0 1 0 1 0 0 1 1 0 1 0 0), and (0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 1).

10. The radio transmitter of claim 1, wherein the variable data portions of the data packets follow after the synchronisation portions without any gap.

11. A radio receiver configured to: receive data packets, each comprising a predetermined synchronisation portion, comprising one or more instances of a predetermined first binary chip sequence, and a variable data portion, comprising one or more encoded message bits, wherein each message bit that has a first value is encoded as the first binary chip sequence and each message bit that has the opposite value is encoded as a predetermined second binary chip sequence, wherein the data packets are modulated on a radio carrier signal using Gaussian frequency-shift-keying (GFSK), and wherein the modulation of the first and second binary chip sequences is such that, for each binary chip sequence of the first and second binary chip sequences, the respective phase of the radio carrier signal at the end of the binary chip sequence is the same as the respective phase of the radio carrier signal at the start of the binary chip sequence; use the synchronisation portion of a received data packet to perform a frequency or timing synchronisation operation, before decoding the variable data portion of the received data packet; and decode message bits from the variable data portion of the received data packet.

12. The radio receiver of claim 11, configured to demodulate the variable data portion of a received data packet using a differential-binary-phase-shift-keying (DBPSK) demodulator.

13. The radio receiver of claim 11, comprising a correlator, and configured to use the correlator for performing the frequency and/or timing synchronisation operation.

14. The radio receiver of claim 13, wherein the correlator is a fixed-coefficient correlator.

15. The radio receiver of claim 11, comprising a correlator that is switchable between two modes: a first mode in which the correlator correlates against the complete first binary chip sequence, and a second mode in which the correlator correlates against a sub-sequence of the first binary chip sequence.

16. The radio receiver of claim 12, configured to use the correlator in the first mode for processing the synchronisation portion of a received data packet, and to switch the correlator to the second mode for decoding message bits from the variable data portion.

17. The radio receiver of claim 12, wherein the sub-sequence is defined by bit positions in the first binary chip sequence at which the first and second binary chip sequences have equal values.

18. The radio receiver of claim 15, wherein the sub-sequence consists of all the bits of the first binary chip sequence except for the first and last bits of the first binary chip sequence.

19. The radio receiver of claim 13, wherein the correlator is configured to output amplitude information and wherein the radio receiver is configured to use the amplitude information to perform symbol timing synchronisation.

20. The radio receiver of claim 13, wherein the correlator is configured to output phase information and wherein the radio receiver is configured to use the phase information to perform an initial frequency synchronisation.

21. The radio receiver of claim 13, configured to use phase information from the correlator to perform on-going frequency drift tracking, and to apply appropriate adjustment or compensation if the frequency of a received signal drifts.

22. The radio receiver of claim 13, configured to use the correlator to determine whether a sub-sequence in the variable data portion of a received data packet has an approximately 0 or an approximately phase change relative to an immediately-preceding occurrence of the sub-sequence in the variable data portion, and to use a signal representative of sub-sequence phase changes from the correlator over the variable data portion to determine the message bits.

23. A radio receiver comprising a fixed-coefficient correlator that is switchable between a first mode in which the correlator is configured to correlate a received signal against a binary chip sequence, and a second mode in which the correlator is configured to correlate a received signal against a sub-sequence from the binary chip sequence, shorter than the binary chip sequence, wherein the correlator is configured, when in the second mode, to output a signal representative of a phase shift between two successive occurrences of the sub-sequence in a received signal.

24. The radio receiver of claim 23, configured to use the signal representative of a phase shift between two successive occurrences of the sub-sequence in a received signal to decode message data from a data portion of a received data packet.

25. The radio receiver of claim 23, comprising a differential-binary-phase-shift-keying (DBPSK) demodulator for demodulating the data portion of a received data packet.

26. The radio receiver of claim 23, configured to use the correlator for performing a frequency or timing synchronisation operation.

27. The radio receiver of claim 23, configured to use the correlator in the first mode for processing a synchronisation portion of a received data packet, and to switch the correlator to the second mode for decoding message bits from a data portion of the received data packet.

28. The radio receiver of claim 23, wherein the sub-sequence consists of all the bits of the binary chip sequence except for a first bit and a last bit of the binary chip sequence.

29. The radio receiver of claim 23, wherein the correlator is configured to output amplitude information and wherein the radio receiver is configured to use the amplitude information to perform symbol timing synchronisation.

30. The radio receiver of claim 23, wherein the correlator is configured to output phase information and wherein the radio receiver is configured to use the phase information to perform an initial frequency synchronisation.

31. The radio receiver of claim 23, configured to use phase information from the correlator to perform on-going frequency drift tracking, and to apply appropriate adjustment or compensation if the frequency of a received signal drifts.

32. The radio receiver of claim 23, configured to use the correlator to determine whether a sub-sequence in a data portion of a received data packet has an approximately 0 or an approximately phase change relative to an immediately-preceding occurrence of the sub-sequence in the data portion, and to use a signal representative of sub-sequence phase changes from the correlator to decode message bits from the data portion of the received data packet.

Description

(1) Certain preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

(2) FIG. 1 is a schematic drawing of a radio communication system embodying the invention;

(3) FIG. 2 is a diagram of a data packet that may be transmitted and received by the radio communication system;

(4) FIG. 3 is a schematic drawing of part of a radio transmitter embodying the invention;

(5) FIG. 4 is a plot of phase against time for two different chip sequences;

(6) FIG. 5 is schematic drawing of part of a radio receiver embodying the invention; and

(7) FIG. 6 is a state diagram for this radio receiver.

(8) FIG. 1 shows a wireless heart-rate monitor 1 which is in communication with a mobile telephone 7. Both devices embody the present invention.

(9) The wireless heart-rate monitor 1 has a heart-rate sensor 2 which is connected to a microprocessor 3 (such as an ARM Cortex M-series). The microprocessor 3 is connected to a radio transmitter 4. The radio transmitter 4 includes an encoder 5 (among other components). Other conventional components, such as memory, a battery, etc. are also present, but are omitted from the drawing for the sake of simplicity. The microprocessor 3 and radio transmitter 4 may be integrated on a single silicon chip. The monitor 1 has a radio antenna 6, which may be integrated on such a chip or external to it.

(10) The mobile telephone 7 has, among other conventional components (not shown), an antenna 8, suitable for receiving short-range radio communications from wireless-personal-area-network devices, which is connected to a radio receiver 9. The radio receiver 9 includes a fixed-coefficient correlator 10 (among other components). The radio receiver 9 is connected to a microprocessor 11 (such as an ARM Cortex M-series), which can output data for display on a screen 12, possibly via other components, such as a further microprocessor (not shown) running an operating system and appropriate software applications.

(11) In use, the wireless heart-rate monitor 1 receives periodic heart-rate readings for a human user from the heart-rate sensor 2. The microprocessor 3 processes the readings into a suitable format for transmission, and sends the message data to the radio transmitter 4. In some embodiments, the message data may already be differentially encoded, in order to improve the efficiency of the decoding operation on the radio receiver 9. The radio transmitter 4 determines whether the message data can fit within a single data packet, or if it must be split across two or more data packets. In either case, the radio transmitter 4 assembles the message data into a data portion, along with any other relevant data. The encoder 5 in the radio transmitter 4 encodes the data portion, containing the message data, to create a payload in which each 1 bit is represented by the 16-bit sequence [0 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1] and each 0 bit is represented by the sequence [1 0 0 1 1 0 1 0 1 1 0 0 1 0 1 0] (or vice versa). It prepends a synchronisation word to the payload, consisting of 15 repetitions of the first sequence, [0 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1]. A fixed preamble (e.g. of 8 chips) may be included before the synchronisation word.

(12) The radio transmitter 4 then transmits the encoded data packet from the antenna 6, modulated on a radio-frequency carrier (e.g. at around 2.4 GHz), using two-level GFSK with a modulation index of 0.5. The data packet may contain additional elements, such as a preamble, if appropriate.

(13) FIG. 2 shows an exemplary data packet structure, which includes a fixed preamble, a synchronisation portion (sync word), and a data portion. The data portion contains an access address, message bits, and a cyclic-redundancy check (CRC).

(14) The mobile telephone 7 receives the radio data packet at the antenna 8. The radio receiver 9 processes the GFSK signal using the correlator 10. The receiver 9 first correlates the received signal with the first 16-bit sequence [0 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1], in order to determine frequency and/or timing synchronisation information from the synchronisation portion.

(15) The radio receiver 9 then reconfigures the correlator 10 to correlate the received data portion with the 14-bit sub-sequence [0 0 1 1 0 1 0 1 1 0 0 1 0 1], which is the shared, middle 14 bits contained in each of the two 16-bit sequences. It processes I and Q components separately in order to determine the phase shift between successive appearances of the sub-sequence in the data portion. The radio receiver 9 decodes the message data from the phase shift information by using an initial phase reference from the synchronisation portion (which corresponds to an initial decoded bit value of 1, for instance) to decode any sequence that shifts in phase by approximately 180 degrees as having the opposite value to the immediately preceding decoded message bit, and any sequence that has approximately zero degrees of phase shift as having the same value as the immediately preceding decoded message bit.

(16) The radio receiver 9 performs on-going drift tracking while processing the data packet, based on phase information output by the correlator 10.

(17) The radio receiver 9 can then extract the message from the decoded data, check the CRC, and perform any other appropriate operations. It then passes the decoded message data to the microprocessor 11 for processing. The microprocessor 11 may process it in any appropriate way. In some embodiments, heart-rate information may be displayed graphically on the display screen 12 for the user to see.

(18) The wireless heart-rate monitor 1 and mobile telephone 7 may be configured so that heart-rate message data is transferred from the wireless heart-rate monitor 1 to the mobile telephone 7 substantially according to the Bluetooth Low Energy (BTLE) core specification version 4.0, with the exception of the physical layer. The wireless heart-rate monitor 1 and mobile telephone 7 may be equipped for two-way radio communication, using corresponding components for radio transmission in the opposite direction, although this is not essential.

(19) FIG. 3 shows greater detail of elements within a radio transmitter embodying the invention. This could be the same radio transmitter 4 as described above, or it could be a different radio transmitter.

(20) This radio transmitter first differentially encodes the data bits using a differential encoder unit 13. Each differentially encoded bit is then represented by one of two quasi-antipodal chip sequences, by an up-chipping unit 14. Each of the chips in a sequence is then feed through a GFSK filter 15 and is transmitted as a GFSK modulated signal.

(21) FIG. 4 illustrates two possible quasi-antipodal chip sequences 16, 17 that could be used by the up-chipping unit 14. The two chip sequences are the same length and differ only in the first and last chips. When, as is preferred, the modulation index is h=0.5 nominally, the phase difference between the two signals will be everywhere except for the very first chip and the very last chip in the sequences, as can be seen from FIG. 4, which shows the first five chips of both sequences 16, 17, as well as the final chip (the remaining chips are omitted for conciseness).

(22) FIG. 5 shows detail of a digital baseband processing stage of a radio receiver embodying the invention. This could be the same radio receiver 9 as described above, or it could be a different radio receiver.

(23) Steps such as filtering and residual frequency offset tracking are not shown for reasons of conciseness.

(24) The design of the radio receiver aims to optimize sensitivity while tolerating realistic channel conditions (carrier frequency offset, carrier drift, fading, etc.). It uses correlation for timing synchronization and detection.

(25) Complex-valued baseband samples are shown entering from the left side of FIG. 5. These are passed to a CORDIC unit 18, and from there to a despreader unit 19. The despreader unit 19 performs a cross correlation between an incoming chip sequence containing data and a stored replica of this chip sequence. The output of the despreader unit 19 conveys the phase difference between the two different chip sequences. This is passed to a second CORDIC unit 20, and then on to a DBPSK decoder unit 21. The incoming samples are also passed to a synchronisation unit 22 which performs timing synchronization and initial carrier frequency offset estimation.

(26) FIG. 5 contains the following abbreviations: n=chip index; m=symbol index; z(n)=complex baseband samples; z(n)=carrier-frequency offset (CFO) compensated z(n); and p(k)=complex values representing the chip sequence.

(27) The synchronization is built around a particular kind of correlator. The correlator is a data-aided joint timing and frequency estimator which exploits knowledge of the data in the received symbols to cancel the effect of the modulation on the estimate of a conventional delay-and-correlate type of carrier frequency offset estimator. The principle behind the synchronisation is described in WO 2014/167318, by the present applicant, the entire contents of which are hereby incorporated by reference.

(28) The performance of the radio receiver of FIG. 5, assuming ideal synchronisation, can be analysed as follows.

(29) For discriminator detection of FSK signalling with a modulation index of h=0.5, it is expected that E.sub.b/N.sub.012 dB for a bit error rate (BER)=0.001. When cross-correlating directly on I and Q, the underlying theory for BER in additive white Gaussian noise (AWGN) is expected to follow that for non-coherent detection of correlated binary signalling. For a modulation index=0.5, E.sub.b/N.sub.014.5 dB for a bit error rate (BER)=0.001.

(30) Discriminator detection will normally outperform non-coherent detection of correlated binary signalling for this modulation index. However, by correlating after the discriminator, the discriminator is here operating below the FM thresholda region where detector performance deteriorates rapidly.

(31) For differential detection of DBPSK, the E.sub.b/N.sub.08 dB for a bit error rate (BER)=0.001. This is 6.5 dB less compared to orthogonal detection and about 4 dB less than the case for discriminator detection of a GFSK signal given modulation index=0.5 Thus, utilizing DBPSK signalling on symbols made of GFSK modulated chips gives an inherent gain of 4 dB on the link budget. This is a very significant benefit of the present approach. This gain adds on top of the usual DSSS processing gain.

(32) The joint timing & freq. offset sync synchronisation unit 22 in FIG. 5 carries out the following cross correlation for every incoming baseband sample z.sub.n=I(n)+jQ(n):

(33) $\hat{f}=\frac{1}{2\mathrm{DT}}\arg \left\{\underset{i=0}{\overset{L-1}{.Math.}}\left[z_{n-i}{z}_{n-i-D}^{*}\right]d_i\right\},$
where L is the number of samples representing an up-sampled sync word (such as the 16-bit sequence specified above); where D is a lag which is decided at design time; and where T is the sample period.

(34) The coefficients are given as d.sub.i=p.sub.i*p.sub.i+D where p are the samples constituting the up-sampled and modulated sync word bits. The correlator should be sampled at the right point in time for the frequency offset estimate to be valid, and this time instant is when a peak is observed in the value of M.sub.n given by:

(35) $M_n^{}=\frac{.Math.C_n.Math.}{P_n},\mathrm{where}{C}_n=\underset{i=0}{\overset{L-1}{.Math.}}\left[z_{n-i}{z}_{n-i-D}^{*}\right]d_i\mathrm{and}{P}_n=\underset{i=0}{\overset{L-1}{.Math.}}{.Math.z_{n-i-D}.Math.}^2.$

(36) A valid peak in M.sub.n is determined against a programmable threshold. A successful synchronisation event is defined by the observation of a few valid peaks spaced apart in time by amounts corresponding to the sync word length, plus or minus a value, , to account for noise. This synchronization event furthermore defines the strobe time to be used for subsequent detection of the data symbols.

(37) The coefficients d.sub.i=p.sub.i*p.sub.i+D are calculated at design time.

(38) The DBPSK detection is implemented as follows.

(39) The received sequence of complex baseband samples z(n) that represents a sequence of GFSK-modulated chips is processed by the digital-baseband-correlator despreader unit 19. The chip sequence constitutes one symbol with period T.sub.S. Assuming a constant envelope A:
z(n)=Ae.sup.j(n), where (n)=.sub.0+.sub.cfon+.sub.m(n).

(40) Here, .sub.0 represents a constant phase offset between the transmitter and the receiver, while .sub.cfo represents a negligible carrier frequency offset (a non-zero carrier frequency offset will result in a constellation rotation between symbols; unless this offset is kept sufficiently small after carrier-frequency offset estimation and compensation, the bit error rate will increase). The differential phase modulation is embedded in .sub.m(n) which represents the phase relative to the previous symbol, and will take on values in {0, }.

(41) The message data bits are determined in the decoder unit 21 by observing the phase shift of .sub.m(n) between consecutive received symbols. The radio transmitter applies the same phase shift to all chips in a symbol, depending on the data to be transmitted. Each bit of the message data may therefore be differentially decoded, with no phase shift implying a 0 and a phase shift of implying a 1 (or vice versa, depending on how the differential encoding is implemented in the radio transmitter).

(42) In order to correlate N values of z(n) with a set of N complex coefficients representing N GFSM modulated chips (assuming no oversampling for now, for simplicity), the coefficients p(k) can be written as:
p(k)=e.sup.j.sup.k.

(43) Assuming, for simplicity, that .sub.cfo=0, the complex-valued correlator output at time t is then given by:

(44) $\begin{array}{c}C\left(t\right)={.Math.}_{k=0}^{N-1}z\left(n-k\right)p^{*}\left(k\right)\\ =A{.Math.}_{k=0}^{N-1}{e}^{j\left(n-k\right)}{e}^{-j{}_k}\\ =A{.Math.}_{k=0}^{N-1}{e}^{j\left({}_0+{}_m\left(n-k\right)-{}_k\right)}\\ =A{.Math.}_{k=0}^{N-1}{e}^{j\left({}_0+q\right)},q\left\{0,1\right\},\mathrm{when}\mathrm{timing}\mathrm{synchronized}\\ {}_m\left(n-k\right)-{}_k\left\{0,\right\}\\ =\mathrm{AN}{e}^{j\left({}_0+q\right)},\end{array}$
where angle(C(t))=.sub.0+g.

(45) Thus the angular difference between C(t) and C(t+T.sub.S) will be 0 or . Note that .sub.0 disappears.

(46) If the angular difference is greater than /2 or less than /2 the detector will output a 1; otherwise it will output a 0.

(47) For coherent detection, .sub.0 would need to be estimated.

(48) Symbol timing synchronization or tracking can be done by detecting the time when a peak value is observed on |C(t)|.

(49) The residual carrier frequency offset .sub.cfo is a consequence of carrier-frequency drift and initial carrier frequency offset estimation error, and can be tracked by looking at the angular difference between C(t) and C(t+T.sub.S). Thus .sub.cfo can be estimated as:

(50) $=\frac{\mathrm{angle}\left(C\left(t+T_s\right)\right)-\mathrm{angle}\left(C\left(t\right)\right)}{T_s},$
after subtracting the known phase shift (after decision) due to the modulation. The residual carrier frequency offset in [Hz] is then calculated as

(51) $\frac{1}{2}\left[\mathrm{Hz}\right].$

(52) FIG. 6 shows a finite state machine (FSM) that can orchestrate the synchronization process and data reception in a radio receiver as illustrated in FIG. 5.

(53) The state of this FSM is given by the variable syncstate. At time t=0 the FSM starts out in syncstate=0. In this state the FSM is to the right side of the dashed line in FIG. 6, and is looking for peaks in the value of M.sub.n computed by the synchronisation unit 22. For each peak, the {circumflex over (f)} value is recorded in a vector element cfoVec[MnCnt], and the peak counter MnCnt is incremented by one. When a sufficient minimum number min of such peaks with a certain distance dist between each peak has been observed, initial timing and carrier frequency offset synchronization is achieved and syncstate is incremented by one.

(54) The average time of the peaks as measured by a counter (which counts modulo the number of samples per symbol) defines the subsequent symbol boundaries (strobe timing). Additionally, an initial carrier frequency offset estimate is computed as the average of the elements in the vector cfoVec. This value, , is then passed to the CORDIC unit 18.

(55) Now, with syncstate>0, the FSM enters the left side of the dashed line in FIG. 6, for receiving the payload. In this state, the message data bits are determined in the decoder unit 21 by observing the phase shift of .sub.m(n) between consecutive received symbols, as described above. Additionally, the residual carrier frequency offset (CFO) is tracked and .sub.CFO is computed, as described above. In turn, this value is used to update (by being added to) the value in the CORDIC unit 18.