Neural network computation circuit including non-volatile semiconductor memory element

Abstract

A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.

Claims

1. A neural network computation circuit that includes a non-volatile semiconductor memory element and outputs output data of a first logical value or a second logical value, based on a result of a multiply-accumulate operation between input data of the first logical value or the second logical value and connection weight coefficients respectively corresponding to the input data, the neural network computation circuit comprising: a plurality of word lines; a first data line; a second data line; a third data line; a fourth data line; a plurality of computation units each of which includes a series connection of a first non-volatile semiconductor memory element and a first cell transistor, and a series connection of a second non-volatile semiconductor memory element and a second cell transistor, the first non-volatile semiconductor memory element having one end connected to the first data line and has a resistance value that is variable, the first cell transistor having one end connected to the second data line and a gate connected to one of the plurality of word lines, the second non-volatile semiconductor memory element having one end connected to the third data line and has a resistance value that is variable, the second cell transistor having one end connected to the fourth data line and a gate connected to one of the plurality of word lines; a word line selection circuit that places the plurality of word lines in a selection state or a non-selection state; a determination circuit that determines a magnitude relationship between voltage values or current values applied to the first data line and the third data line or the second data line and the fourth data line, to output the first logical value or the second logical value; and a current application circuit that is connected to at least one of the first data line, the second data line, the third data line, or the fourth data line, wherein the neural network computation circuit sets resistance values corresponding to the connection weight coefficients to the first non-volatile semiconductor memory element and the second non-volatile semiconductor memory element of each of the plurality of computation units, the neural network computation circuit has a function of adjusting any of the connection weight coefficients by the current application circuit applying a current to one of the first data line, the second data line, the third data line, and the fourth data line, the word line selection circuit places the plurality of word lines in the selection state or the non-selection state according to the input data, the determination circuit outputs output data, the plurality of computation units are equal in number to the input data, the plurality of computation units are connected in parallel to the first data line and the third data line, thereby causing a current value corresponding to a result of a multiply-accumulate operation to flow in the first data line or the third data line, in the adjusting of any of the connection weight coefficients, the neural network computation circuit determines a connection weight coefficient to be added, and causes the current application circuit to apply a current corresponding to the connection weight coefficient to be added determined to the first data line, the second data line, the third data line, or the fourth data line that corresponds to the connection weight coefficient to be added, and the determination circuit determines the magnitude relationship using a current value obtained by adding (i) the current applied by the current application circuit and corresponding to the connection weight coefficient to be added to (ii) the current value corresponding to the result of the multiply-accumulate operation.

2. The neural network computation circuit according to claim 1, wherein the current application circuit includes a first current source that is connected to ground and a fifth data line and outputs constant current to the fifth data line, and the fifth data line is connected to at least one of the first data line and the second data line via a first switch transistor or the third data line and the fourth data line via a second switch transistor.

3. The neural network computation circuit according to claim 1, wherein the current application circuit includes a first current source that is connected to ground and a fifth data line and outputs constant current to the fifth data line, and a second current source that is connected to ground and a sixth data line and outputs constant current to the sixth data line, the fifth data line is connected to the first data line or the second data line via a first switch transistor, and the sixth data line is connected to the third data line or the fourth data line via a second switch transistor.

4. The neural network computation circuit according to claim 1, wherein the current application circuit includes a first current generation circuit that has a first end connected to ground and a second end connected to a seventh data line and an eighth data line, the first current generation circuit outputs generated current to the second end, the seventh data line or the eighth data line is connected to one of the first data line and the second data line via a first switch transistor, and the eighth data line is connected to one of the third data line and the fourth data line via a second switch transistor.

5. The neural network computation circuit according to claim 1, wherein the current application circuit includes: a first current generation circuit that has a first end connected to a seventh data line, a second end connected to an eighth data line, and that outputs generated current to the seventh data line or the eighth data line; and a second current generation circuit that has one end connected to a ninth data line, a second end connected to a tenth data line, and that outputs generated current to the ninth data line or the tenth data line, the seventh data line or the eighth data line is connected to the first data line or the second data line via a first switch transistor, and the ninth data line or the tenth data line is connected to the third data line or the fourth data line via a second switch transistor.

6. The neural network computation circuit according to claim 4, wherein the first current generation circuit is configured as a first resistance element, one end of the first resistance element is connected to the seventh data line, and another end of the first resistance element is connected to the eighth data line.

7. The neural network computation circuit according to claim 4, wherein the first current generation circuit is configured as a load transistor, one end of the load transistor is connected to the seventh data line, another end of the load transistor is connected to the eighth data line, and a gate of the load transistor is connected to a load gate line.

8. The neural network computation circuit according to claim 4, wherein in the first current generation circuit, at least one parallel connection of series connections each of which is a series connection of a first resistance element and a first selection transistor is provided, one end of the first resistance element is connected to the seventh data line, one end of the first selection transistor is connected to the eighth data line, and a gate of the first selection transistor is connected to a selection gate line.

9. The neural network computation circuit according to claim 4, wherein in the first current generation circuit, at least one parallel connection of series connection each of which is a series connection of a load transistor and a selection transistor is provided, one end of the load transistor is connected to the seventh data line, one end of the selection transistor is connected to the eighth data line, a gate of the load transistor is connected to a load gate line, and a gate of the selection transistor is connected to a selection gate line.

10. The neural network computation circuit according to claim 5, wherein the first current generation circuit and the second current generation circuit each are configured as a first resistance element, one end of the first resistance element is connected to the seventh data line or the ninth data line, and another end of the first resistance element is connected to the eighth data line or the tenth data line.

11. The neural network computation circuit according to claim 5, wherein the first current generation circuit and the second current generation circuit each are configured as a load transistor, one end of the load transistor is connected to the seventh data line or the ninth data line, another end of the load transistor is connected to the eighth data line or the tenth data line, and a gate of the load transistor is connected to a load gate line.

12. The neural network computation circuit according to claim 5, wherein in each of the first current generation circuit and the second current generation circuit, at least one parallel connection of series connections each of which is a series connection of a first resistance element and a first selection transistor is provided, one end of the first resistance element is connected to the seventh data line or the ninth data line, one end of the first selection transistor is connected to the eighth data line or the tenth data line, and a gate of the first selection transistor is connected to a selection gate line.

13. The neural network computation circuit according to claim 5, wherein in each of the first current generation circuit and the second current generation circuit, at least one parallel connection of series connections each of which is a series connection of a load transistor and a selection transistor is provided, one end of the load transistor is connected to the seventh data line or the ninth data line, one end of the selection transistor is connected to the eighth data line or the tenth data line, a gate of the load transistor is connected to a load gate line, and a gate of the selection transistor is connected to a selection gate line.

14. The neural network computation circuit according to claim 1, wherein the current application circuit includes at least one current application unit including a series connection of a second resistance element and a third cell transistor, and a series connection of a third resistance element and a fourth cell transistor, the second resistance element having one end connected to the first data line, the third cell transistor having one end connected to the second data line and a gate connected to one of the plurality of word lines, the third resistance element having one end connected to the third data line, the fourth cell transistor having one end connected to the fourth data line and a gate connected to one of the plurality of word lines.

15. The neural network computation circuit according to claim 6, wherein the first resistance element is configured as a fixed resistance element or a third non-volatile semiconductor memory element.

16. The neural network computation circuit according to claim 14, wherein the second resistance element and the third resistance element each are configured as a fixed resistance element or a third non-volatile semiconductor memory element.

17. The neural network computation circuit according to claim 1, wherein in storing the connection weight coefficients in the first non-volatile semiconductor memory element and the second non-volatile semiconductor memory element of each of the plurality of computation units: when a connection weight coefficient is a positive value, the connection weight coefficient is written into the first non-volatile semiconductor memory element so that a current value flowing in the first non-volatile semiconductor memory element is in proportion to a value of the connection weight coefficient; and when a connection weight coefficient is a negative value, the connection weight coefficient is written into the second non-volatile semiconductor memory element so that a current value flowing in the second non-volatile semiconductor memory element is in proportion to a value of the connection weight coefficient.

18. The neural network computation circuit according to claim 1, wherein in storing the connection weight coefficients in the first non-volatile semiconductor memory element and the second non-volatile semiconductor memory element of each of the plurality of computation units: when a connection weight coefficient is a positive value, the connection weight coefficient is written into the first non-volatile semiconductor memory element and the second non-volatile semiconductor memory element so that a current value flowing in the first non-volatile semiconductor memory element is higher than a current value flowing in the second non-volatile semiconductor memory element, and a current difference between the current values is in proportion to a value of the connection weight coefficient; and when a connection weight coefficient is a negative value, the connection weight coefficient is written into the first non-volatile semiconductor memory element and the second non-volatile semiconductor memory element so that a current value flowing in the second non-volatile semiconductor memory element is higher than a current value flowing in the first non-volatile semiconductor memory element, and a current difference between the current values is in proportion to a value of the connection weight coefficient.

19. The neural network computation circuit according to claim 1, wherein the word line selection circuit: places a corresponding word line in the non-selection state when the input data indicate the first logical value; and places a corresponding world line in the selection state when the input data indicate the second logical value.

20. The neural network computation circuit according to claim 1, wherein a current value flows in the first data line or the second data line, the current value corresponding to a result of a multiply-accumulate operation between input data having connection weight coefficients that are positive values and corresponding connection weight coefficients having positive values, and a current value flows in the third data line or the fourth data line, the current value corresponding to a result of a multiply-accumulate operation between input data having connection weight coefficients that are negative values and corresponding connection weight coefficients having negative values.

21. The neural network computation circuit according to claim 1, wherein the determination circuit: outputs the first logical value when a current value flowing in the first data line or the second data line is lower than a current value flowing in the third data line or the fourth data line; and outputs the second logical value when a current value flowing in the first data line or the second data line is higher than a current value flowing in the third data line or the fourth data line.

22. The neural network computation circuit according to claim 1, wherein when the current application circuit is connected to the first data line or the second data line and applies a current to the first data line or the second data line, a sum of (i) a current value corresponding to a result of a multiply-accumulate operation between input data having connection weight coefficients that are positive values and corresponding connection weight coefficients having positive values and (ii) a current value applied by the current application circuit flows in the first data line or the second data line, and when the current application circuit is connected to the third data line or the fourth data line and applies a current to the third data line or the fourth data line, a sum of (i) a current value corresponding to a result of a multiply-accumulate operation between input data having connection weight coefficients that are negative values and corresponding connection weight coefficients having negative values and (ii) a current value applied by the current application circuit flows in the third data line or the fourth data line.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) These and other objects, advantages and features of the disclosure will become apparent from the following description thereof taken in conjunction with the accompanying drawings that illustrate a specific embodiment of the present disclosure.

(2) FIG. 1A is a diagram illustrating a neuron used in a neural network computation.

(3) FIG. 1B is a diagram illustrating a detailed configuration of a circuit that performs a computation of the neuron illustrated in FIG. 1A.

(4) FIG. 2 is a diagram illustrating a configuration of a deep neural network.

(5) FIG. 3 is a diagram illustrating a calculation performed by a neuron in a neural network computation.

(6) FIG. 4 is a diagram illustrating a case in which a computation of bias coefficient b is assigned to input x.sub.0 and connection weight coefficient w.sub.0 in a calculation performed by a neuron in a neural network computation.

(7) FIG. 5 is a diagram illustrating activation function f for a neuron in neural network computation according to an embodiment.

(8) FIG. 6 is a diagram illustrating an entire configuration of a neural network computation circuit including a non-volatile semiconductor memory element according to an embodiment.

(9) FIG. 7A is a circuit diagram of memory cell MC, a non-volatile semiconductor memory element, which is included in the memory cell array illustrated in FIG. 6.

(10) FIG. 7B is a cross-sectional view of memory cell MC.

(11) FIG. 7C is a diagram illustrating applied voltages in each operation mode of memory cell MC.

(12) FIG. 8A is a diagram illustrating a calculation indicating the operating principles of the neural network computation circuit according to an embodiment.

(13) FIG. 8B is a diagram illustrating an operation of computation unit PUi according to an embodiment.

(14) FIG. 9A is a diagram illustrating an operation of computation unit PUi.

(15) FIG. 9B is a diagram illustrating a state of word line WLi in relation to input x.sub.i of computation unit PUi according to an embodiment.

(16) FIG. 9C is a diagram illustrating a current range of variable resistance elements RP and RN of computation unit PUi and a calculation of current values to be written into the variable resistance elements according to an embodiment.

(17) FIG. 9D is a diagram illustrating a multiply-accumulate operation between input x.sub.i and connection weight coefficient w.sub.i performed by computation unit PUi according to an embodiment.

(18) FIG. 10A is a diagram illustrating a configuration of neural network computation according to Embodiment 1.

(19) FIG. 10B is a diagram illustrating values of connection weight coefficients in the neural network computation according to Embodiment 1.

(20) FIG. 11 is a diagram illustrating a detailed configuration of a neural network computation circuit according to Embodiment 1.

(21) FIG. 12A is a diagram illustrating a current range of variable resistance elements of a computation unit and current values to be written into the variable resistance elements according to Embodiment 1.

(22) FIG. 12B is a diagram illustrating a current range of variable resistance elements RP and RN of computation units PU0 to PU3 and current values (resistance values) to be written into variable resistance elements RP and RN.

(23) FIG. 13A is a diagram illustrating a configuration of neural network computation according to Embodiment 2.

(24) FIG. 13B is a truth table of a neural network circuit according to Embodiment 2.

(25) FIG. 13C is a diagram illustrating connection weight coefficients of the neural network circuit according to Embodiment 2.

(26) FIG. 13D is a diagram illustrating computational operations performed by an input layer, a hidden layer, and an output layer of the neural network circuit according to Embodiment 2.

(27) FIG. 14A is a diagram illustrating a current range of variable resistance elements of a computation unit, and current values to be written into the variable resistance elements, according to Embodiment 2.

(28) FIG. 14B is a diagram illustrating a current range of variable resistance elements of a computation unit of a neural network computation circuit according to Embodiment 2, and current values to be written into the variable resistance elements.

(29) FIG. 15A is a diagram illustrating connection weight coefficients of the output layer.

(30) FIG. 15B is a diagram illustrating results of neural network computations performed by the output layer according to Embodiment 2.

(31) FIG. 15C is a diagram illustrating a detailed configuration of the neural network computation circuit for the output layer according to Embodiment 2.

(32) FIG. 16A is a diagram illustrating a configuration example of a current application circuit.

(33) FIG. 16B is a diagram illustrating the second configuration example of the current application circuit.

(34) FIG. 16C is a diagram illustrating the third configuration example of the current application circuit.

(35) FIG. 16D is a diagram illustrating the fourth configuration example of the current application circuit.

(36) FIG. 16E is a diagram illustrating a specific configuration of a current generation circuit in the current application circuit.

(37) FIG. 16F is a diagram illustrating a specific configuration of a current generation circuit in the current application circuit.

(38) FIG. 16G is a diagram illustrating a specific configuration of a current generation circuit in the current application circuit.

(39) FIG. 16H is a diagram illustrating a specific configuration of a current generation circuit in the current application circuit.

(40) FIG. 17 is a diagram illustrating details when a current application circuit is disposed in a memory cell array.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(41) Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

(42) FIG. 1A and FIG. 1B each are a diagram illustrating a detailed configuration of a neural network computation circuit including a non-volatile semiconductor memory element according to an embodiment. FIG. 1A is a diagram illustrating a neuron used in a neural network computation. FIG. 1B is a diagram illustrating a detailed configuration of a circuit that performs a computation of the neuron illustrated in FIG. 1A, and is a representative figure illustrating the features of the present disclosure. FIG. 1A and FIG. 1B will be described in detail later.

(43) [Neural Network Computation]

(44) First, the following describes the basic theory of neural network computation.

(45) FIG. 2 is a diagram illustrating a configuration of a deep neural network. A neural network includes: input layer 1 to which input data are inputted; hidden layer 2 (sometimes referred to as a middle layer) that receives the input data of input layer 1 and performs a computation; and output layer 3 that receives output data of hidden layer 2 and performs a computation. In each of input layer 1, hidden layer 2, and output layer 3, there are many basic elements of the neural network referred to as neurons 10, and each neuron 10 is connected to other neurons 10 via connection weights 11. Connection weights 11, each of which has a different connection weight coefficient, connect the neurons. Neuron 10 receives input data, performs a multiply-accumulate operation between the input data and corresponding connection weight coefficients, and outputs a result of the multiply-accumulate operation as output data. Here, in the sense that hidden layer 2 includes connected columns (four columns in FIG. 2) of neurons, which forms a deep neural network, the neural network illustrated in FIG. 2 is referred to as a deep neural network.

(46) FIG. 3 is a diagram illustrating a calculation performed by a neuron in a neural network computation. The calculation performed by neuron 10 is expressed by equation (1) and equation (2) in FIG. 3. Neuron 10 is connected to n inputs x.sub.1 to x.sub.n via connection weights each having a corresponding one of connection weight coefficients w.sub.1 to w.sub.n, and performs a multiply-accumulate operation between inputs x.sub.1 to x.sub.n and connection weight coefficients w.sub.1 to w.sub.n. Neuron 10 has bias coefficient b and adds bias coefficient b to a result of the multiply-accumulate operation between inputs x.sub.1 to x.sub.n and connection weight coefficients w.sub.1 to w.sub.n. Neuron 10 has activation function f and performs a computation on a result obtained by adding bias coefficient b to the result of the multiply-accumulate operation between inputs x.sub.1 to x.sub.n and connection weight coefficients w.sub.1 to w.sub.n, using activation function f, to output output y.

(47) FIG. 4 is a diagram illustrating a case in which a computation of bias coefficient b is assigned to input x.sub.0 and connection weight coefficient w.sub.0 in a calculation performed by a neuron in a neural network computation. The calculation performed by neuron 10 is expressed by equation (1) and equation (2) in FIG. 4. Neuron 10 performs the multiply-accumulate operation between inputs x.sub.1 to x.sub.n and connection weight coefficients w.sub.1 to w.sub.n and adds bias coefficient b in FIG. 3. However, as illustrated in FIG. 4, by assigning the addition of bias coefficient b to input x.sub.0=1 and connection weight coefficient w.sub.0=b, it is possible to interpret that neuron 10 is connected to n+1 inputs x.sub.0 to x.sub.n via connection weights each having a corresponding one of connection weight coefficients w.sub.0 to w.sub.n. As shown by equation (1) and equation (2) in FIG. 4, the calculation performed by neuron 10 can be concisely expressed by only the sum of products between inputs x.sub.0 to x.sub.n and connection weight coefficients w.sub.0 to w.sub.n. In the present embodiment, as illustrated in FIG. 4, the addition of bias coefficient b is expressed as input x.sub.0=1 and connection weight coefficient w.sub.0=b.

(48) FIG. 5 is a diagram illustrating activation function f for a neuron in neural network computation according to the embodiment. The x axis indicates input u of activation function f, and the y axis indicates output f(u) of activation function f. In the present embodiment, a step function is used as activation function f. Although the step function is used as the activation function in the present embodiment, examples of other activation functions used in the neural network computation include a sigmoid function. As illustrated in FIG. 5, the step function outputs output f(u)=0 when input u is a negative value (<0), and outputs output f(u)=1 when input u is a positive value (≥0). When neuron 10 illustrated in FIG. 4 uses activation function f of the step function, neuron 10 outputs output y=0 when a result of a multiply-accumulate operation between inputs x.sub.0 to x.sub.n and connection weight coefficients w.sub.0 to w.sub.n is a negative value, and outputs output y=1 when the result of the multiply-accumulate operation is a positive value.

(49) [Entire Configuration of Neural Network Computation Circuit Including Non-Volatile Semiconductor Memory Element]

(50) FIG. 6 is a diagram illustrating an entire configuration of a neural network computation circuit including a non-volatile semiconductor memory element according to the embodiment. The neural network computation circuit of the present disclosure includes memory cell array 20, word line selection circuit 30, column gate 40, determination circuit 50, write circuit 60, and control circuit 70.

(51) Memory cell array 20 includes non-volatile semiconductor memory elements arranged in a matrix, and the non-volatile semiconductor memory elements store connection weight coefficients used in neural network computation.

(52) Memory cell array 20 has word lines WL0 to WLn, bit lines BL0 to BLm, and source lines SL0 to SLm.

(53) Word line selection circuit 30 drives word lines WL0 to WLn of memory cell array 20. Word line selection circuit 30 places a word line into a selection state or a non-selection state according to an input from a neuron in the neural network computation (to be described later).

(54) Column gate 40 is connected to bit lines BL0 to BLm and source lines SL0 to SLm, selects a predetermined bit line and a predetermined source line from among the bit lines and the source lines, and connects the predetermined bit line and the predetermined source line to determination circuit 50 and write circuit 60 described later.

(55) Determination circuit 50 is connected to bit lines BL0 to BLm and source lines SL0 to SLm via column gate 40, and detects current values flowing in the bit lines or the source lines to output output data. Determination circuit 50 reads out data stored in a memory cell of memory cell array 20 to output output data of a neuron in the neural network computation (to be described later).

(56) Write circuit 60 is connected to bit lines BL0 to BLm and source lines SL0 to SLm via column gate 40, and applies a rewrite voltage to a non-volatile semiconductor memory element of memory cell array 20.

(57) Control circuit 70 controls operations of memory cell array 20, word line selection circuit 30, column gate 40, determination circuit 50, and write circuit 60, and controls a readout operation, a write operation, and a neural network computational operation performed on a memory cell of memory cell array 20.

(58) [Configuration of Non-Volatile Semiconductor Memory Element]

(59) FIG. 7A to FIG. 7C are a circuit diagram of a non-volatile semiconductor memory element according to the embodiment, a cross-sectional view of the non-volatile semiconductor memory element, and a diagram illustrating applied voltages in each operation of the non-volatile semiconductor memory element, respectively.

(60) FIG. 7A is a circuit diagram of memory cell MC, a non-volatile semiconductor memory element, which is included in memory cell array 20 illustrated in FIG. 6. Memory cell MC is a 1T1R memory cell that is configured of a series connection of variable resistance element RP and cell transistor T0, and includes one cell transistor T0 and one variable resistance element RP. Variable resistance element RP is a non-volatile semiconductor memory element referred to as a resistive random access memory (ReRAM). Memory cell MC has word line WL connected to the gate terminal of cell transistor T0, bit line BL connected to variable resistance element RP, and source line SL connected to the source terminal of cell transistor T0.

(61) FIG. 7B is a cross-sectional view of memory cell MC. Diffusion regions 81a and 81b are disposed on semiconductor substrate 80. Diffusion region 81a serves as the source terminal of cell transistor T0, and diffusion region 81b serves as the drain terminal of the cell transistor. A space between diffusion regions 81a and 81b serves as a channel region of cell transistor T0. Oxide film 82 and gate electrode 83 including polysilicon are disposed above the channel region. These elements serve as cell transistor T0. Diffusion region 81, the source terminal of cell transistor T0, is connected to source line SL that is first interconnect layer 85a via via 84a. Diffusion region 81b, the drain terminal of cell transistor T0, is connected to first interconnect layer 85b via via 84b. Moreover, first interconnect layer 85b is connected second interconnect layer 87 via via 86, and second interconnect layer 87 is connected to variable resistance element RP via via 88. Variable resistance element RP includes lower electrode 89, variable resistance layer 90, and upper electrode 91. Variable resistance element RP is connected to bit line BL that is third interconnect layer 93 via via 92.

(62) FIG. 7C is a diagram illustrating applied voltages in each operation mode of memory cell MC.

(63) A reset operation (high resistance writing) applies a voltage of Vg_reset (e.g. 2 V) to word line WL to place cell transistor T0 into a non-selection state, applies a voltage of Vreset (e.g. 2.0 V) to bit line BL, and applies ground voltage VSS (0 V) to source line SL. With this, variable resistance element RP changes to a high resistance state by a positive voltage being applied to the upper electrode.

(64) A set operation (low resistance writing) applies a voltage of Vg_set (e.g. 2.0 V) to word line WL to place cell transistor T0 into a selection state, applies ground voltage VSS (0 V) to bit line BL, and applies a voltage of Vset (e.g. 2.0 V) to source line SL. With this, variable resistance element RP changes to a low resistance state by a positive voltage being applied to the lower electrode.

(65) A readout operation applies a voltage of Vg_read (e.g. 1.1 V) to word line WL to place cell transistor T0 into the selection state, applies a voltage of Vread (e.g. 0.4 V) to bit line BL, and applies ground voltage VSS (0 V) to source line SL. With this, when variable resistance element RP is in the high resistance state (reset state), a small memory cell current flows in variable resistance element RP, and when variable resistance element RP is in the low resistance state (set state), a large memory cell current flows in variable resistance element RP. Data stored in the memory cell is read out by the determination circuit determining a difference between the current values.

(66) When memory cell MC is used as a semiconductor memory that stores 0 or 1, a resistance value of variable resistance element RP can be in only two resistance states (digital) of a high resistance state (0) and a low resistance state (1). However, when memory cell MC is used as an element in the neural network computation circuit of the present disclosure, a resistance value of variable resistance element RP is set to be a variable (analog) value, and used.

(67) [Detailed Configuration of Neural Network Computation Circuit Including Non-Volatile Semiconductor Memory Element]

(68) FIG. 1A and FIG. 1B each are a diagram illustrating a detailed configuration of a neural network computation circuit including a non-volatile semiconductor memory element according to the embodiment.

(69) FIG. 1A is a diagram illustrating a neuron used in a neural network computation, and is the same as FIG. 4. Neuron 10 receives n+1 inputs x.sub.0 to x.sub.n each having a corresponding one of connection weight coefficients w.sub.0 to w.sub.n. Inputs x.sub.0 to x.sub.n can take a value of 0 or a value of 1, and connection weight coefficients w.sub.0 to w.sub.n can take a variable (analog) value. A computation is performed on a result of a multiply-accumulate operation between inputs x.sub.0 to x.sub.n and connection weight coefficients w.sub.0 to w.sub.n using activation function f, the step function illustrated in FIG. 5, to output output y.

(70) FIG. 1B is a diagram illustrating a detailed configuration of a circuit that performs a computation of neuron 10 illustrated in FIG. 1A. The memory cell array has word lines WL0 to WLn, bit lines BL0 and BL1, and source lines SL0 and SL1.

(71) Word lines WL0 to WLn correspond to inputs x.sub.0 to x.sub.n of neuron 10. Specifically, word line WL0 corresponds to input x.sub.0, word line WL1 corresponds to input x.sub.1, word line WLn−1 corresponds to input x.sub.n-1, and word line WLn corresponds to input x.sub.n. Word line selection circuit 30 places word lines WL0 to WLn into a selection state or a non-selection state according to inputs x.sub.0 to x.sub.n. Word line selection circuit 30 places a word line into the non-selection state when an input is 0, and places a word line into the selection state when an input is 1. Since each of inputs x.sub.0 to x.sub.n can take a value of 0 or a value of 1 in an arbitrary manner in the neural network computation, when two or more inputs among inputs x.sub.0 to x.sub.n have the value of 1, word line selection circuit 30 selects two or more word lines simultaneously.

(72) Connection weight coefficients w.sub.0 to w.sub.n of neuron 10 correspond to computation units PU0 to PUn including memory cells. Specifically, connection weight coefficient w.sub.0 corresponds to computation unit PU0, connection weight coefficient w.sub.1 corresponds to computation unit PU1, connection weight coefficient w.sub.n-1 corresponds to computation unit PUn−1, and connection weight coefficient w.sub.n corresponds to computation unit PUn.

(73) Computation unit PU0 includes a memory cell composed of variable resistance element RP and cell transistor T0, and a memory cell composed of variable resistance element RN and cell transistor T1. In other words, one computation unit includes two memory cells. Computation unit PU0 is connected to word line WL0, bit lines BL0 and BL1, and source lines SL0 and SL1. Word line WL0 is connected to the gate terminals of cell transistors T0 and T1. Bit line BL0 is connected to variable resistance element RP. Source line SL0 is connected to the source terminal of cell transistor T0. Bit line BL1 is connected to variable resistance element RN. Source line SL1 is connected to the source terminal of cell transistor T1. Input x.sub.0 is inputted via word line WL0 of computation unit PU0, and connection weight coefficient w.sub.0 is stored as a resistance value (conductance) in two variable resistance elements RP and RN of computation unit PU0. Since computation units PU1, PUn−1, and PUn have the same configuration as computation unit PU0, the detailed description thereof will be omitted. Each of inputs x.sub.0 to x.sub.n is inputted via a corresponding one of word lines WL0 to WLn connected to computation units PU0 to PUn, and each of connection weight coefficients w.sub.0 to w.sub.n is stored as a resistance value (conductance) in variable resistance elements RP and RN of computation units PU0 to PUn.

(74) Bit line BL0 is connected to determination circuit 50 via column gate transistor YT0, and bit line BL1 is connected to determination circuit 50 via column gate transistor YT1. The gate terminals of column gate transistors YT0 and YT1 are connected to column gate control signal YG. Activation of column gate control signal YG connects bit lines BL0 and BL1 to determination circuit 50. Source line SL0 is connected to ground voltage via discharge transistor DT0, and source line SL1 is connected to ground voltage via discharge transistor DT1. The gate terminals of discharge transistors DT0 and DT1 are connected to discharge control signal DIS. Activation of discharge control signal DIS connects source lines SL0 and SL1 to ground voltage. When a neural network computational operation is performed, the activation of column gate control signal YG and discharge control signal DIS connects bit lines BL0 and BL1 to determination circuit 50, and source lines SL0 and SL1 to ground voltage.

(75) Determination circuit 50 detects and compares current values flowing in bit lines BL0 and BL1 connected to determination circuit 50 via column gate transistors YT0 and YT1, to output output y. Output y can take a value of 0 or a value of 1. Determination circuit 50 outputs output y having the value of 0 when the current value flowing in bit line BL0 is smaller than the current value flowing in bit line BL1, and outputs output y having the value of 1 when the current value flowing in bit line BL0 is larger than the current value flowing in bit line BL1. In other words, determination circuit 50 determines a magnitude relationship between the current values flowing in bit lines BL0 and BL1, to output output y.

(76) Current application circuit 100 applies current to at least one of bit line BL0 or bit line BL1.

(77) As illustrated in FIG. 16A, current application circuit 100 can apply current from current source 110 to bit line BL0 or bit line BL1 by an input of current source 110 being connected to bit line BL0 via switch transistor YTp and an input of current source 110 being connected to bit line BL1 via switch transistor YTn. In addition, an input of current source 110 may be connected to only one of bit line BL0 via switch transistor YTp and bit line BL1 via switch transistor YTn.

(78) FIG. 16B is a diagram illustrating the second configuration example of current application circuit 100. Current application circuit 100 can apply current from current source 110 to bit line BL0 by an input of current source 110 being connected to bit line BL0 via switch transistor YTp, and can apply current from current source 111 to bit line BL1 by an input of current source 111 being connected to bit line BL1 via switch transistor YTn.

(79) FIG. 16C is a diagram illustrating the third configuration example of current application circuit 100. Current application circuit 100 can apply current from current generation circuit 120 to bit line BL0 or bit line BL1 by one end of current generation circuit 120 being connected to bit line BL0 via switch transistor YTp and connected to bit line BL1 via switch transistor YTn, and the other end of current generation circuit 120 being connected to ground voltage by activating discharge control signal DIS. In addition, the one end of current generation circuit 120 may be connected to only one of bit line BL0 via switch transistor YTp and bit line BL1 via switch transistor YTn.

(80) FIG. 16D is a diagram illustrating the fourth configuration example of current application circuit 100. Current application circuit 100 can apply current from current generation circuit 120 to bit line BL0 and current from current generation circuit 121 to bit line BL1 by one end of current generation circuit 120 being connected to bit line BL0 via switch transistor YTp, one end of current generation circuit 121 being connected to bit line BL1 via switch transistor YTn, and the other ends of current generation circuits 120 and 121 being connected to ground voltage by activating discharge control signal DIS.

(81) FIG. 16E, FIG. 16F, FIG. 16G, and FIG. 16H each are a diagram illustrating a specific configuration of current generation circuit 120 in current application circuit 100. As illustrated in FIG. 16E, current generation circuit 120 is configured as resistance element Rw. Resistance element Rw may be configured as a fixed resistance element or a nonvolatile memory element. As illustrated in FIG. 16, current generation circuit 120 is configured as load transistor WT. The gate of load transistor WT is controlled using load gate voltage WLw. As illustrated in FIG. 16G, in current generation circuit 120, at least one parallel connection of series connections of resistance elements Rw0 to Rw2 and selection transistors ST0 to ST2 is provided. As illustrated in FIG. 16H, in current generation circuit 120, at least one parallel connection of series connections of load transistors WT0 to WT2 and selection transistors ST0 to ST2 is provided. The gates of load transistors WT0 to WT2 are controlled using load gate voltages WLw0 to WLw2.

(82) FIG. 17 is a diagram illustrating the fifth configuration example of current application circuit 100. As illustrated in FIG. 17, current application circuit 100 may be disposed in a memory cell array. Currents to be added correspond to current application units PUαp and PUαn including memory cells. Connection weight coefficient wαp to be added corresponds to current application unit PUαp, and connection weight coefficient wan to be added corresponds to current application unit PUαn.

(83) Current application units PUαp and PUαn each include a memory cell composed of variable resistance element RP and cell transistor T0, and a memory cell composed of variable resistance element RN and cell transistor T1. In other words, one current application unit includes two memory cells. Current application unit PUαp is connected to word line WLαp, bit lines BL0 and BL1, and source lines SL0 and SL1. Word line WLαp is connected to the gate terminals of cell transistors T0 and T1. Bit line BL0 is connected to variable resistance element RP. Source line SL0 is connected to the source terminal of cell transistor T0. Bit line BL1 is connected to variable resistance element RN. Source line SL1 is connected to the source terminal of cell transistor T1. Since current application unit PUαn has the same configuration as current application unit PUαp, the detailed description thereof will be omitted. In other words, any current value can be applied to bit lines BL0 and BL1 by setting to variable resistance element RP a resistance value equivalent to a current to be applied to BL0, setting to variable resistance element RN a resistance value equivalent to a current to be applied to BL1, and selecting corresponding word lines WLαp and WLαn. Here, each of the variable resistance elements may be configured as a fixed resistance element or a load transistor. In addition, one or more current application units PUαp and PUαn may be provided.

(84) The following describes in detail the operating principles of and the operating method for the neural network computation circuit including the non-volatile semiconductor memory element thus configured, and a method of storing a connection weight coefficient in a variable resistance element.

(85) [Operating Principles of Neural Network Computation Circuit Including Non-Volatile Semiconductor Memory Element]

(86) FIG. 8A and FIG. 8B are a diagram illustrating a calculation indicating the operating principles of the neural network computation circuit according to the embodiment, and a diagram illustrating an operation of a computation unit, respectively.

(87) FIG. 8A is a diagram illustrating a calculation indicating the operating principles of the neural network computation circuit according to the embodiment. As shown by equation (1) in FIG. 8A, neuron 10 performs a computation on a result of a multiply-accumulate operation between input x.sub.i and connection weight coefficient w.sub.i, using activation function f that is a step function. As shown by equation (2) in FIG. 8A, the present disclosure is characterized by replacing connection weight coefficient w.sub.i with current value I.sub.i flowing in a variable resistance element (memory cell) and performing a multiply-accumulate operation between input x.sub.i and current value I.sub.i flowing in the variable resistance element (memory cell).

(88) Here, connection weight coefficient w.sub.i takes both a positive value (≥0) and a negative value (<0) in a neural network computation. When a product between input x.sub.i and connection weight coefficient w.sub.i in the multiply-accumulate operation is a positive value, addition is performed. When a product between input x.sub.i and connection weight coefficient w.sub.i in the multiply-accumulate operation is a negative value, subtraction is performed. However, since current value I.sub.i flowing in the variable resistance element (memory cell) can take only a positive value, while addition when a product between input x.sub.i and connection weight coefficient w.sub.i is a positive value can be performed by addition of current value I.sub.i, there is a need to figure out how subtraction when a product between input x.sub.i and connection weight coefficient w.sub.i is a negative value is performed using current value I.sub.i that is a positive value.

(89) FIG. 8B is a diagram illustrating an operation of computation unit PUi according to the embodiment. The configuration of computation unit PUi is as illustrated in FIG. 1A and FIG. 1B, and thus the detailed description thereof will be omitted. The present disclosure is characterized by storing connection weight coefficient w.sub.i in two variable resistance elements RP and RN. A resistance value set to variable resistance element RP, a resistance value set to variable resistance element RN, a voltage applied to bit lines BL0 and BL1, and current values flowing in variable resistance elements RP and RN are denoted by Rpi, Rni, Vbl, and Ipi and Ini, respectively. The present disclosure is also characterized by adding a positive result of a multiply-accumulate operation to a current flowing in bit line BL0, and adding a negative result of a multiply-accumulate operation to a current flowing in bit line BL1. Resistance values Rpi and Rni (current values Ipi and Ini) of variable resistance elements RP and RN are set so that the currents flow as described above. Connecting as many computation units PUi as inputs x.sub.0 to x.sub.n (connection weight coefficients w.sub.0 to w.sub.n) to bit lines BL0 and BL1 in parallel as illustrated in FIG. 1B makes it possible to provide a positive result of a multiply-accumulate operation in neuron 10 as a current value flowing in bit line BL0, and a negative result of a multiply-accumulate operation in neuron 10 as a current value flowing in bit line BL1. Calculations for the above-described operation are represented by equation (3), equation (4), and equation (5) in FIG. 8A. In other words, properly writing resistance values Rpi and Rni, equivalent to connection weight coefficient w.sub.i, into variable resistance elements RP and RN of computation unit PUi makes it possible to provide the current value of bit line BL0 corresponding to the positive result of the multiply-accumulate operation, and the current value of bit line BL1 corresponding to the negative result of the multiply-accumulate operation.

(90) Current values flowing in bit lines BL0 and BL1 are detected and determined so that since activation function f is a step function (0 is outputted when an input is a negative value (<0), 1 is outputted when an input is a positive value (≥0)) in equation (5) in FIG. 8A, when the current value flowing in bit line BL0, which is a positive result of a multiply-accumulate operation, is smaller than the current value flowing in bit line BL1, which is a negative result of a multiply-accumulate operation, that is, all results of multiply-accumulate operations are negative values, 0 is outputted, and when the current value flowing in bit line BL0, which is a positive result of a multiply-accumulate operation, is larger than the current value flowing in bit line BL1, which is a negative result of a multiply-accumulate operation, that is, all results of multiply-accumulate operations are positive values, 1 is outputted. This enables the neural network computation in neuron 10 using computation unit PUi including variable resistance elements RP and RN.

(91) FIG. 9A to FIG. 9D each are a diagram illustrating a detailed operation of a computation unit according to the embodiment. FIG. 9A is a diagram illustrating an operation of computation unit PUi. Since FIG. 9A is the same as FIG. 8B, the detailed description thereof will be omitted. The following describes a multiply-accumulate operation between input x.sub.1 and connection weight coefficient w.sub.i in computation unit PUi.

(92) FIG. 9B is a diagram illustrating a state of word line WLi in response to input x.sub.i of computation unit PUi according to the embodiment. Input x.sub.i takes a value of 0 or a value of 1. When input x.sub.i is 0, word line WLi is placed in a non-selection state. When input x.sub.i is 1, word line WLi is placed in a selection state. Word line WLi is connected to the gate terminals of cell transistors T0 and T1. When word line WLi is in the non-selection state, cell transistors T0 and T1 are in an inactive state (cut-off state), and current does not flow in bit lines BL0 and BL1 regardless of resistance values Rpi and Rni of variable resistance elements RP and RN. In contrast, when word line WLi is in the selection state, cell transistors T0 and T1 are in an activation state (connection state), and current flows in bit lines BL0 and BL1 based on resistance values Rpi and Rni of variable resistance elements RN and RN.

(93) FIG. 9C is a diagram illustrating a current range of variable resistance elements RP and RN of computation unit PUi, and a calculation of current values to be written into the variable resistance elements, according to the embodiment. A possible range of current values flowing in variable resistance elements RP and RN is assumed to be from minimum value I.sub.min to maximum value I.sub.max. Absolute value |w.sub.i| of a connection weight coefficient inputted to a neuron is normalized to be in a range from 0 to 1. A current value to be written into a variable resistance element is determined so that the current value is a current value (analog value) in proportion to connection weight coefficient |w.sub.i| after normalization.

(94) When connection weight coefficient w.sub.i is a positive value (≥0), in order to add a result of a multiply-accumulate operation (≥0) between input x.sub.i (0 or 1) and connection weight coefficient w.sub.i (≥0) as a current value to bit line BL0 in which a current of a positive result of the multiply-accumulate operation flows, resistance value Rpi that causes current value I.sub.min+(I.sub.max−I.sub.min)×|w.sub.i| in proportion to absolute value |w.sub.i| of the connection weight coefficient to flow is written into variable resistance element RP connected to bit line BL0, and resistance value Rni that causes current value I.sub.min (equivalent to connection weight coefficient of 0) to flow is written into variable resistance element RN connected to bit line BL1.

(95) In contrast, when connection weight coefficient w.sub.i is a negative value (<0), in order to add a result of a multiply-accumulate operation (<0) between input x.sub.i (0 or 1) and connection weight coefficient w.sub.i (<0) as a current value to bit line BL1 in which a current of a negative result of the multiply-accumulate operation flows, resistance value Rni that causes current value I.sub.min+(I.sub.max−I.sub.min)×|w.sub.i| in proportion to absolute value |w.sub.i| of the connection weight coefficient to flow is written into variable resistance element RN connected to bit line BL1, and resistance value Rpi that causes current value I.sub.min (equivalent to a connection weight coefficient of 0) to flow is written into variable resistance element RP connected to bit line BL0.

(96) By setting the resistance values (current values) to be written into variable resistance elements RP and RN as above, differential current (I.sub.max−I.sub.min)×|w.sub.i| between the current (equivalent to the positive result of the multiply-accumulate operation) flowing in bit line BL0 and the current (equivalent to the negative result of the multiply-accumulate operation) flowing in bit line BL1 is obtained as a current value equivalent to a result of a multiply-accumulate operation between an input and a connection weight coefficient. A method of normalizing absolute value |w.sub.i| of a connection weight coefficient to be in a range from 0 to 1 will be described in detail later.

(97) FIG. 9D is a diagram illustrating a multiply-accumulate operation between input x.sub.i and connection weight coefficient w.sub.i performed by computation unit PUi according to the embodiment.

(98) When input x.sub.i is 0, result of multiply-accumulate operation x.sub.i×x.sub.i is 0 regardless of a value of connection weight coefficient w.sub.i. Since input x.sub.i is 0, word line WLi is placed in the non-selection state, and cell transistors T0 and T1 are placed in the inactive state (cut-off state). As a result, current values Ipi and Ini flowing in bit lines BL0 and BL1 are 0. In other words, since result of multiply-accumulate operation x.sub.i×x.sub.i is 0, no current flows both in bit line BL0 in which a current equivalent to a positive result of a multiply-accumulate operation flows, and in bit line BL1 in which a current equivalent to a negative result of a multiply-accumulate operation flows.

(99) When input x.sub.i is 1 and connection weight coefficient w.sub.i is a positive value (≥0), result of multiply-accumulate operation x.sub.i×x.sub.i is a positive value (≥0). Since input x.sub.1 is 1, word line WLi is placed in the selection state, and cell transistors T0 and T1 are placed in the activation state (connection state). As a result, currents Ipi and Ini illustrated in FIG. 9C flow in bit lines BL0 and BL1 based on resistance values of variable resistance elements RP and RN. Large amount of differential current (I.sub.max−I.sub.min)×|w.sub.i| between current Ipi equivalent to the positive result of the multiply-accumulate operation flowing in bit line BL0 and current Ini equivalent to the negative result of the multiply-accumulate operation flowing in bit line BL1 flows as a current equivalent to result of multiply-accumulate operation x.sub.1×x.sub.i (≥0) between input x.sub.1 and connection weight coefficient w.sub.i, in bit line BL0, compared to bit line BL1.

(100) When input x.sub.1 is 1 and connection weight coefficient w.sub.i is a negative value (<0), result of multiply-accumulate operation x.sub.1×x.sub.1 is a negative value (<0). Since input x.sub.1 is 1, word line WLi is placed in the selection state, and cell transistors T0 and T1 are placed in the activation state (connection state). As a result, currents Ipi and Ini illustrated in FIG. 9C flow in bit lines BL0 and BL1 based on resistance values of variable resistance elements RP and RN. Large amount of differential current (I.sub.max−I.sub.min)×|w.sub.i| between current Ipi equivalent to the positive result of the multiply-accumulate operation flowing in bit line BL0 and current Ini equivalent to the negative result of the multiply-accumulate operation flowing in bit line BL1 flows as a current equivalent to result of multiply-accumulate operation x.sub.i×x.sub.i (≤0) between input x.sub.i and connection weight coefficient w.sub.i, in bit line BL1, compared to bit line BL0.

(101) As above, the current equivalent to the result of the multiply-accumulate operation between input x.sub.i and connection weight coefficient w.sub.i flows in bit lines BL0 and BL1, the large amount of the current flows in bit line BL0 in the case of the positive result of the multiply-accumulate operation, compared to bit line BL1, and the large amount of the current flows in bit line BL1 in the case of the negative result of the multiply-accumulate operation, compared to bit line BL0. Connecting as many computation units PUi as inputs x.sub.0 to x.sub.n (connection weight coefficients w.sub.0 to w.sub.n) to bit lines BL0 and BL1 in parallel makes it possible to provide a result of a multiply-accumulate operation in neuron 10 as a differential current between a current flowing in bit line BL0 and a current flowing in bit line BL1.

(102) Here, a determination circuit connected to bit lines BL0 and BL1 is caused to output output data of 0 when a current value flowing in bit line BL0 is smaller than a current value flowing in bit line BL1, that is, a result of a multiply-accumulate operation is a negative value, and to output output data of 1 when a current value flowing in bit line BL0 is larger than a current value flowing in bit line BL1, that is, when a result of a multiply-accumulate operation is a positive value. This is equivalent to the determination circuit performing a computation using an activation function of a step function, and enables a neural network computation that performs the multiply-accumulate operation and the computation using the activation function.

(103) [Neural Network Computation Circuit Including Non-Volatile Semiconductor Memory Element According to Embodiment 1]

(104) The operating principles of the neural network computation circuit including the non-volatile semiconductor memory element according to the present disclosure have been described above. Hereinafter, specific embodiments will be described.

(105) FIG. 10A is a diagram illustrating a configuration of neural network computation according to Embodiment 1. FIG. 10B is a diagram illustrating values of connection weight coefficients in the neural network computation according to Embodiment 1. As illustrated in FIG. 10A, neuron 10 has four inputs x.sub.0 to x.sub.3 and corresponding connection weight coefficients w.sub.0 to w.sub.3. A computation performed by neuron 10 is represented by equation (1) in FIG. 10A. Activation function f of neuron 10 is a step function.

(106) As illustrated in FIG. 10B, the connection weight coefficients of neuron 10 are w.sub.0=+0.6, w.sub.1=−0.9, w.sub.2=−1.2, and w.sub.3=+1.5. The following describes a neural network computation circuit including a non-volatile semiconductor memory element that performs a computational operation of neuron 10 illustrated in FIG. 10A and FIG. 10B.

(107) FIG. 11 is a diagram illustrating a detailed configuration of a neural network computation circuit according to Embodiment 1. In FIG. 11, the same elements as in FIG. 1B are assigned the same reference numerals and numbers, and the detailed description thereof will be omitted. The neural network computation circuit according to Embodiment 1 is a neuron having four inputs and one output, and includes: four computation units PU0 to PU3 that store connection weight coefficients w.sub.0 to w.sub.3; four word lines WL0 to WL3 corresponding to inputs x.sub.0 to x.sub.3; bit line BL0 and source line SL0 to which variable resistance elements RP and cell transistors T0 are connected; and bit line BL1 and source line SL1 to which variable resistance elements RN and cell transistors T1 are connected.

(108) When a neural network computational operation is performed, each of word lines WL0 to WL3 and cell transistors T0 and T1 of computation units PU0 to PU3 are placed in a selection state or a non-selection state according to inputs x.sub.0 to x.sub.3. Bit lines BL0 and BL1 are supplied with bit line voltage via column gates YT0 and YT1 by determination circuit 50, and source lines SL0 and SL1 are connected to ground voltage via discharge transistors DT0 and DT1. For this reason, a current equivalent to a positive result of a multiply-accumulate operation flows in bit line BL0, and a current equivalent to a negative result of a multiply-accumulate operation flows in bit line BL1. Determination circuit 50 detects and determines a magnitude relationship between the currents flowing in bit lines BL0 and BL1, to output output y. In other words, determination circuit 50 outputs 0 when a result of a multiply-accumulate operation in neuron 10 is a negative value (<0), and outputs 1 when a result of a multiply-accumulate operation in neuron 10 is a positive value (≥0). Determination circuit 50 outputs a result of the computation using activation function f (step function), using the result of the multiply-accumulate operation as an input.

(109) FIG. 12A and FIG. 12B each are a diagram illustrating a current range of variable resistance elements RP and RN of computation units PU0 to PU3 and current values (resistance values) to be written into variable resistance elements RP and RN according to Embodiment 1. As illustrated in FIG. 12A, a possible range of current values flowing in variable resistance elements RP and RN is from 0 μA to 50 μA in Embodiment 1. Stated differently, a current value has minimum value I.sub.min of 0 μA and maximum value I.sub.max of 50 μA, and a 50-μA current range (dynamic range) is used.

(110) As illustrated in FIG. 12B, first, connection weight coefficients w.sub.0 to w.sub.3 are normalized to be in a range from 0 to 1. In the present embodiment, among connection weight coefficients w.sub.0 to w.sub.3, w.sub.3=+1.5 has the largest absolute value, and the normalized value of this connection weight coefficient is w.sub.3=+1.0. The normalized values of the remaining connection weight coefficients are w.sub.0=+0.4, w.sub.1=−0.6, and w.sub.2=−0.8.

(111) Next, as illustrated in FIG. 12A, current values to be written into variable resistance elements RP and RN of computation units PU0 to PU3 are determined using the normalized connection weight coefficients. FIG. 12B shows a result of calculations of the current values to be written into variable resistance elements RP and RN. Since the normalized value of connection weight coefficient w.sub.0 is +0.4, a positive value, the current value to be written into variable resistance element RP is 20 μA, and the current value to be written into variable resistance element RN is 0 μA. Since the normalized value of connection weight coefficient w.sub.1 is −0.6, a negative value, the current value to be written into variable resistance element RP is 0 μA, and the current value to be written into variable resistance element RN is 30 μA. Since the normalized value of connection weight coefficient w.sub.2 is −0.8, a negative value, the current value to be written into variable resistance element RP is 0 μA, and the current value to be written into variable resistance element RN is 40 μA. Since the normalized value of connection weight coefficient w.sub.3 is +1.0, a positive value, the current value to be written into variable resistance element RP is 50 μA, and the current value to be written into variable resistance element RN is 0 μA. In this manner, writing the current values (resistance values) into variable resistance elements RP and RN of computation units PU0 to PU3 makes it possible to perform the neural network computation.

(112) In Embodiment 1, the following further describes a method of performing a neural network computation for which a connection weight coefficient is adjusted using a current application circuit without rewriting variable resistance elements RP and RN.

(113) For example, in order to perform a neural network computation when connection weight coefficient w.sub.0 is +0.9, connection weight coefficient α is added to connection weight coefficient w.sub.0 as illustrated in FIG. 10A. As illustrated in FIG. 10B, connection weight coefficient w.sub.0 is +0.6, and connection weight coefficient α is +0.3. The computation performed then by neuron 10 is expressed by equation (2) in FIG. 10A.

(114) Next, as illustrated in FIG. 12A, an applied current value of the current application circuit is determined using a normalized connection weight coefficient in the same manner as variable resistance elements RP and RN. FIG. 12B shows a result of a calculation of the applied current value of the current application circuit. When input x.sub.0 is inputted and world line WL0 is in the selection state, the normalized value of connection weight coefficient α is +0.2, a positive value, the current application circuit applies a current value of 10 μA to BL0.

(115) In this manner, it is possible to perform the neural network computation for which the connection weight coefficient is adjusted using the current application circuit without rewriting variable resistance elements RP and RN.

(116) [Neural Network Computation Circuit Including Non-volatile Semiconductor Memory Element According to Embodiment 2]

(117) FIG. 13A to FIG. 13D are a diagram illustrating a configuration of a neural network circuit according to Embodiment 2, a diagram illustrating a truth table of the neural network circuit, a diagram illustrating values of connection weight coefficients of the neural network circuit, and a diagram illustrating computational operations performed by an input layer, a hidden layer, and an output layer of the neural network circuit.

(118) FIG. 13A is a diagram illustrating a detailed configuration of a neural network computation circuit according to Embodiment 2. The neural network circuit according to Embodiment 2 is a multilayer neural network circuit including input layer 1, hidden layer 2, and output layer 3.

(119) Input layer 1 has three inputs x.sub.0 to x.sub.2. Input x.sub.0 is always an input of 1. As illustrated in FIG. 4, hidden layer 2 computes a bias coefficient using input x.sub.0 and the corresponding connection weight coefficient. Two inputs x.sub.1 and x.sub.2 are inputted from the outside.

(120) Hidden layer 2 has one input y.sub.0 and three neurons y.sub.1 to y.sub.3. Input y.sub.0 is always an input of 1. As illustrated in FIG. 4, output layer 3 computes a bias coefficient using input y.sub.0 and the corresponding connection weight coefficient. Three neurons y.sub.1 to y.sub.3 each receive three inputs x.sub.0 to x.sub.2 and the corresponding connection weight coefficients from input layer 1, and output outputs y.sub.1 to y.sub.3.

(121) Output layer 3 has two neurons z.sub.1 and z.sub.2. Neurons z.sub.1 and z.sub.2 each receive four inputs y.sub.0 to y.sub.3 and the corresponding connection weight coefficients from hidden layer 2, and output outputs z.sub.1 and z.sub.2.

(122) Neural network computations performed by neurons y.sub.1 to y.sub.3, z.sub.1, and z.sub.2 are expressed by equation (1) and equation (2) in FIG. 13A. Here, connection weight coefficient w.sub.ik_y is used in calculations performed by neurons y.sub.1 to y.sub.3 of hidden layer 2, connection weight coefficient w.sub.ik_z is used in calculations performed by output layer 3, and activation function f is a step function.

(123) FIG. 13B is a diagram illustrating a truth table of the neural network circuit according to Embodiment 2. Two inputs x.sub.1 and x.sub.2 and output z.sub.1 and z.sub.2 take a value of 0 or a value of 1. Output z.sub.1 is 1 only when both inputs x.sub.1 and x.sub.2 are 1, and is 0 in the other cases. In addition, output z.sub.2 is 0 only when both inputs x.sub.1 and x.sub.2 are 1, and is 1 in the other cases. In other words, the neural network circuit according to Embodiment 2 outputs output z.sub.1 resulting from an AND operation between inputs x.sub.1 and x.sub.2, and outputs output z.sub.2 resulting from a NAND operation between inputs x.sub.1 and x.sub.2.

(124) FIG. 13C is a diagram illustrating connection weight coefficients of the neural network computation circuit according to Embodiment 2. Neurons y.sub.1 to y.sub.3 of hidden layer 2 each have three connection weight coefficients respectively corresponding to three inputs x.sub.0 to x.sub.2. Neurons z.sub.1 and z.sub.2 of output layer 3 each have four connection weight coefficients respectively corresponding to four inputs y.sub.0 to y.sub.3.

(125) FIG. 13D is a diagram illustrating computational operations performed by an input layer, a hidden layer, and an output layer of the neural network circuit according to Embodiment 2. There are four combinations of inputs of input layer 1. FIG. 13D shows: results of multiply-accumulate operations performed by neurons y.sub.1 to y.sub.3 that have received inputs x.sub.0 to x.sub.2 from input layer 1, and an output result of an activation function (step function) using the results of the multiply-accumulate operations as inputs, in hidden layer 2; and results of multiply-accumulate operations performed by neurons z.sub.1 and z.sub.2 that have received inputs y.sub.0 to y.sub.3 from hidden layer 2, and an output result of the activation function (step function) using the results of multiply-accumulate operations as inputs, in output layer 3. As shown by the truth table of FIG. 13B, output z.sub.1 resulting from an AND operation between inputs x.sub.1 and x.sub.2 is outputted, and output z.sub.2 resulting from a NAND operation between inputs x.sub.1 and x.sub.2 is outputted.

(126) FIG. 14A and FIG. 14B each are a diagram illustrating a current range of variable resistance elements of a computation unit of the neural network computation circuit according to Embodiment 2, and current values to be written into the variable resistance elements. As illustrated in FIG. 14A, just like Embodiment 1, a possible range of current values flowing in variable resistance elements RP and RN is from 0 μA to 50 μA in Embodiment 2. Stated differently, a current value has minimum value I.sub.min of 0 μA and maximum value I.sub.max of 50 μA, and a 50-μA current range (dynamic range) is used.

(127) FIG. 14B is a diagram illustrating current values for writing, into variable resistance elements of computation units, connection weight coefficients used in neural network computations performed by neurons y.sub.1 to y.sub.3 of hidden layer 2 and neurons z.sub.1 and z.sub.2 of output layer 3. First, connection weight coefficients normalized to be in a range from 0 to 1 are calculated, and current values to be written into variable resistance elements RP and RN are determined based on the normalized connection weight coefficients. Connection weight coefficients are normalized for each neuron.

(128) The following describes a method of calculating current values for writing, into variable resistance elements RP and RN, connection weight coefficients w.sub.10_y=+0.8, w.sub.11_y=−0.6, and w.sub.12_y=−0.4 of neuron y.sub.1 of hidden layer 2. The three connection weight coefficients are written as resistance values (current values) into variable resistance elements RP and RN of each of three computation units. In normalizing connection weight coefficients, among connection weight coefficients w.sub.10_y, w.sub.11_y, and w.sub.12_y, w.sub.10_y=+0.8 has the largest absolute value, and the normalized value of this connection weight coefficient is w.sub.10_y=+1.0. The normalized values of the remaining connection weight coefficients are w.sub.11_y=−0.75 and w.sub.12_y=−0.5.

(129) Next, as illustrated in FIG. 14A, current values to be written into variable resistance elements RP and RN of the computation unit are determined using the normalized connection weight coefficients. FIG. 14B shows a result of calculations of the current values to be written into variable resistance elements RP and RN. Since the normalized value of connection weight coefficient w.sub.10_y is +1.0, a positive value, the current value to be written into variable resistance element RP is 50 μA, and the current value to be written into variable resistance element RN is 0 μA. Since the normalized value of connection weight coefficient w.sub.11_y is −0.75, a negative value, the current value to be written into variable resistance element RP is 0 μA, and the current value to be written into variable resistance element RN is 37.5 μA. Since the normalized value of connection weight coefficient w.sub.12_y is −0.5, a negative value, the current value to be written into variable resistance element RP is 0 μA, and the current value to be written into variable resistance element RN is 25 μA. Similarly, FIG. 14B shows a result of calculations of current values to be written into variable resistance elements RP and RN of the computation units relative to neurons y.sub.2 and y.sub.3 of hidden layer 2 and neuron z.sub.1 of output layer 3.

(130) A computational operation of the neural network circuit determines output data of hidden layer 2 by writing the current values (resistance values) illustrated in FIG. 14B into variable resistance elements RP and RN of computation units disposed in a memory cell array, using input data of input layer 1 as inputs, selecting the computation units in which connection weight coefficients necessary for computations in hidden layer 2 are stored, and detecting and determining currents flowing in bit lines. Next, the computational operation determines output data of output layer 3 by using output data of hidden layer 2 as inputs, selecting the computation units in which connection weight coefficients necessary for computations in output layer 3 are stored, and detecting and determining current flowing in the bit lines. The neural network circuit can perform a multilayer neural network computation by being caused to operate in the above manner.

(131) FIG. 15A to FIG. 15C illustrate a method of canceling an error in writing a connection weight coefficient, using the current application circuit in the neural network circuit according to Embodiment 2. FIG. 15A is a diagram illustrating connection weight coefficients of an output layer. For connection weight coefficient w.sub.20_z, an ideal value is −0.2, and a result of writing is +0.1. For connection weight coefficient w.sub.22_z, an ideal value is −0.3, and a result of writing is −0.8.

(132) FIG. 15C is a diagram illustrating a detailed configuration of a neural network computation circuit for the output layer according to Embodiment 2. In FIG. 15C, the same elements as in FIG. 1B are assigned the same reference numerals and numbers, and the detailed description thereof will be omitted. The neural network computation circuit for the output layer according to Embodiment 2 is a neuron having four inputs and two outputs, and includes: four computation units PU10 to PU13 that store connection weight coefficients w.sub.10_z to w.sub.13_z; four computation units PU20 to PU23 that store connection weight coefficients w.sub.20_z to w.sub.23_z; four word lines WL0 to WL3 corresponding to inputs y.sub.0 to y.sub.3; bit line BL0 and source line SL0 to which variable resistance element RP and cell transistor T0 are connected; bit line BL1 and source line SL1 to which variable resistance element RN and cell transistor T1 are connected; bit line BL2 and source line SL2 to which variable resistance element RP and cell transistor T2 are connected; and bit line BL3 and source line SL3 to which variable resistance element RN and cell transistor T3 are connected. In addition, current application circuit 100 is connected to bit line BL0 and bit line BL1, and current application circuit 100 is also connected to bit line BL2 and bit line BL3.

(133) When a neural network computational operation is performed, each of word lines WL0 to WL3 and cell transistors T0 to T3 of computation units PU10 to PU13 and PU20 to PU23 are placed in a selection state or a non-selection state according to inputs x.sub.0 to x.sub.3. Bit lines BL0 to BL3 are supplied with bit line voltage via column gates YT0 to YT3 by determination circuit 50, and source lines SL0 to SL3 are connected to ground voltage via discharge transistors DT0 to DT3. For this reason, a current equivalent to a positive result of a multiply-accumulate operation corresponding to output z.sub.0 flows in bit line BL0, and a current equivalent to a negative result of a multiply-accumulate operation corresponding to output z.sub.0 flows in bit line BL1. Moreover, a current equivalent to a positive result of a multiply-accumulate operation corresponding to output z.sub.1 flows in bit line BL2, and a current equivalent to a negative result of a multiply-accumulate operation corresponding to output z.sub.1 flows in bit line BL3. Determination circuit 50 detects and determines a magnitude relationship between the currents flowing in bit lines BL0 and BL1, to output output z.sub.0. In addition, determination circuit 50 detects and determines a magnitude relationship between the currents flowing in bit lines BL2 and BL3, to output output z.sub.1. Stated differently, determination circuit 50 outputs 0 when the result of the multiply-accumulate operation is a negative value (<0), and outputs 1 when the result of the multiply-accumulate operation is a positive value (≥0). Determination circuit 50 outputs a result of the computation using activation function f (step function) using the result of the multiply-accumulate operation as an input. However, as with the neural network computation according to Embodiment 2 of the present disclosure, in a neural network computation in which one of two outputs z.sub.0 and z.sub.1 indicating 1 is outputted, there is a case in which both outputs indicating 1 are outputted or a case in which both outputs indicating 0 are outputted, due to an error in writing a connection weight coefficient or an error of the determination circuit, etc. When both outputs are 1, it is possible to change, from 1 to 0, the outputs of the determination circuit with a small difference between currents applied to the determination circuit, by current application circuit 100 applying a current to each of bit lines BL1 and BL3. When both outputs are 0, it is possible to change, from 0 to 1, the outputs of the determination circuit with a small difference between currents applied to the determination circuit, by current application circuit 100 applying a current to each of bit lines BL0 and BL2.

(134) FIG. 15B is a diagram illustrating results of neural network computations performed by the output layer according to Embodiment 2. In a neural network computation using ideal values, output z.sub.1 resulting from an AND operation between inputs x.sub.1 and x.sub.2 is outputted, and output z.sub.2 resulting from a NAND operation between inputs x.sub.1 and x.sub.2 is outputted. However, when there are errors in results of writing connection weight coefficients as illustrated in FIG. 15A, there is a case in which both outputs z.sub.1 and z.sub.2 indicating 1 are outputted or a case in which both outputs z.sub.1 and z.sub.2 indicating 0 are outputted. It is possible to configure a neural network computation circuit that, even when there are errors in results of writing connection weight coefficients, outputs output z.sub.1 resulting from an AND operation between inputs x.sub.1 and x.sub.2, and output z.sub.2 resulting from a NAND operation between inputs x.sub.1 and x.sub.2, by applying to bit lines BL1 and BL3 a current equivalent to −0.5 as connection weight coefficient α when both outputs z.sub.1 and z.sub.2 indicating 1 are outputted, and applying to bit lines BL0 and BL2 a current equivalent to +0.5 as connection weight coefficient α when both outputs z.sub.1 and z.sub.2 indicating 0 are outputted.

(135) [Conclusion]

(136) As described above, the neural network computation circuit including the non-volatile semiconductor memory element of the present disclosure performs a multiply-accumulate operation using current values flowing in the non-volatile semiconductor memory element. With this, the neural network computation circuit can perform a multiply-accumulate operation without including a large-capacity memory circuit, a large-capacity register circuit, a large-scale multiplication circuit, a large-scale cumulative circuit (accumulator circuit), and a complex control circuitry that are configured as conventional digital circuits. Accordingly, it is possible to reduce the power consumption of the neural network computation circuit, and decrease the chip area of a semiconductor integrated circuit. Moreover, since the neural network circuit includes neurons with input data and output data that are digital data of 0 or 1, it is possible to digitally transmit information between neurons, it is easy to mount a large-scale neural network circuit including neurons, and it is possible to integrate large-scale neural network circuits. In other words, the neural network computation circuit including the non-volatile semiconductor memory element of the present disclosure enables the low power consumption and the large-scale integration.

(137) Although the embodiments of the present disclosure have been described above, the neural network computation circuit including the non-volatile semiconductor memory element of the present disclosure is not limited to the above-described examples. The present disclosure is effective for embodiments to which various modifications etc. are made without departing from the scope of the present disclosure.

(138) For example, although the neural network computation circuit including the non-volatile semiconductor memory element in the aforementioned embodiments is an example of a variable resistance non-volatile memory (ReRAM), the present disclosure is applicable to a non-volatile semiconductor memory element other than a variable resistance memory, such as a magnetoresistive non-volatile memory (MRAM), a phase-change non-volatile memory (PRAM), and a ferroelectric non-volatile memory (FeRAM).

(139) Although only some exemplary embodiments of the present disclosure have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure.

INDUSTRIAL APPLICABILITY

(140) Since the neural network computation circuit including the non-volatile semiconductor memory element according to the present disclosure is configured to perform a multiply-accumulate operation using the non-volatile semiconductor memory element, the neural network computation circuit can perform a multiply-accumulate operation without including a multiplication circuit and a cumulative circuit (accumulator circuit) configured as conventional digital circuits. Moreover, digitizing input data and output data makes it easy to integrate large-scale neural network circuits.

(141) Accordingly, the present disclosure is effective in ensuring that the neural network computation circuit achieves the low power consumption and the large-scale integration, and is useful for, for example, a semiconductor integrated circuit equipped with artificial intelligence (AI) technology that performs self-learning and self-determination, and an electronic device including such semiconductor integrated circuits.