Differential activated latch for GaN based level shifter

Abstract

A cross-coupled differential activated latch circuit with circuitry comprising a plurality of n-FETs and inverters that can be implemented completely in GaN. The circuitry prevents the digital latched values on the outputs of the latch from changing unless the digital input values on the inputs are different, thus preventing common-mode voltage on the inputs from corrupting the stored latch values.

Claims

1. A cross-coupled differential activated latch circuit, comprising: first and second inputs for receiving digital input values; first and second outputs for outputting digital latched values; first and second n-FETs connected in a cross-coupled arrangement, with a gate of each of same first and second n-FETs electrically connected to a drain of the other one of the first and second n-FETs, wherein the drain of the first n-FET is connected to the first output, and the drain of the second n-FET is connected to the second output; first and second resistors connected between a voltage source and the first and second outputs, respectively, for pulling up the voltage at the first and second outputs, respectively, when the first and second n-FETs, respectively, are turned off; a node SW having a changing voltage; and circuitry comprising a plurality of n-FETs and inverters connected to the first and second inputs, the first and second outputs, the first and second cross-coupled n-FETs and the node SW, for preventing common mode signals caused by the changing voltage on the node SW from affecting the digital latched values of the first and second outputs, such that the digital latched values on the first and second outputs only change if the digital input values on the first and second inputs are opposite to each other.

2. The cross-coupled differential activated latch circuit of claim 1, wherein the plurality of n-FETs comprise: third and fourth n-FETs electrically coupled in series, wherein a drain of the third n-FET is connected to the gate of the second n-FET, the source of the third n-FET is connected to a drain of the fourth n-FET, and wherein a gate of the fourth n-FET is connected to the first input, and a gate of the third n-FET is connected to an inverse of the second input; and fifth and sixth n-FETs electrically coupled in series, wherein a drain of the fifth n-FET is connected to the gate of the first n-FET, the source of the fifth n-FET is connected to a drain of the sixth n-FET, and wherein a gate of the fifth n-FET is connected to the second input, and a gate of the sixth n-FET is connected to an inverse of the first input.

3. The cross-couple differential activated latch circuit of claim 2, wherein the circuitry implements the logic function:
First Output=((First Input).Math.Second Input+Second Output)
Second Output=((Second Input).Math.First Input)+First Output).

4. The cross-coupled differential activated latch circuit of claim 1, wherein the plurality of n-FETs comprise: third and fourth n-FETs electrically coupled in parallel, wherein a drain of the third n-FET is connected to a drain of the fourth n-FET and a source of the third n-FET is connected to a source of the fourth n-FET, and wherein a gate of the third n-FET is connected to the first input, and a gate of the fourth n-FET is connected to an inverse of the second input; and fifth and sixth n-FETs electrically coupled in parallel, wherein a drain of the fifth n-FET is connected to a drain of the sixth n-FET and a source of the fifth n-FET is connected to a source of the sixth n-FET, and wherein a gate of the fifth n-FET is connected to the second input and a gate of the sixth n-FET is connected an inverse of the first input.

5. The cross-couple differential activated latch circuit of claim 4, wherein the circuitry implements the logic function:
First Output=(Second Output).Math.((First Input)+Second Input)
Second Output=(First Output).Math.((Second Input)+First Input).

6. The cross-coupled differential activated latch circuit of claim 1, wherein the circuitry is implemented entirely in GaN.

7. The cross-coupled differential activated latch circuit of claim 1, further comprising a pulse filter at each of the first and second inputs.

8. The cross-coupled differential activated latch circuit of claim 1, wherein the first and second latch inputs are clamped by diode-connected protection n-FETs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A shows a typical prior art half bridge design, and FIG. 1B shows the voltage at the SW node as the circuit switches.

(2) FIG. 2 is a block diagram of a typical prior art level shifter.

(3) FIG. 3 shows the circuitry of a simple prior art cross-coupled latch.

(4) FIGS. 4A and 4B show a simple prior art SR flip-flop circuit which functions as a latch.

(5) FIG. 5 shows a SR flip-flop latch with an analog differential front-end amplifier.

(6) FIG. 6 shows a prior art circuit for common-mode current rejection using a dynamic current source.

(7) FIG. 7 shows a first embodiment of the differential activated cross-coupled latch of the present invention.

(8) FIG. 8 shows a second embodiment of the differential activated cross-coupled latch of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(9) FIG. 7 shows a first embodiment of the circuit of the present invention, a differential activated cross-coupled latch that does not require p-FETs and can be implemented using GaN processes. The latch value is changed only with differential digital inputs on latch inputs 20 and 22. Common-mode voltage on latch inputs 20 and 22 is treated as digital inputs with the same logic values. The circuit is advantageously designed with inverters 72 and 74 and associated circuitry so that the latch outputs 24 and 26 will not change if both logic inputs are the same, i.e., both low or both high.

(10) Specifically, if both latch inputs 20 and 22 simultaneously become logic low, n-FETs 76 and 80 are turned off, blocking pull down of latch outputs 24 and 26, and maintaining the output logic levels. A logic high on both latch inputs 20 and 22 will turn on n-FET 76 and n-FET 80, and, via inverters 72 and 74, will also turn off n-FET 78 and n-FET 82, thereby blocking pull down of latch outputs 24 and 26 and maintaining the output logic levels. As a result, a common-mode signal appearing as the same logic signal at the latch inputs due to fast positive and negative dv/dt at the SW node 6 in FIG. 1A will not corrupt the latch outputs. A pull down path for current to flow from VddF to SW6 through resistor 30 (and to thereby to bring latch output 24 low and keep latch output 26 high) is only created when latch input 20 is high and latch input 22 is low. Likewise, a pull down path for current to flow from VddF to SW6 through resistor 32 (and to thereby to bring latch output 26 low and keep latch output 24 high) is only created when latch input 20 is low and latch input 22 is high. Thus, the latched value can only be changed with differential digital input values on latch inputs 20 and 22.

(11) The differential activated latch of the first embodiment of the present invention can be considered as having two feedback connected, complex gates with the following two logic functions:
Output 24=((Input 20).Math.Input 22+Output 26)
Output 26=((Input 22).Math.Input 20+Output 24)

(12) As explained above, the output logic value can only be changed by pulling down either latch output 24 or latch output 26. Diode-connected n-FETs for protection are required at inputs 20 and 22, as in the prior art cross-coupled latch circuit of FIG. 3.

(13) FIG. 8 shows a second embodiment of the differential activated latch of the present invention. The output logic values are changed by turning off n-FET 42 or n-FET 44 and letting resistor 30 or resistor 32 pull up latch output 24 or latch output 26.

(14) More specifically, in the embodiment of FIG. 8, if both latch inputs 20 and 22 simultaneously become logic low, n-FETs 76 and 80 are turned off, but both n-FETs 78 and 82 will be turned on due to inverters 74 and 72, respectively. As a result, n-FETs 42 and 44 are connected to SW 6, and the logic outputs on 24 and 26 will maintain the same output logic levels.

(15) When both latch inputs 20 and 22 simultaneously become logic high, both n-FETs 76 and 80 will be turned on, but n-FETs 78 and 82 will be turned off due to inverters 72 and 74. Nevertheless, n-FETs 42 and 44 are still connected to SW 6 and the latch outputs on 24 and 26 will maintain the same logic levels. As a result, common-mode signal appearing as the same logic signal at the latch inputs due to fast positive and negative dv/dt at the SW node 6 in FIG. 1A will not corrupt the latch outputs.

(16) When latch input 20 is low and latch input 22 is high, n-FETs 76 and 82 are both off, such that n-FET 42 is disconnected from SW 6 and resistor 30 pulls up latch output 24. At the same time, n-FET 44 is connected to SW 6 and the latch output 26 will be pulled down by n-FET 44, since n-FET 80 is turned on due to logic high at the latch input 22, and n-FET 78 is also turned on due to inverter 74 with logic low at the latch input 20.

(17) When latch input 20 is high and latch input 22 is low, n-FETs 80 and 78 are both off, such that n-FET 44 is disconnected from SW 6, and resistor 32 pulls up latch output 26. At the same time, n-FET 42 is connected to SW 6 and the latch output 24 will be pulled down by n-FET 42, since n-FET 76 is turned on due to the logic high at the latch input 20, and n-FET 82 is also turned on due to inverter 72 with logic low at the latch input 22.

(18) The differential activated latch of this second embodiment of the present invention can be considered as having two feedback connected, complex gates with the following two logic functions:
Output 24=(Output 26).Math.((Input 20)+Input 22)
Output 26=(Output 24).Math.((Input 22)+Input 20)

(19) Diode-connected n-FETs are required for protection at latch inputs 20 and 22 as in the prior art cross-coupled latch circuit and the first embodiment of the present invention. Other implementations are possible to realize the logic functions in the first and second embodiments of the invention.

(20) An optional pulse filter can be added at latch inputs 20 and 22 in both embodiments of the present invention.

(21) The differential activated latch of the present invention has a number of advantages over the prior art latch circuits described above. For example, the differential control-signal activated latches of the present invention require less power dissipation than the prior art approach of FIG. 5 using an SR flip-flop with a differential front-end amplifier, since the latter approach requires a continuous biasing current to achieve high-speed operation. In addition, a small difference on the common-mode signal at latch input 20 and latch input 22 can make the prior art circuit using a differential amplifier and SR flip-flop react incorrectly to the common-mode signal. The circuit of the present invention will reject this small differential signal when it is less than the noise margin of the logic gates.

(22) Compared to the dynamic current source approach of FIG. 6, the circuit of the present invention does not require p-FETs and can be readily realized in a GaN or NMOS only process. The circuitry of the present invention described above is preferably implemented entirely in GaN.

(23) The circuit of the present invention can, in theory, withstand an infinite positive or negative dv/dt on SW node 6, as long as the gate-to-source voltages of the n-FETs connected to latch inputs 20 and 22 are clamped by diode-connected protection FETs to be within the maximum allowable value.

(24) The above description and drawings are only to be considered illustrative of specific embodiments, which achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Accordingly, the embodiments of the invention are not considered as being limited by the foregoing description and drawings.