METHOD FOR READING A MULTI-LEVEL NON-VOLATILE MEMORY DEVICE, IN PARTICULAR A PHASE-CHANGE MEMORY DEVICE, AND MULTI-LEVEL NON-VOLATILE MEMORY DEVICE

Abstract

A multi-level non-volatile memory cell has N levels, N being even and greater than two, corresponding respectively to N logical data that can be stored in the memory cell and to N corresponding read current ranges. A datum stored in the memory cell is read by performing successive comparisons of a read current output by the memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value.

Claims

1. A method for managing operation of a multi-level non-volatile memory cell, the multi-level non-volatile memory cell having N levels, N being even and greater than two, corresponding respectively to N logical data that can be stored in the multi-level non-volatile memory cell and to N corresponding read current ranges, the method comprising: reading the datum stored in the multi-level non-volatile memory cell by performing successive comparisons of a read current output by the multi-level non-volatile memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value.

2. The method according to claim 1, wherein a reference memory cell that is structurally identical to the multi-level non-volatile memory cell is placed next to the multi-level non-volatile memory cell, and wherein reading comprises successively reading the reference memory cell to cause the reference memory cell to output the corresponding reference currents from the set of N-1 reference currents.

3. The method according to claim 1, wherein reading comprises successively adjusting an adjustable current source to cause the adjustable current source to output the corresponding reference currents from the set of N-1 reference currents.

4. The method according to claim 1, wherein the multi-level non-volatile memory cell is a phase-change type memory cell.

5. The method according to claim 1, wherein the multi-level non-volatile memory cell is a phase-change type memory cell, wherein a reference memory cell that is structurally identical to the multi-level non-volatile memory cell is placed next to the multi-level non-volatile memory cell, wherein the reference memory cell is a phase-change memory cell, wherein reading comprises successively reading the reference memory cell to cause the reference memory cell to output the corresponding reference currents from the set of N-1 reference currents, and further comprising: placing the reference memory cell in a SET state and applying a selected reference voltage to the reference memory cell to cause it to output the corresponding reference current.

6. The method according to claim 1, further comprising programming the multi-level non-volatile memory cell to the desired level and checking the programming by using said reading of the multi-level non-volatile memory cell.

7. The method according to claim 1, wherein the multi-level non-volatile memory cell is a phase-change type memory cell, wherein programming the multi-level non-volatile memory cell to a level lower than a maximum level comprises programming the multi-level non-volatile memory cell to the maximum level, then successively outputting erase pulses erasing the multi-level non-volatile memory cell, respectively followed by successively reading the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.

8. A multi-level non-volatile memory device, comprising: at least one non-volatile memory cell having N levels, N being even and greater than two, corresponding respectively to N logical data that can be stored in the multi-level non-volatile memory cell and to N corresponding read current ranges; and a reading circuit configured to read a datum stored in the multi-level non-volatile memory cell by carrying out successive comparisons of a read current output by the multi-level non-volatile memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value.

9. The device according to claim 8, wherein the reading circuit comprises: a reference memory cell located next to the multi-level non-volatile memory cell and structurally identical to the multi-level non-volatile memory cell; and a read module configured to perform successive readings of the reference memory cell to cause the reference memory cell to output the corresponding reference currents.

10. The device according to claim 8, wherein the reading circuit comprises: an adjustable current source; and a control circuit configured to make successive adjustments to the current source to cause it to output successively selected reference currents.

11. The device according to claim 8, wherein the multi-level non-volatile memory cell is a phase-change type memory cell.

12. The device according to claim 8, wherein the multi-level non-volatile memory cell is a phase-change type memory cell; wherein the phase-change type reference memory cell is programmed in a SET state; wherein the reading circuit comprises: a reference memory cell located next to the multi-level non-volatile memory cell and structurally identical to the multi-level non-volatile memory cell; and a read module configured to perform successive readings of the reference memory cell to cause the reference memory cell to output the corresponding reference currents; and wherein the read module is configured to apply a selected reference voltage to the reference memory cell to cause it to output the corresponding reference current.

13. The device according to claim 8, further comprising: a processing circuit configured to program the multi-level non-volatile memory cell to the desired level; and wherein the reading circuit is configured to check the programming by reading the multi-level non-volatile memory cell.

14. The device according to claim 8, wherein the multi-level non-volatile memory cell is a phase-change type memory cell, further comprising: a processing circuit configured to program the multi-level non-volatile memory cell to the desired level; and wherein the reading circuit is configured to check the programming by reading the multi-level non-volatile memory cell; and wherein the processing circuit is configured to program the multi-level non-volatile memory cell to a level lower than a maximum level by programming the multi-level non-volatile memory cell to the maximum level, then by successively outputting erase pulses erasing the multi-level non-volatile memory cell, respectively followed by successively reading the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.

15. A method for managing the operation of a multi-level non-volatile memory cell, wherein the multi-level non-volatile memory cell is a phase change type memory cell having N levels, N being greater than or equal to two, corresponding respectively to N logical data likely to be stored in the multi-level non-volatile memory cell and N corresponding read current ranges, the method comprising: reading the logical data stored in the multi-level non-volatile memory cell with successive comparisons a read current delivered by the multi-level non-volatile memory cell with reference currents chosen from a set of N-1 reference currents having values respectively located between two different successive ranges; wherein reading uses a dichotomous algorithm starting with the reference current having the median value; placing, next to the multi-level non-volatile memory cell, a reference memory cell with a phase change structurally identical to the multi-level non-volatile memory cell; and successively reading this reference memory cell to cause delivery of corresponding reference currents; wherein delivery of a reference current comprises placing the reference memory cell in an initialized state and applying a selected reference voltage to the reference memory cell to cause delivery of the corresponding reference current.

16. The method of claim 15 further comprising: programming the multi-level non-volatile memory cell at a desired programming level and verifying programming at the desired level reading said multi-level non-volatile memory cell.

17. The method of claim 16, wherein programming comprises programming the multi-level non-volatile memory cell at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level and then successively delivering erasure pulses to the multi-level non-volatile memory cell respectively followed by successive reads of the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.

18. A multi-level non-volatile memory device, comprising: at least one multi-level non-volatile memory cell; wherein the multi-level non-volatile memory cell is a phase change type memory cell having N levels, N being greater than or equal to two, corresponding respectively to N logical data likely to be stored in the multi-level non-volatile memory cell and N corresponding read current ranges; a circuit for reading data stored in the multi-level non-volatile memory cell, wherein said circuit is configured to perform successive comparisons of a read current delivered by the multi-level non-volatile memory cell with reference currents selected from a set of N-1 reference currents having values respectively located between two different successive ranges, using a dichotomous algorithm starting with the reference current having the median value in which the circuit for reading comprises: a reference memory cell of phase change type, located next to the multi-level non-volatile memory cell and structurally identical to the multi-level non-volatile memory cell; and a read module configured to perform successive reads of said reference memory cell to deliver corresponding reference currents; wherein the reference memory cell is programmed in an initialized state and the read module is configured to apply a reference voltage to the reference memory cell to cause delivery of the corresponding reference current.

19. The apparatus of claim 18, further comprising a processing circuit configured to perform a programming of the multi-level non-volatile memory cell at a desired programming level and to perform a programming check by reading said multi-level non-volatile memory cell.

20. The apparatus of claim 19, wherein the processing circuit is configured to perform memory cell programming at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level and then performing successive deliveries of memory cell erasure pulses respectively followed by successive reads from the multi-level non-volatile memory cell until reaching a read current corresponding to the desired programming level.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other advantages and features of the invention will become apparent upon examining the detailed description of non-limiting embodiments and implementations of the invention, and from the accompanying drawings in which:

[0027] FIG. 1 shows a multi-level non-volatile memory device comprising at least one non-volatile memory cell;

[0028] FIG. 2 diagrammatically illustrates a conventional and well-known structure of a phase-change memory cell;

[0029] FIG. 3 illustrates various read currents;

[0030] FIGS. 4 and 5 illustrate an example of the programming of the memory cell;

[0031] FIG. 6 shows a method for reading the memory cell in order to determine the logic datum stored therein;

[0032] FIG. 7 illustrates the implementation of the dichotomous algorithm;

[0033] FIGS. 8 and 9 illustrate an embodiment and implementation of a reference circuit;

[0034] FIG. 10 illustrates use of an adjustable current source as the reference circuit instead of a reference memory cell; and

[0035] FIG. 11 illustrates a single group of a plurality of memory cells.

DETAILED DESCRIPTION

[0036] In FIG. 1, the reference DISP denotes a multi-level non-volatile memory device comprising at least one non-volatile memory cell MLB storing a datum having N levels, N being even and greater than two.

[0037] N is, for example, equal to 4, but is not limited thereto.

[0038] These levels correspond respectively to N logical data that can be stored in the memory cell and to N corresponding read current ranges.

[0039] For example, when N is equal to 4, the 4 corresponding logic data can be respectively equal to 0b00, 0b01, 0b10 and 0b11, in hexadecimal format.

[0040] The device DISP further comprises circuit for reading the datum stored in the memory cell and configured, as will be seen in more detail hereinbelow, to carry out successive comparisons of a read current Iread output by the memory cell MLB with reference currents Iref selected from a set of N-1 reference currents having values respectively lying between two different successive ranges, using a dichotomous algorithm starting with the reference current having the median value.

[0041] Each reference current is output by an adjustable reference circuit REF, one possible structure whereof will be described in more detail hereinbelow.

[0042] In addition to the reference circuit REF, the reading circuit in this case comprises a processing circuit DGC, for example a microcontroller, capable of adjusting the reference circuit REF and of retrieving information representative of the datum D stored in the memory cell MLB.

[0043] This information is output by a conventional sense amplifier AMP, forming part of the reading circuit, and including a first input E1 connected to the memory cell MLB for receiving the read current Iread, a second input E2 connected to the reference circuit REF for receiving the reference current Iref, and an output OUT intended to output the information representative of the stored datum D.

[0044] Although the memory cell can be any type of non-volatile memory cell, for example a memory cell of the floating gate type with a buried selection transistor, or a memory cell of the electrically erasable programmable read-only memory (EEPROM) type, one implementation and embodiment will now be described wherein, unless specified otherwise, the memory cell MLB is of the phase-change type.

[0045] As is well known to a person skilled in the art, phase-change memories are non-volatile memories that rely on the properties of phase-change materials.

[0046] More specifically, a phase-change material is able to switch from a low-resistance state to a high-resistance state under heating.

[0047] Phase-change memories take advantage of the fact that the electric resistances of the different states of the phase-change materials are different in order to store data.

[0048] More specifically, when the memory is intended to store a binary logic value having two logic states, the phase-change material is able to switch from a High-Resistance State (HRS) to a Low-Resistance State (LRS) under the effect of heat and the Joule effect generated by the application of a current between electrodes.

[0049] Switching from a high-resistance state to a low-resistance state corresponds to a programming or activation operation referred to as SET, i.e., an operation writing a binary datum value, for example a logic value 1. The memory is thus in a so-called SET state.

[0050] Switching from a low-resistance state to the high-resistance state corresponds to an erase or deactivation operation referred to as RESET, i.e., an operation to write an opposite binary datum value, for example a logic value 0. The memory is thus in a so-called RESET state.

[0051] To carry out a programming or SET operation, the phase-change material is heated between its crystallization and melting temperatures and then slowly cooled to obtain a crystalline phase. The current pulse thus decays slowly.

[0052] However, in order to make the phase-change material amorphous (the erase or RESET operation), it is heated above its melting temperature and then rapidly cooled to set it in the amorphous state at room temperature. The current pulse is thus very short and abrupt.

[0053] As will be seen in more detail hereinbelow, when the memory is a multi-level memory, i.e., when it is capable of storing logical data that can take N different logic values (N being greater than two), intermediate states between the RESET state and the SET state can be provided for the memory cell.

[0054] Thus, when N is equal to 4, two intermediate states can be provided, which intermediate states correspond respectively to a partially RESET state and to a partially SET state.

[0055] The various states of the memory cell are differentiated by the value of the read current Iread output by the memory cell.

[0056] FIG. 2 diagrammatically illustrates a conventional and well-known structure of a phase-change memory cell MLB.

[0057] More specifically, it includes a memory element, for example containing germanium, antimony and tellurium, which have different resistance values depending on the RESET/partially RESET/partially SET/SET states of the memory.

[0058] This memory element is associated with a heating device, for example two electrodes, which, when a current flows therethrough, heats the memory element by Joule effect to vary the resistance thereof.

[0059] The memory cell MLB is associated with a selection transistor TS, in this case a bipolar transistor PNP connected in series between the memory element and a neutral supply point, typically the ground GND.

[0060] The base of the bipolar transistor is connected to a word line and is intended to receive a voltage V.sub.WL switching this transistor on so as to allow current to flow through the heating device in order to heat the memory element.

[0061] It goes without saying that the bipolar transistor TS could be replaced by an MOS transistor, for example by a PMOS transistor.

[0062] A memory cell CEL in a SET state is, for example, intended to output a read current Iread in the order of, for example, 12 microamperes.

[0063] A memory cell CEL in its RESET state is capable of outputting a current Iread of, for example, zero or almost zero amperes.

[0064] A memory cell CEL in its partially RESET state is capable of outputting, for example, a current Iread in the order of 4 microamperes.

[0065] A memory cell CEL in its partially SET state is capable of outputting, for example, a current Iread in the order of 8 microamperes.

[0066] These currents are obtained in the presence, for example, of a voltage applied to the memory element of between 1.5 and 1.8 volts for a bipolar selection transistor TS and between 0.4 and 0.5 volts for a selection transistor of the MOS type.

[0067] FIG. 3 in particular illustrates these various read currents.

[0068] In practice, and by way of a non-limiting example, the values 0, 4, 8 and 12 microamperes correspond to target read current values Itread0, Itread1, Itread2, and Itread3.

[0069] In practice, the effective read currents can lie within the value ranges PV1, PV2 and PV3 around the target values Itread1, Itread2 and Itread3 and within the value range PV0 starting at the target value Itread0.

[0070] For simplification purposes, the value ranges PV1-PV3 have the same amplitude PV and the value range PV0 has an amplitude equal to PV/2.

[0071] This amplitude PV depends, in particular, on the sensitivity of the sense amplifier AMP and/or on a tolerance when programming/erasing the memory cell.

[0072] By way of a non-limiting example, the amplitude PV can be taken to be equal to 1 microampere.

[0073] In practice, however, in the case of a phase-change memory cell, the range PV can, under certain conditions, increase as the conductance increases.

[0074] The value range PV3 can thus be higher than the value range PV2, which can itself be higher than the value range PV1, which itself can be higher than the value range PV0.

[0075] However, for non-volatile floating-gate memory cells, the amplitude PV remains more or less constant.

[0076] As illustrated in FIG. 3, these target values and their associated value range define in this case, for the memory cell MLB, four levels LV0, LV1, LV2 and LV3 respectively associated with the following four logic values of the datum D: 00b0, 00b01, 00b10 et 00b11.

[0077] Three reference currents Iref1, Iref2 and Iref3, intended to be output by the reference circuit REF, are defined and have values lying between adjacent ones of the value ranges PV0-PV3, for example in the middle of the intervals between the adjacent value ranges.

[0078] Thus, in this case, the values of these reference currents Iref1, Iref2 and Iref3 are equal to, for example, 2, 4 and 6 microamperes respectively.

[0079] FIGS. 4 and 5 illustrate an example of the programming of the memory cell MLB.

[0080] This programming is carried out under the control of a processing circuit incorporated in the microcontroller DGC.

[0081] A programming pulse PLS is firstly output (FIG. 4) to the memory cell so as to place it in its SET state.

[0082] The memory cell thus has level LV3 (FIG. 5) corresponding to a read current Iread of between 11.5 and 12.5 microamperes.

[0083] If the memory cell is to be programmed to level LV2, corresponding to a read current Iread of between 7.5 and 8.5 microamperes, a burst BST1 of erase pulses PLRS is output to the memory cell until the desired read current is reached.

[0084] If the memory cell is to be programmed to level LV1, corresponding to a read current Iread of between 4.5 and 3.5 microamperes, another burst BST2 of erase pulses PLRS is output to the memory cell until the desired read current is reached.

[0085] If the memory cell is to be RESET to level LV0, corresponding to a read current Iread of between 0.5 and 0 microamperes, another burst BST3 of erase pulses PLRS is output to the memory cell until the desired read current is reached.

[0086] In practice, after each erase pulse in a given burst, the memory cell is read, as explained hereinbelow, in order to check the read current obtained and decide whether another erase pulse is required.

[0087] However, other programming schemas are possible.

[0088] More specifically, a first cycle can be carried out, which cycle includes a programming pulse, followed by an erase pulse, followed by a reading of the memory cell. If the desired read current is not obtained, the same cycle is repeated, but with an erase pulse of a more adjusted amplitude. These cycles are repeated until the desired read current is obtained.

[0089] Reference is now made more particularly to FIG. 6 to describe one implementation of a method for reading the memory cell MLB in order to determine the logic datum stored therein.

[0090] The microcontroller DGC adjusts the reference circuit so as to cause it to output the reference current Iref2 having the median value from among the values of the set of reference currents Iref1-Iref3 (step ST60).

[0091] The reading circuit then read the memory cell MLB (step ST61) by applying a read voltage to the memory cell so as to cause it to output the read current Iread.

[0092] The sense amplifier AMP then compares (step ST62) the read current Iread with the reference current Iref2.

[0093] If the reference current Iref2 is less than the current Iread, then the result Res output by the amplifier AMP corresponds to a logic 1.

[0094] This means that the read current Iread lies in the interval to the right of Iref2 in FIG. 3.

[0095] If the reference current Iref2 is greater than the current Iread, then the result Res output by the amplifier AMP corresponds to a logic 0.

[0096] This means that the read current Iread lies in the interval to the left of Iref2 in FIG. 3.

[0097] The microcontroller will thus implement a dichotomous algorithm to halve the interval considered and continue to do so in order to obtain the value of the datum D stored in the memory cell.

[0098] More specifically, if in step ST62 the result Res is 1, the microcontroller will adjust the reference circuit REF so that it outputs the reference current Iref3 (step ST66).

[0099] The reading circuit reads the memory cell MLB again (step ST67).

[0100] The corresponding read current Iread is compared in the sense amplifier AMP with the reference current Iref3.

[0101] If Iref3 is less than Iread, which corresponds to a result Res of 1, this means that the current Iread lies in the interval to the right of Iref3 in FIG. 3.

[0102] As a result, since there is no longer any interval to halve and thus no longer any uncertainty about the value of the logical datum, the datum D in this case has the logic value 0b11.

[0103] If Iref3 is greater than Iread, which corresponds to a result Res of 0, this means that the current Iread lies in the interval to the left of Iref3 in FIG. 3.

[0104] As a result, since there is no longer any interval to halve and thus no longer any uncertainty about the value of the logical datum, the datum D in this case has the logic value 0b10.

[0105] More specifically, if in step ST62 the result Res is 0, the microcontroller will adjust the reference circuit REF so that it outputs the reference current Iref1 (step ST63).

[0106] The reading circuit read the memory cell MLB again (step ST64).

[0107] The corresponding read current Iread is compared in the sense amplifier AMP with the reference current Iref1.

[0108] If Iref1 is less than Iread, which corresponds to a result Res of 1, this means that the current Iread lies in the interval to the right of Iref1 in FIG. 3.

[0109] As a result, since there is no longer any interval to halve and thus no longer any uncertainty about the value of the logical datum, the datum D in this case has the logic value 0b01.

[0110] If Iref1 is greater than Iread, which corresponds to a result Res of 0, this means that the current Iread lies in the interval to the left of Iref1 in FIG. 3.

[0111] As a result, since there is no longer any interval to halve and thus no longer any uncertainty about the value of the logical datum, the datum D in this case has the logic value 0b00.

[0112] FIG. 7 illustrates the implementation of the dichotomous algorithm in the general case where N is even and greater than 3.

[0113] The algorithm uses a parameter A, which is set to the value 2.

[0114] The microcontroller adjusts the reference circuit REF such that it outputs a current Iref equal to Imax/A (step ST70).

[0115] Imax denotes the maximum of the target values for the read currents.

[0116] In the case shown in FIG. 6, Imax was the value of the current Itread3, i.e., 12 microamperes.

[0117] Then, in step ST71, the memory cell MLB is read.

[0118] If the result Res is equal to 1, the value of A is doubled (step ST72) and, in step ST73, the microcontroller adjusts the reference circuit REF such that it outputs a current Iref, whose value is equal to the previous value increased by N.Imax/A. (N-1).

[0119] If the result Res is equal to 0, the value of A is doubled (step ST75) and, in step ST76, the microcontroller adjusts the reference circuit REF such that it outputs a current Iref, whose value is equal to the previous value decreased by N.Imax/A. (N-1).

[0120] If, in step ST74, A is less than or equal to N, the microcontroller circles back to step ST71.

[0121] If, on the other hand, A is greater than N, this means that the entire dichotomy has been performed and that the value of the datum D has been determined.

[0122] Reference is now made more particularly to FIGS. 8 and 9 to describe an embodiment and implementation of a reference circuit REF.

[0123] The features of this embodiment and implementation provide for the use of a reference memory cell CELR (FIG. 8) of the phase-change type for the reference circuit REF.

[0124] The memory cell MLB and the reference memory cell CELR have an identical structure and are placed side by side.

[0125] The reference memory cell is programmed in a SET state and a read module is configured to apply a selected reference voltage to the reference memory cell to cause it to output the corresponding reference current.

[0126] The base of the bipolar selection transistor TSR associated with the reference memory cell CELR is also intended to receive the voltage V.sub.wL.

[0127] It goes without saying that the bipolar transistor TSR could be replaced by an MOS transistor, for example by a PMOS transistor.

[0128] The memory device DISP further includes a bit line BL associated with the memory cell MLB and a bit line BLR associated with the reference memory cell CELR.

[0129] The reference RC denotes the stray resistances and capacitances resulting from interconnections between the various elements of the device DISP.

[0130] The reading module includes a first voltage generator GEN1 and a second voltage generator GEN2 intended to be respectively connected to the bit lines BL and BLR.

[0131] Moreover, the bit lines BL and BLR are respectively connected to the two inputs E1 and E2 of the sense amplifier AMP.

[0132] The memory cell MLB is connected to the bit line BL, whereas the reference cell CELR is connected to the bit line BLR.

[0133] The fact that the memory cell MLB and the reference memory cell are placed side by side ensures that the voltages applied to the bases of the selection transistors TS and TSR are substantially the same and that the read paths of the memory cell MLB and the read paths of the reference memory cell CELR are correctly balanced.

[0134] For information, a distance of between 10 micrometers and 20 micrometers between the memory cell MLB and the reference memory cell CELR can advantageously be selected for 18-nanometer technology.

[0135] It goes without saying that this distance value is only an example and that a person skilled in the art will be able to adjust this value, where necessary, depending in particular on the features of the memory cells and of the read schemas.

[0136] The reading of the cell CEL is a single-input read (as opposed to a differential read) described with reference to FIG. 9.

[0137] In a step ST31, a voltage VBL1 is applied to the bit line BL and a voltage VBL2 is applied to the bit line BLR.

[0138] These two voltages VBL1 and VBL2 are respectively output by the two current generators GEN1 and GEN2.

[0139] The voltage VBL1 is that producing a current corresponding to the SET state of the memory cell MLB (typically 12 microamperes).

[0140] For a bipolar selection transistor, a voltage VBL1 of between 1.5V and 1.8V will be selected.

[0141] The voltage VBL2 is less than or equal to the voltage VBL1, in order to cause the selected reference current to be output to the reference memory cell CELR.

[0142] By way of example, in order to obtain the reference current Iref 3 (10 microamperes), a voltage VBL2 of between 1.5V and 1.8V will be used for a bipolar selection transistor.

[0143] By way of example, in order to obtain the reference current Iref 2 (6 microamperes), a voltage VBL2 of between 1.35V and 1.7V will be used for a bipolar selection transistor.

[0144] By way of example, in order to obtain the reference current Iref 1 (2 microamperes), a voltage VBL2 of between 1.2V and 1.55V will be used for a bipolar selection transistor.

[0145] Once the bit lines BL and BLR have been biased with voltages VBL1 and VBL2 in step ST31, the bit lines BL and BLR are set to a floating state (step ST32), for example by disconnecting the two generators GEN1 and GEN2 from the bit lines BL and BLR or by stopping generation.

[0146] As the transistors TS and TSR are on, the memory cell MLB draws the current Iread flowing on the bit line BL, whereas the reference memory cell CELR draws the reference current Iref flowing on the bit line BLR (step ST33).

[0147] These two currents Iref and Iread are compared (step ST34) in the sense amplifier AMP.

[0148] If the current Iref is less than the current Iread, then the result Res is equal to 1.

[0149] If the current Iread is greater than the current Iref, then the result Res is equal to 0.

[0150] It is also possible, as illustrated in FIG. 10, to use an adjustable current source SC as the reference circuit REF, instead of a reference memory cell CELR.

[0151] The microcontroller DGC incorporates control circuit capable of adjusting the current source SC to cause it to output the selected reference current.

[0152] The current source SC thus draws a current Iref (selected from the set of currents Iref1-Iref3) on the bit line BLR, whereas the memory cell MLB draws a current Iread on the bit line BL.

[0153] The two currents are compared in the sense amplifier AMP.

[0154] However, the single-input mode reading using the reference memory cell CELR is more precise than the single-input reading method using a current source, because it is less sensitive to the resistance difference of the memory cell MLB and to the structural differences observed between a memory cell and a current source.

[0155] Typically, in practice, the memory device comprises a memory map having a matrix of memory cells organized into rows and columns.

[0156] Thus, as illustrated in FIG. 11, wherein the memory cells are referenced with the root CEL, a row of memory cells includes groups of a plurality of memory cells.

[0157] For simplification purposes, FIG. 11 illustrates a single group of a plurality of memory cells CELG.sub.i and CELD.sub.i respectively coupled to the first input E1 of the sense amplifier AMP via controllable switches SW.

[0158] A single reference memory cell CELR is associated with this group of memory cells CEL.

[0159] This saves considerable space on silicon.

[0160] Moreover, this reference memory cell is connected to the second input E2 of the sense amplifier as described hereinabove.

[0161] Control circuit MCM, for example a logic circuit, is thus configured to successively select said switches SW so that the reading circuit can successively read each memory cell CEL as explained hereinabove.

[0162] In practice, groups of Nb memory cells associated with a single reference memory cell CELR could be selected, for example.

[0163] Moreover, so as not to distance the memory cells in this group too far from the reference memory cell, a number Nb of memory cells is selected, and the memory cells are divided into two sub-groups of Nb/2 memory cells.

[0164] Moreover, as illustrated in FIG. 11, the reference memory cell CELR is bordered by a first sub-group of Nb/2 memory cells CELG.sub.1-CELG.sub.Nb/2 and by a second group of Nb/2 memory cells CELD.sub.1-CELD.sub.Nb/2.

[0165] The distance DD between each memory cell CELG.sub.1-CELD.sub.1 immediately adjacent to the reference memory cell is, as indicated hereinabove, preferably in the order of 10 to 20 microns.

[0166] Moreover, a person skilled in the art will select the value of Nb/2 so that the memory cells CELG.sub.Nb/2-CELD.sub.Nb/2 located the furthest from the reference cell are not excessively impacted by a too great distance relative to the reference memory cell CELR.

[0167] For example, groups of 8 memory cells can be selected on each row of the memory map.

[0168] Each group is thus associated with a reference cell bordered on the left and right by 4 memory cells.

[0169] Moreover, for example, the first cell on the left MLBG.sub.1 is firstly read, then the other cells on the left are successively read until the cell MLBG.sub.Nb/2 is read.

[0170] Subsequently, the first cell on the right MLBD.sub.1 is read, then the other cells on the right are successively read until the cell MLBD.sub.Nb/2 is read.

[0171] It goes without saying that any other reading order is possible.

[0172] As indicated hereinabove, the invention, and in particular the method for reading using a dichotomous algorithm, applies to any type of multi-level non-volatile memory, for example a floating-gate memory with a selection transistor buried in the semiconductor substrate.

[0173] However, with this type of memory, the various levels are programmed by completely erasing the memory to obtain level LV0, then by successively programming the memory to obtain levels LV1 and following until the desired level is obtained.

[0174] This is thus the reverse of what occurs for a phase-change memory, where the memory is firstly programmed to the highest level (SET) and then gradually erased to obtain the lower levels until the desired level is obtained.