OXIDATION AND CORROSION PREVENTION IN SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE ASSEMBLIES

Abstract

In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.

Claims

1. A semiconductor device comprising: a semiconductor substrate; an active circuit disposed on a surface of the semiconductor substrate; a first metallization layer disposed on the active circuit, the first metallization layer including a first through hole; a first non-conducting layer disposed on the first metallization layer and in the first through hole, the first non-conducting layer including a second through hole; a second metallization layer disposed on the first non-conducting layer and in the second through hole, the second metallization layer including a third through hole separating the second metallization layer into a first portion and second portion; a corrosion prevention implant disposed in an upper surface of the second metallization layer; and a second non-conducting layer disposed on the second metallization layer and in the third through hole, the second non-conducting layer including a fourth through hole above the second portion of the second metallization layer, the fourth through hole exposing at least a portion of the upper surface of the second metallization layer.

2. The semiconductor device of claim 1, wherein the active circuit includes at least one electrical contact.

3. The semiconductor device of claim 1, wherein the first portion of the second metallization layer is electrically coupled with the semiconductor substrate via an electrical contact.

4. The semiconductor device of claim 1, wherein at least one of the first through hole, the second through hole, the third through hole and the fourth through hole includes tapered side walls.

5. The semiconductor device of claim 1, further comprising a connector electrically coupled to the upper surface of the second metallization layer.

6. A silicon carbide semiconductor device comprising: a silicon carbide substrate; an active circuit disposed on a surface of the silicon carbide substrate; a first metallization layer disposed on the active circuit, the first metallization layer including a first through hole; a first non-conducting layer disposed on the first metallization layer and in the first through hole, the first non-conducting layer including a second through hole; a second metallization layer disposed on the first non-conducting layer and in the second through hole, the second metallization layer including a third through hole separating the second metallization layer into a first portion and a second portion; a corrosion prevention implant disposed in an upper surface of the second metallization layer; and a second non-conducting layer disposed on the second metallization layer and in the third through hole, the second non-conducting layer including a fourth through hole above the second portion of the second metallization layer, the fourth through hole exposing at least a portion of the upper surface of the second metallization layer.

7. The silicon carbide semiconductor device of claim 6, wherein the active circuit includes at least one electrical contact.

8. The silicon carbide semiconductor device of claim 6, wherein the first portion of the second metallization layer is electrically coupled with the silicon carbide substrate via an electrical contact.

9. The silicon carbide semiconductor device of claim 6, wherein at least one of the first through hole, the second through hole, the third through hole and the fourth through hole includes tapered side walls.

10. A method for producing a semiconductor device, the method comprising: forming an active circuit on a surface of a semiconductor substrate; forming a first metallization layer on the active circuit, the first metallization layer including a first through hole; forming a first non-conducting layer on the first metallization layer and in the first through hole, the first non-conducting layer including a second through hole; forming a second metallization layer on the first non-conducting layer and in the second through hole, the second metallization layer including a third through hole separating the second metallization layer into a first portion and second portion; forming a corrosion prevention implant in an upper surface of the second metallization layer; and forming a second non-conducting layer on the second metallization layer and in the third through hole, the second non-conducting layer including a fourth through hole above the second portion of the second metallization layer, the fourth through hole exposing at least a portion of the upper surface of the second metallization layer.

11. The method of claim 10, wherein forming the active circuit includes forming at least one electrical contact of the active circuit.

12. The method of claim 10, further comprising forming an electrical contact electrically coupling the first portion of the second metallization layer to the semiconductor substrate.

13. The method of claim 10, wherein at least one of the first through hole, the second through hole, the third through hole and the fourth through hole includes tapered side walls.

14. The method of claim 10, comprising electrically coupling a connector to the upper surface of the second metallization layer.

15. A semiconductor device assembly having an active circuit embedded in the semiconductor device assembly comprising: a semiconductor substrate including an active circuit; a first metallization layer disposed on the active circuit of the semiconductor substrate; a first non-conducting layer disposed on the first metallization layer; a second metallization layer disposed on the first non-conducting layer; a corrosion prevention implant disposed in an upper surface of the second metallization layer; and a second non-conducting layer disposed on the second metallization layer, the second non-conducting layer including a through hole exposing at least a portion of the upper surface of the second metallization layer.

16. The semiconductor device assembly of claim 15, further comprising an external electrical connector that is electrically coupled with the active circuit via the first metallization layer and the second metallization layer.

17. The semiconductor device assembly of claim 15, wherein the active circuit includes at least one electrical contact.

18. The semiconductor device assembly of claim 15, wherein the second metallization layer is electrically coupled with the semiconductor substrate via an electrical contact.

19. The semiconductor device assembly of claim 15, wherein the through hole includes tapered side walls.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 is a block diagram schematically illustrating an apparatus including an example implementation for corrosion prevention.

[0027] FIG. 2 is a diagram illustrating another apparatus including an example implementation for corrosion prevention.

[0028] FIG. 3 is a diagram illustrating yet another apparatus including an example implementation for corrosion prevention.

[0029] FIG. 4 is a diagram illustrating a semiconductor device including an example implementation for corrosion prevention.

[0030] FIG. 5 is a flowchart illustrating semiconductor processing operations, in accordance with an implementation.

[0031] FIG. 6 is another flowchart illustrating semiconductor processing operations, in accordance with an implementation.

[0032] In the drawings, which are not necessarily drawn to scale, like reference symbols may indicate like and/or similar components (elements, structures, etc.) in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various implementations discussed in the present disclosure. Reference symbols show in one drawing may not be repeated for the same, and/or similar elements in related views. Reference symbols that are repeated in multiple drawings may not be specifically discussed with respect to each of those drawings, but are provided for context between related views. Also, not all like elements in the drawings are specifically referenced with a reference symbol when multiple instances of that element are illustrated.

DETAILED DESCRIPTION

[0033] This disclosure is directed to approaches preventing corrosion (oxidation, etc.) of metallization, e.g., exposed metallization, in semiconductor devices and/or semiconductor device assemblies, where such corrosion can cause poor electrical interconnection quality, such as due to poor wire bond or conductive clip adhesion. Thus, the approaches described herein facilitate producing electric interconnections for semiconductor devices and/or semiconductor device assemblies with good adhesion quality, and good conductivity (low resistance). The approaches described herein can also overcome at least some of the drawbacks of current approaches. For instance, the disclosed approaches can be less complex, can be easily integrated with existing manufacturing processes, may be lower cost than the current approaches, and can prevent cross-contamination.

[0034] In the approaches described herein, a corrosion-prevention implant process can be performed in an upper portion of metallization layers to inhibit corrosion of, or portions, of those metallization layers prior to forming electrical connections using, e.g., wire bonds and/or conductive clips. In some implementations, by way of example, aluminum (Al), magnesium (Mg) and/or nitrogen (N) (e.g., Al, Mg and/or N ions) can be implanted in an upper portions of a metallization layer, such as copper (Cu) metallization, aluminum-copper (AlCu) metallization, titanium-nickel-copper (TiNiCu) metallization, or titanium-nickel-silver (TiNiAg) metallization.

[0035] While generally described with respective to semiconductor devices, and semiconductor wafer fabrication, the approaches described herein can also be applied in conjunction with other components of semiconductor device assemblies, such as metallization layers included on a substrate, such a direct-bonded metal (DBM) substrate. In some implementations, metallization layers described herein can be referred to as top metallization layers, where additional metallization layers can be included with the top metallization layers in a stack, with dielectric layers and/or passivation layers being disposed between different layers of metallization, such as in a semiconductor device produced with a process that includes forming multiple layers of interconnected patterned metallization.

[0036] FIG. 1 is a block diagram schematically illustrating an apparatus 100 including an example implementation for corrosion prevention. As shown in FIG. 1, the apparatus 100 includes a substrate 110, a metallization layer 120 and an electrical connector 130. In some implementations, the substrate 110 can include a semiconductor device, such as a semiconductor die or a semiconductor wafer. For instance, the substrate 110 can include a silicon die (or silicon wafer) having integrated circuitry formed along a side or surface, e.g., an upper side or surface in the view shown in FIG. 1. For purposes of brevity and clarity, specifics of such circuitry are not shown or described herein, and those specifics will depend on the particular implementation. In some implementations, the substrate 110 can include other semiconductor materials

[0037] In this example, the metallization layer 120 can be a top level metallization layer that is patterned, e.g., using photolithography, where such patterning is appropriate for a given implementation. The metallization layer 120 can have a surface 121, which can be fully exposed, or can be partially exposed, such as through a passivation layer (not shown). In some implementations, the metallization layer 120 can include one or more of Cu, AlCu, TiNiCu, or TiNiAg, though other metals can be used.

[0038] In some implementations, the substrate 110 can be a ceramic substrate, such as included in a DBM substrate. For instance, the substrate 110 can include aluminum-oxide, or aluminum-nitride, though other materials can be used. In this example, the metallization layer 120 can be a patterned metallization layer (e.g., Cu layer) that is direct-bonded, e.g., using a sintering process, and can be used for electrical connection to a corresponding semiconductor device, e.g., using the electrical connector 130.

[0039] As further shown in FIG. 1, the metallization layer 120, in either of the above example implementations, can have a corrosion-prevention implant 122 that is disposed in the metallization layer 120. In this example, the corrosion-prevention implant 122 is formed through the surface 121 of the metallization layer 120, where a surface 123 (bottom surface) of the metallization layer 120, opposite the surface 121, can be disposed on the substrate 110. In implementations, the corrosion-prevention implant 122 includes one or more materials that inhibit corrosion of the metallic layer 120. The particular materials included in the corrosion-prevention implant 122 can depend, at least in part, on the composition of the metallization layer 120. In some implementations, the corrosion-prevention implant 122 can include Al, Mg and/or N, e.g., implanted as ions. In some implementations, the corrosion-prevention implant 122 can include other substances.

[0040] The corrosion-prevention implant 122 can be formed using an ion beam with an energy and ion dose that is appropriate for the particular implementation. For example, the implantation energy and dose can depend on the composition of the metallization layer 120 and/or on a process used to produce the metallization layer 120, e.g., sputtering, plating, etc. As one example, a Cu metallization layer that is formed using sputtering can be implanted with Al ions using an energy in a range of 10 of kiloelectron volts (keV) and 60 keV, and an implant dose in a range of 1?10.sup.15 cm-2 to 6?10.sup.15 cm.sup.?2.

[0041] In this example, the corrosion-prevention implant 122 is only formed in a portion of the metallization layer 120 along the surface 121, while other portions of the metallization layer 120 along the surface 121 exclude the corrosion-prevention implant 122. Such an approach could be used for bond pads of a semiconductor device, where the portions of the metallization layer 120 that exclude the corrosion-prevention implant 122 may be covered by passivation that blocks the corrosion-prevention implant 122 during its formation. In other implementations, the corrosion-prevention implant 122 can be formed over the entirety of the surface 121 of the metallization layer 120, such as for metallization of a redistribution layer for a chip-scale package, or for metallization included in a DBM substrate. Such an approach can be referred to as a blanket implant.

[0042] As illustrated in FIG. 1, the metallization layer 120 can have a thickness T1, while the corrosion-prevention implant 122 can have a depth T2 in the metallization layer 120 that is measured from the surface 121. In the apparatus 100, the depth T2 is less than the thickness T1. Depending on the specific implementation (e.g., a semiconductor device or a DBM substrate) the thickness TI can be greater than or equal to 2 microns (?m), while the depth T2 can be less than or equal to 100 nanometers (nm). In some implementations, the thickness TI can be in a range of 1 to 10 ?m and the depth T2 can be in a range of 50 to 100 nm. In some implementations, the depth T2 can be less than or equal to ten percent of the thickness T1.

[0043] In the apparatus 100, the electrical connector 130 is disposed on, and electrically coupled with the surface 121 corresponding with the portion of the metallization layer 120 including the corrosion-prevention implant 122. Depending on the particular implementation, the electrical connector 130 can be a wire bond, a conductive clip, a solder ball, and so forth, where the electrical connector 130 can facilitate electrical connection with the metallization layer 120 and/or the substrate 110. In such an arrangement, the corrosion-prevention implant 122, by preventing corrosion (oxidation, or otherwise) of the metallization layer 120, can facilitate a low resistance and mechanically robust connection between the metallization layer 120 and the electrical connector 130, while avoiding drawbacks of current approaches.

[0044] FIG. 2 is a diagram schematically illustrating another apparatus 200 including an example implementation for corrosion prevention. In some implementations the apparatus 200 can be implemented in conjunction with the example implementations of the apparatus 100 discussed above. For instance, the apparatus 200 could be included in implementations of the apparatus 100 where the substrate 110 includes a semiconductor device or wafer, or could be included in implementations of the apparatus 100 where the substrate 110 includes a ceramic layer (e.g., of a DBM substrate). As shown in FIG. 2, the apparatus 200 includes a metallization layer 220, and a conductive clip 230 (electrical connector) that electrically couples the metallization layer 220 with a leadframe 240, e.g., of a corresponding semiconductor device assembly. For instance, the conductive clip 230 can be coupled with the metallization layer 220 via solder layer, or other electrically conductive adhesive (not explicitly shown in FIG. 2).

[0045] As compared with the corrosion-prevention implant 122 of the apparatus 100, the metallization layer 220 includes a corrosion-prevention implant 222 that is disposed (e.g., using a blanket implant) in the metallization layer 220 along an entirety of a surface 221 (e.g., using a blanket implant). In this example, the corrosion-prevention implant 222 is formed through the surface 221 of the metallization layer 220. As with the corrosion-prevention implant 122, in implementations, the corrosion-prevention implant 222 includes one or more materials that inhibit corrosion of the metallic layer 220. The particular materials included in the corrosion-prevention implant 222 can depend, at least in part, on the composition of the metallization layer 220. For instance, in some implementations, the metallization layer 220 can include one or more of Cu, AlCu, TiNiCu, or TiNiAg, though other metals can be used. In some implementations, the corrosion-prevention implant 222 can include Al, Mg and/or N, e.g., implanted as ions. In some implementations, the corrosion-prevention implant 222 can include other substances.

[0046] Also, as with the corrosion-prevention implant 122, the corrosion-prevention implant 222 can be formed using an ion beam with an energy and ion dose that is appropriate for the particular implementation. For example, the implantation energy and dose can depend on the composition of the metallization layer 220 and/or on a process used to produce the metallization layer 220, e.g., sputtering, plating, etc. In some implementations, the metallization layer 220 can have a thickness consistent with the ranges described with respect to the metallization layer 120, and the corrosion-prevention implant 222 can have a depth consistent with ranges described above with respect to the corrosion-prevention implant 122.

[0047] FIG. 3 is a diagram schematically illustrating another apparatus 300 including an example implementation for corrosion prevention. As with the apparatus 200, in some implementations the apparatus 300 can be implemented in conjunction with the example implementations of the apparatus 100 discussed above. For instance, the apparatus 300 could be included in implementations of the apparatus 100 where the substrate 110 includes a semiconductor device or wafer, or could be included in implementations of the apparatus 100 where the substrate 110 includes a ceramic layer (e.g., of a DBM substrate). As shown in FIG. 3, the apparatus 300 includes a metallization layer 320, and a bond wire 330 (electrical connector) that electrically couples the metallization layer 320 with a leadframe 340, e.g., of a corresponding semiconductor device assembly.

[0048] The metallization layer 320 includes a corrosion-prevention implant 322 that is disposed in the metallization layer 320 along only a portion of a surface 321 and is excluded from other portions of the metallization layer 320, such as with the corrosion-prevention implant 122 in the metallization layer 120 of FIG. 1. In this example, the corrosion-prevention implant 322 is formed through the surface 321 of the metallization layer 320, e.g., through an opening in a passivation layer 350. As with the corrosion-prevention implant 122 and the corrosion-prevention implant 222, in implementations, the corrosion-prevention implant 322 includes one or more materials that inhibit corrosion of the metallic layer 320. The particular materials included in the corrosion-prevention implant 322 can depend, at least in part, on the composition of the metallization layer 320. For instance, in some implementations, the metallization layer 320 can include one or more of Cu, AlCu, TiNiCu, or TiNiAg, though other metals can be used. In some implementations, the corrosion-prevention implant 322 can include Al, Mg and/or N, e.g., implanted as ions. In some implementations, the corrosion-prevention implant 322 can include other substances.

[0049] Also, as with the corrosion-prevention implant 122 and the corrosion-prevention implant 222, the corrosion-prevention implant 322 can be formed using an ion beam with an energy and ion dose that is appropriate for the particular implementation. For example, the implantation energy and dose can depend on the composition of the metallization layer 320 and/or on a process used to produce the metallization layer 320, e.g., sputtering, plating, etc. In some implementations, the metallization layer 320 can have a thickness consistent with the ranges described with respect to the metallization layer 120, and the corrosion-prevention implant 322 can have a depth consistent with ranges described above with respect to the corrosion-prevention implant 122.

[0050] FIG. 4 is a diagram illustrating a semiconductor device 400 including an example implementation for corrosion prevention. The semiconductor device 400 includes a semiconductor substrate 410, e.g., such as a silicon substrate, a silicon-carbide substrate, etc. As schematically shown FIG. 4, the substrate 410 includes an active circuitry layer 412 formed therein and/or thereon. The semiconductor device 400 also includes a metallization layer 414, of which a portion of is electrically coupled with the substrate 410 via contacts 416. The semiconductor device 400 further includes a dielectric layer 460 that, at least, isolates portions of the metallization layer 414 from each other.

[0051] As shown in FIG. 4, the semiconductor device 400 further includes a top-level metallization layer 420, which can be a patterned metallization layer that includes a portion 420a and a portion 420b. As with the corrosion-prevention implant 122 of the apparatus 100 and the corrosion-prevention implant 222 of the apparatus 200, the portion 420a and the portion 420b of the top-level metallization layer 420 include a corrosion-prevention implant 422 that is disposed (e.g., using a blanket implant) along an entirety of a surface 421a of the portion 420a, and an entirety of a surface 421b of the portion 420b (e.g., using a blanket implant). In this example, the corrosion-prevention implant 422 is formed through the surface 421a and the surface 421b of the top-level metallization layer 420. The semiconductor device 400 in FIG. 4 further includes a passivation layer 450 that can protect the underlying structure of the semiconductor device 400. The passivation layer 450, as shown in FIG. 4, is patterned (e.g., using photolithography and etch processes) to expose a portion of the surface 421a of the top-level metallization layer 420, which can be used for coupling an electrical connector (not shown) with the semiconductor device 400.

[0052] As with the corrosion-prevention implants of FIGS. 1-3, in implementations, the corrosion-prevention implant 422 includes one or more materials that inhibit corrosion of the top-level metallization layer 420. The particular materials included in the corrosion-prevention implant 422 can depend, at least in part, on the composition of the top-level metallization layer. For instance, in some implementations, the top-level metallization layer can include one or more of Cu, AlCu, TiNiCu, or TiNiAg, though other metals can be used. In some implementations, the corrosion-prevention implant 422 can include Al, Mg and/or N, e.g., implanted as ions. In some implementations, the corrosion-prevention implant 422 can include other substances.

[0053] Also, as with the corrosion-prevention implants of FIGS. 1-3, the corrosion-prevention implant 422 can be formed using an ion beam with an energy and ion dose that is appropriate for the particular implementation. For example, the implantation energy and dose can depend on the composition of the top-level metallization layer 420 and/or on a process used to produce the top-level metallization layer 420, e.g., sputtering, plating, etc. In some implementations, the top-level metallization layer 420 can have a thickness consistent with the ranges described with respect to the metallization layer 120, and the corrosion-prevention implant 422 can have a depth consistent with ranges described above with respect to the corrosion-prevention implant 122.

[0054] FIGS. 5 and 6 are flowcharts illustrating, respectively, methods 500 and 600, which include example semiconductor processing operations that can be used to produce the implementations described herein. The operations shown in FIGS. 5 and 6 are given be way of example and can be implemented in conjunction with other operations of a semiconductor manufacturing process. In some implementations, one or more operations of the approaches shown in FIGS. 5 and 6 can used for producing, e.g., a DBM substrate with a corrosion-prevention implant.

[0055] Referring to FIG. 5, the method 500, which can be implemented after performing other semiconductor processing operations (e.g., operations to produce active circuitry), at block 510, includes forming a barrier metal layer and, at block 520, includes forming a metallization layer (e.g., the metallization layer 120, the metallization layer 220, the metallization layer 320, the top-level metallization layer 420, etc.) that is disposed on the barrier metal layer. The barrier metal layer can prevent unwanted interaction (e.g., spiking and/or material migration) between the metallization layer of block 520 and layers of a semiconductor device underlying the barrier metal.

[0056] At block 530, the method 500 includes performing a corrosion-prevention implant on the metallization layer of block 520, which can be a blanket implant, such as described herein. At block 540, the method 500 includes forming a passivation layer, such as the passivation layer 450 of FIG. 4. At block 550, the method includes performing a back grind, e.g., to thin a corresponding semiconductor wafer to a desired thickness, and applying a metal layer (back metal) to the ground surface, where the back metal layer facilitates electrical connection with the back side of the semiconductor wafer. The method can then proceed to block 560, where the semiconductor wafer is used for assembling individual semiconductor devices, e.g., by dicing the wafer into individual die for use in respective semiconductor device assemblies. The assembly process at block 560 can include coupling electrical connectors (e.g., bond wires, conductive clips, solder balls, etc.) with exposed portions of the metallization layer of block 520 that include the corrosion-prevention implant of block 530.

[0057] Referring to FIG. 6, the method 600, as with the method 500, can be implemented after performing other semiconductor processing operations (e.g., operations to produce active circuitry). At block 610, the method 600 includes forming a barrier metal layer and, at block 620, includes forming a metallization layer (e.g., an underlying metallization layer). At block 630, the method 600 includes forming a passivation layer, such as those described herein, and at block 640 includes forming a metallization layer (e.g., a top level metallization layer). The metallization layer of block 640 can be bond pad metallization, or metallization of a redistribution layer, as two examples.

[0058] At block 650, the method 600 includes performing a corrosion-prevention implant on the metallization layer of block 640. At block 660, the method includes performing a back grind and back metal process, such as described with respect to FIG. 5. The method 600 can then proceed to block 670, where the semiconductor wafer is used for assembling individual semiconductor devices, e.g., by dicing the wafer into individual die. The assembly process at block 670 can include coupling electrical connectors (e.g., bond wires, conductive clips, solder balls, etc.) with exposed portions of the metallization layer of block 640 that include the corrosion-prevention implant of block 650.

[0059] It will be understood that, in the foregoing description, when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.

[0060] As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, top, bottom, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

[0061] Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Silicon Carbide (SiC), Gallium Arsenide (GaAs), Gallium Nitride (GaN), and/or so forth. Some implementations may be implemented using various types of semiconductor assemblies, such as assemblies include substrates including, but not limited to, direct-bonded metal (DBM) substrates.

[0062] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.