Method and apparatus for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs)

Abstract

An apparatus and method are provided for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs) caused by the effects of aging on the power transistors of the DLDO, such as by the effects of negative bias temperature instability (NBTI)-induced aging, for example. The apparatus comprises a shift register for use in a DLDO that is configured to activate and deactivate power transistors of the DLDO to evenly distribute electrical stress among the transistors in a way that mitigates performance degradation of the DLDO under various load current conditions. In addition, the shift register and methodology can be implemented in such a way that nearly no extra power and area overhead are consumed.

Claims

1. A digital low-dropout voltage regulator (DLDO) having a configuration that mitigates performance degradation of the DLDO caused by effects of aging on power transistors of the DLDO, the DLDO comprising: a clocked comparator circuit having at least first and second input terminals and an output terminal, the first terminal receiving a reference voltage V.sub.ref, the second input terminal receiving an output voltage signal V.sub.out output from an output voltage terminal of the DLDO, the comparator comparing the reference voltage signal with the output voltage signal and outputting a comparator output voltage signal, V.sub.cmp; an array of N power transistors electrically connected in parallel with one another, where N is a positive integer that is greater than or equal to one, each power transistor having first, second and third terminals, the first terminal of each power transistor being electrically coupled to the output voltage terminal of the DLDO; and a digital controller comprising control logic configured to activate and deactivate the power transistors of the DLDO in accordance with a preselected activation/deactivation control scheme that causes the power transistors to be turned ON or OFF, wherein the preselected activation/deactivation control scheme ensures that the power transistors are turned ON or OFF in a way that evenly distributes electrical stress among the power transistors over time to thereby mitigate performance degradation of the DLDO caused by the effects of aging on the power transistors, the second terminal of each power transistor being electrically coupled to a respective output terminal of the digital controller for receiving a respective one of the control signals from the digital controller.

2. The DLDO of claim 1, wherein the control logic comprises a uni-directional shift register.

3. The DLDO of claim 2, wherein the control signals turn the power transistors ON or OFF in such a way that the power transistors are substantially evenly utilized over time to mitigate performance degradation of the DLDO.

4. The DLDO of claim 2, wherein the control signals turn an inactive power transistor at a right boundary of active and inactive power transistors ON if V.sub.cmp is a logic high and turn an active power transistor at a left boundary of active and inactive power transistors OFF if V.sub.cmp is a logic low.

5. The DLDO of claim 4, wherein the control logic further comprises N combinations of logic gates and wherein the shift register comprises N flip flops, each flip flop having a first input terminal that is electrically coupled to an output terminal of one of the N combinations of logic gates, each of the N combinations of logic gates processing the comparator output voltage signal, V.sub.cmp, and a respective pair of control signals output from a respective pair of adjacent output terminals of the digital controller, and wherein a combination of the processes performed by the N combinations of logic gates and the respective flip flops result in the control logic (1) locating the left and right boundaries, (2) turning ON an inactive power transistor at the right boundary if V.sub.cmp is a logic high, and (3) turning OFF an active power transistor at the left boundary if V.sub.cmp is a logic low.

6. The apparatus of claim 1, wherein the power transistors are p-type metal oxide semiconductor field effect (pMOS) transistors.

7. The apparatus of claim 6, wherein the effects of aging on the power transistors are caused, at least in part, by negative bias temperature instability (NBTI).

8. The apparatus of claim 1, wherein the power transistors are n-type metal oxide semiconductor field effect (nmos) transistors.

9. The apparatus of claim 8, wherein the effects of aging on the power transistors are caused, at least in part, by positive bias temperature instability (PBTI).

10. A method for mitigating performance degradation in a digital low-dropout voltage regulator (DLDO) caused by effects of aging on power transistors, the method comprising: in a clocked comparator of the DLDO, receiving a reference voltage signal, V.sub.ref, at a first input terminal of the clocked comparator, receiving an output voltage signal, V.sub.out, output from an output voltage terminal of the DLDO at a second input terminal of the clocked comparator, and receiving a DLDO clock signal, clk, at a clock terminal of the clocked comparator; in the clocked comparator, comparing the reference voltage signal, V.sub.ref, with the output voltage signal, V.sub.out, and outputting a comparator output voltage, V.sub.cmp; and in a digital controller of the DLDO, receiving the comparator output voltage, V.sub.cmp, at an input terminal of the digital controller and performing a preselected activation/deactivation control scheme that causes the digital controller to send control signals to an array of power transistors of the DLDO to cause the power transistors to be turned ON or OFF in accordance with the preselected activation/deactivation control scheme, wherein the preselected activation/deactivation control scheme ensures that the power transistors are turned ON or OFF in a way that evenly distribute electrical stress among the power transistors over time to thereby mitigate performance degradation of the DLDO caused by the effects of aging on the power transistors, each power transistor having first, second and third terminals, the first terminal of each power transistor being electrically coupled to the output voltage terminal of the DLDO, the second terminal of each power transistor being electrically coupled to one of the output terminals of the digital controller for receiving one of the control signals from the digital controller.

11. The method of claim 10, wherein the DLDO comprises control logic configured to perform the preselected activation/deactivation control scheme, the control logic comprising a uni-directional shift register.

12. The method of claim 11, wherein the control signals turn the power transistors ON or OFF in such in a way that the power transistors are substantially evenly utilized over time to mitigate performance degradation of the DLDO caused by the effects of aging on the power transistors.

13. The method of claim 11, wherein the control signals turn an inactive power transistor at a right boundary of active and inactive power transistors ON if V.sub.cmp is a logic high and turn an active power transistor at a left boundary of active and inactive power transistors OFF if V.sub.cmp is a logic low.

14. The method of claim 13, wherein the control logic further comprises N combinations of logic gates and wherein the shift register comprises N flip flops, each flip flop having a first input terminal that is electrically coupled to an output terminal of one of the N combinations of logic gates, the method further comprising: with each of the N combinations of logic gates, processing the comparator output voltage signal, V.sub.cmp, and a respective pair of control signals output from a respective pair of adjacent output terminals of the digital controller, and wherein a combination of the processes performed by the N combinations of logic gates and the respective flip flops result in the control logic (1) locating the left and right boundaries, (2) turning ON an inactive power transistor at the right boundary if V.sub.cmp is a logic high, and (3) turning OFF an active power transistor at the left boundary if V.sub.cmp is a logic low.

15. The method of claim 10, wherein the power transistors are p-type metal oxide semiconductor field effect (pMOS) transistors.

16. The method of claim 15, wherein the effects of aging on the power transistors are caused, at least in part, by negative bias temperature instability (NBTI).

17. The method of claim 10, wherein the power transistors are n-type metal oxide semiconductor field effect (nmos) transistors.

18. The method of claim 17, wherein the effects of aging on the power transistors are caused, at least in part, by positive bias temperature instability (PBTI).

19. A method for mitigating performance degradation in a digital low-dropout voltage regulator (DLDO) caused by the effects of aging on power transistors of the DLDO, the method comprising: with shift register of a digital controller of the DLDO, outputting control signals that cause power transistors of the DLDO to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme, wherein the preselected activation/deactivation control scheme ensures that the power transistors are turned ON or OFF in a way that evenly distributes electrical stress among the power transistors over time to thereby mitigate performance degradation of the DLDO caused by the effects of aging on the power transistors.

20. The method of claim 19, wherein the shift register is a uni-directional shift register, and wherein the control signals turn an inactive power transistor at a right boundary of active and inactive power transistors ON if V.sub.cmp is a logic high and turn an active power transistor at a left boundary of active and inactive power transistors OFF if V.sub.cmp is a logic low.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The example embodiments are best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that the various features are not necessarily drawn to scale. In fact, the dimensions may be arbitrarily increased or decreased for clarity of discussion. Wherever applicable and practical, like reference numerals refer to like elements.

(2) FIG. 1 is a schematic diagram of a conventional DLDO.

(3) FIG. 2 is a bi-directional shift register comprising the digital controller of the conventional DLDO shown in FIG. 1.

(4) FIG. 3 is a diagram showing the operation of the bi-directional shift register shown in FIG. 2.

(5) FIG. 4 is a graph showing the percentage of I.sub.pMOS degradation over time of a DLDO of the type shown in FIG. 1 that uses a bi-directional shift register of the type shown in FIG. 2.

(6) FIG. 5 is a schematic diagram of an aging-aware (A-A) DLDO in accordance with a representative embodiment.

(7) FIG. 6 is a schematic diagram of a uni-directional shift register of the A-A DLDO shown in FIG. 5 in accordance with a representative embodiment.

(8) FIG. 7 is a diagram showing the operation of the uni-directional shift register shown in FIG. 6 in accordance with a representative embodiment.

(9) FIG. 8 is a timing diagram that represents simulated steady-state gate signals of power transistors with bDSR control as shown in FIG. 2.

(10) FIG. 9 is a timing diagram that represents simulated steady-state gate signals of bower transistors with uDSR control as shown in FIG. 7.

(11) FIG. 10 is a timing diagram demonstrating bDSR control and uDSR control in accordance with FIGS. 8 and 9, respectively, for particular gate signals.

(12) FIG. 11 is a timing diagram that conceptually illustrates transient waveforms and active power transistor locations for the DLDO shown in FIG. 5.

(13) FIG. 12 is a table listing technology and architecture parameters for a simulation that was performed to demonstrate benefits of employing the uni-directional shift register configuration shown in FIG. 6 in a DLDO.

(14) FIG. 13 is a schematic diagram of the functional blocks of one core within an IBM POWER8 like microprocessor chip used in the simulation defined by the architectural parameters listed in the table of FIG. 12.

(15) FIG. 14 is a table listing load characteristics of the different functional blocks shown in FIG. 13 under experimented benchmarks.

(16) FIG. 15 is a table listing simulation results for conventional DLDO performance degradation for different functional blocks shown in FIG. 12 under experimented benchmarks for a five-year time frame.

DETAILED DESCRIPTION

(17) The present disclosure discloses a DLDO having a configuration that mitigates performance degradation caused by the effects of aging on power transistors of the DLDO. In accordance with an embodiment, the apparatus comprises a digital controller comprising a shift register that is configured to activate and deactivate power transistors of the DLDO to evenly distribute electrical stress among the transistors over time in a way that mitigates performance degradation of the DLDO under various load current conditions.

(18) In the following detailed description, for purposes of explanation and not limitation, exemplary, or representative, embodiments disclosing specific details are set forth in order to provide a thorough understanding of inventive principles and concepts. However, it will be apparent to one of ordinary skill in the art having the benefit of the present disclosure that other embodiments according to the present teachings that are not explicitly described or shown herein are within the scope of the appended claims. Moreover, descriptions of well-known apparatuses and methods may be omitted so as not to obscure the description of the exemplary embodiments. Such methods and apparatuses are clearly within the scope of the present teachings, as will be understood by those of skill in the art. It should also be understood that the word “example,” as used herein, is intended to be non-exclusionary and non-limiting in nature.

(19) The terminology used herein is for purposes of describing particular embodiments only, and is not intended to be limiting. The defined terms are in addition to the technical, scientific, or ordinary meanings of the defined terms as commonly understood and accepted in the relevant context.

(20) The terms “a,” “an” and “the” include both singular and plural referents, unless the context clearly dictates otherwise. Thus, for example, “a device” includes one device and plural devices. The terms “substantial” or “substantially” mean to within acceptable limits or degrees acceptable to those of skill in the art. The term “approximately” means to within an acceptable limit or amount to one of ordinary skill in the art.

(21) As an essential part of large scale integrated circuits, on-chip voltage regulators need to be active most of the time to provide the required power to the load circuit. The load current and temperature can vary quite a bit, especially for microprocessor applications. These variations partially contribute to different aging mechanisms of on-chip voltage regulators, which should be considered to avoid overdesign for a targeted lifetime. Additionally, in certain processor components that can show higher degrees of tolerance to errors, the regulators can be intentionally under-designed to save valuable chip area and potentially power-conversion efficiency. In other words, a heterogeneous distributed power delivery network can be designed comprising different DLDOs including accurate DLDOs that house additional circuitry to mitigate the aging-induced supply voltage variations and approximate DLDOs that are intentionally under-designed to mitigate, just enough, aging-induced variations. The quality of the supply voltage directly affects the data path delay and signal quality, and fluctuations in the supply voltage result in delay uncertainty and clock jitter. According to one aspect of the present disclosure, the supply noise tolerance of certain processor components is used as an “area quality control knob” that compromises the quality of the supply voltage to save valuable chip area.

(22) Several studies have been performed regarding the reliability issues in nanometer CMOS designs. To date, only a limited amount of work has been done on the reliability of on-chip voltage regulators. To this end, the present disclosure provides a quantitative analysis of aging effects on on-chip voltage regulators considering load current characteristics and temperature variations as well as efficient reliability enhancement techniques under arbitrary load conditions.

(23) As compared to other voltage regulator types, the emerging DLDO has gained impetus due to the design simplicity, easiness for integration, high power density, and fast response. DLDOs have demonstrated major advantages in modern processors including the recent IBM POWER8 processor. More importantly, as compared to the analog LDOs, a DLDO can provide certain advantages for low-power and low-voltage IoT applications due to its capability for low supply voltage operations. However, as pMOS is used as the power transistor for DLDOs, NBTI-induced degradations largely affect important performance metrics such as the maximum output current capability I.sub.max, load response time T.sub.R, and magnitude of the droop ΔV.

(24) The present disclosure is organized as follows. Background information regarding the conventional DLDO shown in FIG. 1 is introduced in Section I. NBTI-induced DLDO regulator performance degradation including I.sub.max, T.sub.R, and ΔV is demonstrated theoretically in Section II. A representative embodiment of an aging-aware (A-A) DLDO in accordance with the inventive principles and concepts is described in Section III. A benefits evaluation of the A-A DLDO through simulation of an IBM POWER8 like processor is provided in Section IV. Concluding remarks are offered in Section V.

Section I

(25) A. Negative Bias Temperature Instability

(26) NBTI can introduce significant V.sub.th degradations to pMOS transistors due to negatively applied gate to source voltage V.sub.gs. The increase in |V.sub.th| due to NBTI is considered to be related to the generation of interface traps at the Si/SiO2 interface when there is a gate voltage. |V.sub.th| increases when electrical stress is applied and partially recovers when stress is removed. This process is commonly explained using a reaction-diffusion (R-D) model. The V.sub.th degradation can be estimated during each stress and recovery phase using a cycle-to-cycle model and can also be evaluated using a long-term reliability model. As the long-term reliability evaluation is the focus of this work, the analytical model for long-term worst case threshold voltage degradation ΔV.sub.th estimation can be expressed as:

(27) $\begin{array}{cc}\Delta V_{th}=K_{lt}\sqrt{C_{ox}\left(.Math.V_{gs}.Math.-.Math.V_{th}.Math.\right)}{e^{\frac{-E_a}{kT}}\left(\alpha t\right)}^{\frac{1}{6}}& \left(1\right)\end{array}$
where C.sub.ox, k, T, α, and t are, respectively, the oxide capacitance, Boltzmann constant, temperature, the fraction of time (activity factor) when the device is under stress, and operation time. K.sub.lt and E.sub.a are the fitting parameters to match the model with the experimental data. Note that NBTI recovery phase is already included in the model.

Section II. Aging-Induced DLDO Performance Degradation

(28) I.sub.max, T.sub.R, and ΔV are among the most important design parameters for DLDOs. The effect of NBTI-induced degradations on these important performance metrics is examined in this section.

(29) A. Maximum Current Supply Capability

(30) Without NBTI induced degradations, I.sub.max=NI.sub.pMOS, where I.sub.pMOS is the maximum output current of a single pMOS stage. For the DLDO, |V.sub.gs| in Equation (1) is equal to V.sub.in when M.sub.i is active. The pMOS transistor M.sub.i operates in linear region when turned on and the on-resistance R.sub.on of a single pMOS stage can be approximated as:
R.sub.on≈[(W/L)/μ.sub.pC.sub.ox(V.sub.in−|V.sub.th|)].sup.−1  (2)
where W, L, μ.sub.p, and C.sub.ox are, respectively, the width, length, mobility, and oxide capacitance of M.sub.i. I.sub.pMOS can thus be expressed as:

(31) $\begin{array}{cc}{I}_{pMOS}=\frac{V_{sd}}{R_{on}}=\left(V_{in}-V_{out}\right)\left(W/L\right){\mu }_p{C}_{ox}\left(V_{in}-.Math.V_{th}.Math.\right)& \left(3\right)\end{array}$
where V.sub.sd is the source drain voltage of M.sub.i. NBTI induced degradation factor DF.sub.i for M.sub.i can be defined as:

(32) $\begin{array}{cc}D{F}_i=\frac{I_{{\mathrm{pMOS}}_i}^{deg}}{I_{\mathrm{pMOS}}}=\frac{V_{in}-.Math.V_{th}.Math.-\Delta V_{t{h}_i}}{V_{in}-.Math.V_{th}.Math.}& \left(4\right)\end{array}$
where ΔV.sub.th.sub.i and I.sub.pMOS.sub.i.sup.deg are, respectively, NBTI induced V.sub.th degradation and the degraded I.sub.pMOS for M.sub.i. Degraded I.sub.max can be expressed as:
I.sub.max.sup.deg=I.sub.pMOSΣ.sub.i=1.sup.NDF.sub.i.  (5)

(33) FIG. 4 is a plot showing percentage I.sub.pMOS, T.sub.R, and ΔV degradation for bDSR-based DLDOs of the type shown in FIG. 1 for different temperatures. Curves 11-13 correspond to I.sub.pMOS, T.sub.R and ΔV, degradation, respectively, for 27° C. Curves 14-16 correspond to I.sub.pMOS, T.sub.R and ΔV, degradation, respectively, for 75° C. Curves 17-19 correspond to I.sub.pMOS, T.sub.R and ΔV, degradation, respectively, for 125° C. As an example, the percentage I.sub.pMOS degradation 1−DF.sub.i for a smaller value of i, considering M.sub.i is active most of the time, is shown in FIG. 4 as a function of time under different temperatures. Equations (1) and (4) are leveraged for evaluation, where transistor model parameters are adopted from a 32-nm metal gate, high-k strained-Si CMOS technology within the predictive technology model (PTM) model library. A supply voltage V.sub.in=1.1 V is used for estimation. PTM is adopted for the aging-induced deterioration analysis and subsequent DLDO simulations as it is widely used for BTI study due to the availability of fitting parameter values in the ΔV.sub.th degradation model. As shown in FIG. 4, NBTI can induce significant I.sub.pMOS degradations, especially at high temperatures. Also, most degradation occurs in the first two years. Beyond two years, the degradation typically plateaus to within 10%. Degraded I.sub.pMOS can further lead to reduced I.sub.max and lower output voltage regulation capability under high load current. Moreover, as discussed in Sections II-B and II-C, degraded I.sub.pMOS also exacerbates T.sub.R and ΔV, necessitating reliability enhancement techniques.

(34) B. Load Response Time

(35) Load response time T.sub.R measures how fast the feedback loop responds to a step load. T.sub.R can be estimated as:

(36) $\begin{array}{cc}{T}_R=\mathrm{RC}\ln \left(1+\frac{\Delta i_{load}}{I_{\mathrm{pMOS}}{f}_{\mathrm{clk}}\mathrm{RC}}\right)& \left(6\right)\end{array}$
where R, C, f.sub.clk, and Δi.sub.load are, respectively, the average DLDO output resistance before and after Δi.sub.load, load capacitance, clock frequency, and amplitude of the load change. Considering NBTI effect, degraded T.sub.R can be expressed as:

(37) $\begin{array}{cc}{T}_R^{deg}=\mathrm{RC}\ln \left(1+\frac{\Delta i_{load}}{{\mathrm{DFI}}_{\mathrm{pMOS}}{f}_{\mathrm{clk}}\mathrm{RC}}\right).& \left(7\right)\end{array}$
As 0<DF<1 and T.sub.R<T.sub.R.sup.deg, NBTI induced degradation slows down DLDO response.
C. Magnitude of the Droop

(38) Magnitude of the droop ΔV reflects the V.sub.out noise profile under transient response and can be estimated as:

(39) $\begin{array}{cc}\Delta V=R\Delta i_{\mathrm{load}}-I_{pMOS}{f}_{\mathrm{clk}}{R}^{2}C\ln \left(1+\frac{\Delta i_{load}}{I_{\mathrm{pMOS}}{f}_{\mathrm{clk}}\mathrm{RC}}\right).& \left(8\right)\end{array}$
Considering NBTI effect, degraded ΔV can be expressed as:

(40) $\begin{array}{cc}\Delta V_{deg}=R\Delta i_{\mathrm{load}}-{\mathrm{DFI}}_{pMOS}{f}_{\mathrm{clk}}{R}^{2}C\ln \left(1+\frac{\Delta i_{load}}{{\mathrm{DFI}}_{\mathrm{pMOS}}{f}_{\mathrm{clk}}\mathrm{RC}}\right).& \left(9\right)\end{array}$
Let Δi.sub.load/I.sub.pMOSf.sub.clkRC=A, A>0. Under 0<DF<1, the following holds:

(41) $\begin{array}{cc}1+A>{\left(1+\frac{A}{DF}\right)}^{DF}& \left(10\right)\end{array}$

(42) $\begin{array}{cc}{I}_{pMOS}{f}_{clk}{R}^{2}C\ln \left(1+\frac{\Delta i_{\mathrm{load}}}{I_{\mathrm{pMOS}}{f}_{\mathrm{clk}}\mathrm{RC}}\right)>{\mathrm{DFI}}_{pMOS}{f}_{\mathrm{clk}}{R}^{2}C\ln \left(1+\frac{\Delta i_{load}}{{\mathrm{DFI}}_{\mathrm{pMOS}}{f}_{\mathrm{clk}}\mathrm{RC}}\right)& \left(11\right)\end{array}$
and ΔV<ΔV.sub.deg, which means NBTI can degrade the transient voltage noise profile.

Section III. Aging-Aware (A-A) DLDO

(43) Considering the side effects of power transistor array and control loop degradations, a representative embodiment of an A-A DLDO 100 is shown in FIG. 5. The A-A DLDO 100 employs a unidirectional shift register (uDSR) 110 to mitigate, respectively, I.sub.pMOS, T.sub.R, and ΔV degradation. The uDSR 110 is described below in detail in section III-A. Power and area OH of the proposed technique as well as compatibility analysis are provided in Section III-B.

(44) N parallel pMOS power transistors M.sub.i (i=1, . . . , N) of the DLDO 100 are connected between the input voltage V.sub.in and output voltage V.sub.out, and a feedback control loop is implemented with a clocked comparator 101 and the uDSR 110, which operates as the digital controller of the DLDO 100. The value of V.sub.out and reference voltage V.sub.ref are compared through the comparator 101 at the rising edge of the clock signal clk. The power transistors M.sub.i are turned on or off in the manner described below with reference to FIGS. 6 and 7.

(45) A. Unidirectional Shift Register

(46) To mitigate NBTI-induced I.sub.pMOS, T.sub.R and ΔV degradations, distributing the electrical stress among all available power transistors as evenly as possible under arbitrary load current conditions is desirable. Reliability is generally not considered in conventional bDSR-based DLDO designs of the type shown in FIG. 1, and therefore too much stress is exerted on a small portion of M.sub.is. A representative embodiment of the uDSR is disclosed herein that evenly distributes the electrical stress among all of the M.sub.is to realize an A-A DLDO with enhanced reliability.

(47) FIG. 6 shows a schematic diagram of the uDSR 110 in accordance with a representative embodiment. FIG. 7 is a diagram showing the manner in which the uDSR 110 operates in accordance with a representative embodiment. In accordance with this representative embodiment, the elementary D flip-flops (DFFs) and the multiplexer within the bDSR shown in FIG. 2 are replaced with T flip-flops (TFFs) 111.sub.1-111.sub.N and a simple combination of logic gates 112.sub.1-112.sub.N within the uDSR 110, respectively. The rest of the DLDO 100, including the parallel power transistors M.sub.is and the clocked comparator 101 can remain unchanged. One of the objectives here is to balance the utilization of each available M.sub.i under all load current conditions. To achieve this objective, control signals Q.sub.i-1 and Q.sub.i for two adjacent power transistors M.sub.i-1 and M.sub.i, respectively, are XORed to determine if M.sub.i-1 and M.sub.i are at the boundary of active and inactive power transistor portions. Normally, there are two such boundaries if at least one power transistor is active, as shown in FIG. 7. Q.sub.i-1 and output of the comparator V.sub.cmp are thus XORed by the combinations of logic gates 112.sub.1-112.sub.N to decide which power transistor at the boundaries needs to be turned on/off at the rising edge of the clock signal.

(48) An inactive power transistor at the right boundary is turned on if V.sub.cmp is logic high. An active power transistor at the left boundary is turned off if V.sub.cmp is logic low. The uDSR 110 is realized through this activation/deactivation scheme, as demonstrated in FIG. 7. Q.sub.i-1 for the first stage is Q.sub.N from the last stage and thus a loop is formed. Considering the initialization step when all M.sub.is are off and the full load current condition when all M.sub.is are on, additional control signals are inserted as T.sub.b and T.sub.c in the first stage at the combination of logic gates 112.sub.1, to avoid inaction under these two situations, where T.sub.b=Q.sub.1.Math.Q.sub.2 . . . Q.sub.N.Math.V.sub.amp and T.sub.c=Q.sub.1+Q.sub.2+ . . . +Q.sub.N+V.sub.cmp. The logic functions for T.sub.b and T.sub.c can be implemented with n-input AND/NOR gates, for example, as shown in FIG. 6, although other logic gate configurations could be used for this purpose.

(49) 1. Steady-State Operation

(50) FIGS. 8 and 9 are timing diagrams that represent simulated steady-state gate signals of power transistors with bDSR and uDSR control, respectively, where Q.sub.a (1≤a<I.sub.loadN/I.sub.max−M) and Q.sub.b (I.sub.loadN/I.sub.max+M<b≤N) are, respectively, gate signal of active power transistor Ala and inactive power transistor Mb with bDSR control. Q.sub.is (1≤i≤N) all have similar waveforms with uDSR control. For the simulations shown in FIGS. 8 and 9, I.sub.load=300 mA. The detailed design specifications for the DLDO 100 are described in Section IV-A. As shown in FIG. 8, for bDSR control, power transistor M.sub.as experience electrical stress all of the time while power transistors M.sub.bs are always OFF. FIG. 10 is a timing diagram demonstrating bDSR control and uDSR control in accordance with FIGS. 8 and 9, respectively, for particular gate signals. For uDSR control, three randomly picked adjacent power transistor gate signals Q.sub.59, Q.sub.60, and Q.sub.61 together with two additional further separated gate signals Q.sub.20 and Q.sub.120 are demonstrated. The falling edge of Q.sub.60 (Q.sub.61) demonstrates delay as compared to Q.sub.59 (Q.sub.60). However, the percentage of time when power transistor M.sub.i (1≤i≤N) is active is the same for all M.sub.is, and thus, the electrical stress can be more evenly distributed.

(51) 2. Transient Load Operation

(52) FIG. 11 is a timing diagram that conceptually illustrates transient waveforms and active power transistor locations for the DLDO 100. The operation of uDSR 110 under transient load conditions will be elaborated on with reference to FIG. 11. A step load current with a few clock cycles of rise and fall time is utilized for illustration. Assume at t.sub.1 before the load increase, there are three active power transistors on the left side of the power transistor array, the deactivation of power transistor at the left boundary at the next clock rising edge, and the activation of power transistor at the right boundary at the following clock rising edge lead to the updated active power transistor locations at t.sub.2. The number of active power transistors continues to increase after t.sub.2 and due to the steady-state operation of the uDSR, active power transistors with an increased number move right to reach the new locations at t.sub.3. After experiencing one more activation and deactivation of power transistors due to load decrease, the updated locations at t.sub.4 (the second clock rising edge after t.sub.3) are demonstrated at the bottom in FIG. 11.

(53) Thus, regardless of the load current conditions, electrical stress can always be more evenly distributed among all of the available power transistors of the DLDO 100. Furthermore, as compared to the conventional bDSR-based DLDO 2, the number of activated/deactivated power transistors per clock cycle remains the same, and thus, bDSR and uDSR have the same transfer function S(z). Leveraging uDSR to evenly distribute electrical stress within the power transistor array does not negatively affect control loop performance.

(54) B.1 Overhead

(55) Considering the similar area of DFFs and TFFs, the uDSR 110 only induces ˜3.8% area OH per control stage compared to the bDSR 5. The total area OH is −2.6% of a single active DLDO area designed with μA current supply capability. As few extra transistors are added per control stage and the bDSR 5 only consumes a few μW power, the uDSR-induced power OH is also negligible. With a larger I.sub.pMOS for higher load current rating, both the area and power OH can be significantly less.

(56) B.2 Compatibility with Quiescent Current Saving Technique

(57) In accordance with a representative embodiment, known freeze mode operation and clock gating techniques are employed in the DLDO 100 to save quiescent current at steady state. For freeze mode operation, the DLDO control circuit can be disabled once the number of active power transistors converges to save the quiescent current. In this case, the operation of the uDSR 110 would also be stopped. However, after many load current changes and different steady-state operations for long-term reliability concern, the active power transistor region (darkened region shown in FIG. 7) still moves rightward and electrical stress can also be more evenly distributed among all of the power transistors as compared to the conventional bidirectional shift method.

(58) Furthermore, in accordance with an embodiment, a known sliding clock gating technique can also be utilized to save the steady-state quiescent current. For this purpose, the power transistor array and the control flip-flops 111.sub.1-111.sub.N are divided into multiple sections with equal number within each section. During steady-state operation, if the left boundary of the active power transistor region falls within one section and the right boundary falls within another section, other sections not covering the two boundaries can be temporarily clock gated to save quiescent current. The active power transistor region still dynamically moves rightward to evenly distribute the electrical stress and the clock-gated sections also dynamically change. For this case, as not all flip-flops are clock gated, the steady-state quiescent current can be higher than that in the freeze mode operation discussed earlier. Thus, the unidirectional shift scheme is still beneficial even when a steady-state quiescent current saving technique is employed. However, a tradeoff exists between the steady-state quiescent current saving and reliability enhancement enabled by the unidirectional shift scheme.

Section IV. Evaluation

(59) To evaluate the benefits of the proposed A-A DLDO architecture in terms of reliability enhancement and to provide design insights for a targeted lifetime, an IBM POWER8 like microprocessor simulation platform is constructed.

(60) A. 1 Simulation Framework

(61) An IBM POWER8 Like Microprocessor was used for the simulation framework. The IBM POWER8 microprocessor is currently among one of the state-of-the-art server-class processors and, thus, a representative for evaluation of the proposed A-A DLDO design scheme. FIG. 12 contains Table I, which lists the corresponding technology and architecture parameters. FIG. 13 is a block diagram of the IBM POWER8 like microprocessor core, which includes a load store unit (LSU), an execution unit (EXU), an instruction fetch unit (IFU), an instruction scheduling unit (ISU), an L1 data cache inside LSU, an L1 instruction cache inside IFU, and a private L2. All benchmarks are from SPALSH2x and cover a wide range of representative application domains. Analysis is restricted to the region of interest of the benchmarks and eight threads are involved in the simulations. Table II shown in FIG. 14 is a summary of the load characteristics of different functional blocks under all experimented benchmarks.

(62) A.2 DLDO Design Specifications

(63) Distributed microregulators are implemented in IBM POWER8 microprocessor. In this simulation example, a switch array of 256 pMOS transistors, which is typical in DLDO designs, is implemented in each microregulator. Two different DLDO designs with bDSR and uDSR controls are implemented using 32-nm PTM CMOS technology where V.sub.in=1.1V and V.sub.out=1V. In the simulation, I.sub.pMOS=2 mA and I.sub.max=512 mA are used, leading to 7, 24, 3, 10, and 5 microregulators (DLDOs) in the, respectively, IFU, LSU, ISU, EXU, and L2 blocks shown in FIG. 13 to be able to supply the maximum load current across all benchmarks in each block. Load current of each block is assumed to be supplied by microregulators within that block, which is reasonable due to the principle of spatial locality regarding current distribution. Each microregulator within a certain block is assumed to provide equal current due to the availability of current balancing scheme implemented within IBM POWER8 microprocessor. In the simulation, f.sub.clk=10 MHz and C=15 nF are used for each DLDO to achieve smaller than 10% Vdd transient voltage noise most of the time. The total output capacitance is 735 nF. As resonant clock meshes are already deployed within IBM POWER8 processor, the complexity and OH of generating and distributing the clock signal for the DLDOs can be frequency dividers consisting of simple flip-flops and localized routing wires.

(64) A. 3 Evaluation of Aging-Induced Performance Degradation

(65) Equations (1), (3), (6), and (8) are leveraged for the evaluation of aging-induced performance degradation. A typical temperature profile of 90° C., 69° C., 67° C., 63° C., and 62° C. for, respectively, LSU, EXU, IFU, ISU, and L2 is adopted for evaluations. The activity factors for both DLDO designs under different benchmarks and functional blocks are estimated through simulations in Cadence Virtuoso. The worst case I.sub.pMOS degradations are used for evaluations of both designs, which is reasonable due to load characteristics of typical applications and the consequent heavy use of a portion of Ms in conventional DLDOs.

(66) B. 1 Simulation Results: Performance Degradation Within Conventional DLDO

(67) Table III shown in FIG. 15 lists a summary of the conventional DLDO performance degradation regarding I.sub.pMOS, T.sub.R, and ΔV for different functional blocks for a 5-year time frame. These degradations apply to all the experimented benchmarks as the worst case I.sub.pMOS degradation is considered. As shown in Table III, NBTI can induce serious I.sub.pMOS, T.sub.R, and ΔV degradations for all functional blocks. I.sub.pMOS degradation can lead to the deterioration of DLDO V.sub.out regulation capability and possible V.sub.out drop under large load current conditions. Larger than 10% V.sub.out drop can lead to voltage emergencies and potential execution errors for microprocessors. Similarly, T.sub.R and ΔV degradations can, respectively, increase the duration and frequency of voltage emergencies, which can slow down microprocessor executions as further actions may need to be taken to remedy the errors. Moreover, for a longer targeted lifetime of more than 5 years, the degradations are expected to be more disastrous, as I.sub.pMOS degradations are even worse, as seen from FIG. 4, which may not be tolerable for critical applications where the replacement of the devices can be costly or even impossible.

(68) B. 2 Simulation Results: I.sub.pMOS, T.sub.R, and ΔV Mitigation with the Aging-Aware DLDO

(69) Simulation results for all benchmarks for 4MOS, T.sub.R, and ΔV degradation mitigation of the uDSR-based DLDO 100 as compared to the conventional DLDO design for a 5-year time frame indicated up to 39.6%, 43.2%, and 42% performance improvement is achieved for, respectively, I.sub.pMOS, T.sub.R, and ΔV. The highest performance improvement is obtained for the LSU functional block with the highest operation temperature. Even at the lowest operation temperature within the L2 functional block, degradation mitigations of up to 15.1%, 16.4%, and 15.9% are achieved for, respectively, I.sub.pMOS, T.sub.R, and ΔV.

V. Conclusions

(70) The DLDO regulators can experience serious NBTI induced performance degradations including I.sub.pMOS, T.sub.R, and ΔV. These degradations are typically overlooked in the design of DLDOs and can deteriorate the regulation capability, response speed, and transient voltage noise profile. The present disclosure discloses a representative embodiment of a uni-directional shift register that evenly distributes the electrical stress among different power transistors to mitigate NBTI induced performance degradation with nearly no extra power and area overhead under arbitrary load conditions. Through practical simulations of an IBM POWER8 like microprocessor and benchmark evaluations, it is demonstrated that up to 39.6%, 43.2%, and 42% degradation mitigation can be achieved for, respectively, I.sub.pMOS, T.sub.R, and ΔV with the methods and apparatuses disclosed herein. Simulation results also highlight the necessity of adaptive design margins to avoid overdesign.

(71) It should be noted that the illustrative embodiments have been described with reference to a few embodiments for the purpose of demonstrating the principles and concepts of the invention. Persons of skill in the art will understand how the principles and concepts of the invention can be applied to other embodiments not explicitly described herein. For example, while the DLDO and the uDSR have been described with reference to FIGS. 6 and 7, respectively, as having particular configurations, those skilled in the art will understand that many modifications can be made to the configurations shown in FIGS. 6 and 7 while still achieving the goals and benefits described herein. As will be understood by those skilled in the art in view of the description provided herein, such modifications are within the scope of the invention.