HIGH-LINEARITY CASCODE AMPLIFIER AND METHOD THEREOF

Abstract

A cascode amplifier includes a first common-source amplifier (CSA) having a first MOST (metal oxide semiconductor transistor) of a first type configured to receive a first input signal and output a first current to a first node; a first common-gate amplifier (CGA) having a second MOST of the first type and configured to receive the first current from the first node and output a second current to a second node in accordance with a first bias voltage; a first source-follower (SF) having a third MOST of a second type configured to receive a second input signal and output a first voltage at the first node; and a load configured to establish a third voltage at a third node in response to the second current through a DC (direct current) path between the second node and the third node.

Claims

1. A cascode amplifier comprises: a first common-source amplifier (CSA) comprising a first MOST (metal oxide semiconductor transistor) of a first type and configured to receive a first signal and output a first current to a first node; a first common-gate amplifier (CGA) comprising a second MOST of the first type configured to receive the first current from the first node and output a second current to a second node in accordance with a first bias voltage; a first source-follower (SF) comprising a third MOST of a second type configured to receive a second signal and impose on a first voltage at the first node; and a load configured to establish a third voltage at a third node in response to the second current via a DC (direct current) path between the second node and the third node, wherein: the second signal is an inversion of the first signal, a source of the first MOST connects to a first DC node, and the load comprises an inductor configured to provide DC coupling between the third node and a second DC node.

2. The cascode amplifier of claim 1 further comprising a first neutralization capacitor configured to couple the second signal to the first node.

3. The cascode amplifier of claim 1, wherein the DC path comprises a short circuit inserted between the second node and the third node.

4. The cascode amplifier of claim 1, wherein the DC path comprises a second CGA comprising a fourth MOST of the first type and configured to transport the second current into a third current directed to the third node in accordance with a second bias voltage.

5. The cascode amplifier of claim 4 further comprising a second neutralization capacitor configured to couple the second signal to the second node.

6. The cascode amplifier of claim 4 further comprising a second SF comprising a fifth MOST of the second type and configured to receive a third signal and impose a second voltage at the second node, wherein the third signal is an inversion of the first signal.

7. The cascode amplifier of claim 1 further comprising an additional CSA comprising an additional MOST of the first type and configured to receive an additional signal and output an additional current to the first node, wherein a source of the additional MOST connects to the first DC node, and an AC (alternating current) component of the additional signal is approximately equal to an AC component of the first signal.

8. The cascode amplifier of claim 7, wherein the additional signal is AC coupled to the first signal via an AC coupling network configured to allow the additional signal and the first signal to have approximately the same AC components but different DC components.

9. The cascode amplifier of claim 1 further comprising an additional SF comprising an additional MOST of the second type and configured to receive an additional signal and along with the third MOST of the second type jointly impose on the first voltage at the first node, wherein a drain of the additional MOST of the second type connects to the first DC node, and an AC component of the additional signal is approximately equal to an AC component of the second signal.

10. The amplifier of claim 9, wherein the additional signal is AC coupled to the second signal via an AC coupling network configured to allow the additional signal and the second signal to have approximately the same AC components but different DC components.

11. A method comprising the following steps: receiving a first signal and a second signal that is an inversion of the first signal; converting the first signal into a first current directed to a first node using a first common-source amplifier (CSA) comprising a first MOST (metal oxide semiconductor transistor) of a first type, wherein a source, a gate, and a drain of the first MOST of the first type connect to a first DC (direct current) node, the first signal, and the first node, respectively; transporting the first current into a second current directed to a second node using a first common-gate amplifier (CGA) comprising a second MOST of the first type, wherein a source, a gate, and a drain of the second MOST of the first type connect to the first node, a first bias node, and the second node, respectively; imposing the second signal on a first voltage at the first node using a first source follower (SF) comprising a third MOST of a second type, wherein a source, a gate, and a drain of the third MOST of the second type connect to the first node, the second signal, and the first DC (direct current) node, respectively; and establishing a third voltage at a third node by directing the second current to the third node through a DC path and terminating the third node with a load comprising an inductor configured to provide DC coupling between the third node and a second DC node.

12. The method of claim 11 further comprising coupling the second signal to the first node using a first neutralization capacitor.

13. The method of claim 11, wherein the DC path comprises a short circuit inserted between the second node and a third node.

14. The method of claim 11 further comprising transporting the second current into a third current directed to the third node in accordance with a second bias voltage using a second CGA comprising a fourth MOST of the first type.

15. The method of claim 14 further comprising coupling the second signal to the second node using a second neutralization capacitor.

16. The method of claim 14 further comprising imposing a third signal on a second voltage at the second node using a second SF comprising a fifth MOST of the second type, wherein the third signal is an inversion of the first signal.

17. The method of claim 11 further comprising converting an additional signal into an additional current directed to the first node using an additional CSA comprising an additional MOST of the first type, wherein a source, a gate, and a drain of the additional MOST connect to the first DC node, an additional input signal, and the first node, respectively, and an AC (alternating current) component of the additional signal is approximately equal to an AC component of the first signal.

18. The method of claim 17, wherein the additional signal is AC coupled to the first signal via an AC coupling network configured to allow the additional signal and the first signal to have approximately the same AC components but different DC components.

19. The method of claim 11 further comprising imposing an additional signal on the first voltage using an additional SF comprising an additional MOST of the second type, wherein a source, a gate, and a drain of the additional MOST connect to the first node, the additional signal, and the first DC node, respectively, and an AC component of the additional signal is approximately equal to an AC component of the second signal.

20. The method of claim 19, wherein the additional signal is AC coupled to the second signal via an AC coupling network configured to allow the additional signal and the second signal to have approximately the same AC components but different DC components.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 shows a schematic diagram of a cascode amplifier in accordance with an embodiment of the present invention.

[0012] FIG. 2 shows a schematic diagram of a distributed source follower.

[0013] FIG. 3 shows a schematic diagram of an AC coupling network for the distributed source follower of FIG. 2.

[0014] FIG. 4 shows a schematic diagram of a distributed common-source amplifier.

[0015] FIG. 5 shows a flow diagram of a method in accordance with the present invention.

DETAILED DESCRIPTION OF THIS INVENTION

[0016] The present invention relates to cascode amplifiers. While the specification describes several example embodiments of the invention considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

[0017] Throughout this disclosure, DC stands for direct current, and AC stands for alternating current. A DC voltage refers to a substantially stationary voltage. An AC voltage refers to a voltage that varies with time in an oscillatory manner and is also referred to as a dynamic voltage. In general, a signal comprises a DC component and an AC component; the former is substantially stationary and remain fixed in a time duration of interest; and the latter is dynamic and can vary with time in a time duration of interest.

[0018] A DC node is a node of a substantially stationary voltage. Throughout this disclosure, V.sub.DD denotes a first DC node referred to as a power node, and V.sub.SS denotes a second DC node referred to as a ground node.

[0019] A common-source amplifier is embodied by a MOST configured to receive an input voltage from a gate and output an output current via a drain, wherein a source is connected to a DC node.

[0020] A common-gate amplifier is embodied by a MOST configured to receive an input current from a source and output an output current via a drain, wherein a gate is connected to a bias node, a voltage at which is equal to a bias voltage that is substantially stationary.

[0021] A cascode amplifier is a cascade of a common-source amplifier and a common-gate amplifier, wherein an output current of the common-source amplifier is an input current of the common-gate amplifier.

[0022] A source follower is embodied by a MOST configured to receive an input voltage at a gate and output an output voltage at a source, wherein a drain connects to a DC node or a circuit node of a sufficiently low impedance.

[0023] A circuit is a collection of a transistor, a capacitor, an inductor, a resistor, and/or other electronic devices inter-connected in a certain manner to embody a certain function. A network is a circuit or a collection of circuits configured to embody a certain function.

[0024] In this present disclosure, a circuit node is simply referred to as a node for short, as the meaning is clear from a context of microelectronics and won't cause confusion.

[0025] In this present disclosure, a signal is a voltage of a variable level that can vary with time. A (voltage) level of a signal at a moment represents a state of the signal at that moment.

[0026] As shown in FIG. 1, a cascode amplifier 100 in accordance with an embodiment of the present disclosure comprises: a first common-source amplifier CSA1 comprising a first NMOST NM1 and configured to receive a first input signal V.sub.i1 and output a first current I.sub.1 to a first node N1; a first common-gate amplifier CGA1 comprising a second NMOST NM2 and configured to receive the first current I.sub.1 via the first node N1 and output a second current I.sub.2 to a second node N2 in accordance with a first bias voltage V.sub.b1; a first source follower SF1 comprising a first PMOST PM1 and configured to receive a second input signal V.sub.i2 and output a first voltage V.sub.1 at the first node N1; and a first load LD1 comprising a parallel connection of a first inductor L1 and a first capacitor C1 and configured to establish a third voltage V.sub.3, which is an output voltage of the cascode amplifier 100, at a third node N3 in response to the second current I.sub.2 via a DC (direct current) path between the second node N2 and the third node N3. In a first embodiment of said DC path, dashed line DL1 is a solid connection between the second node N2 and the third node N3, so that N2 and N3 are electrically shorted and effectively become the same node. In a second embodiment of said DC path, dashed line DL1 is broken, a second common-gate amplifier CGA2 is added, inserted between the second node N2 and the third node N3, and configured to transport the second current I.sub.2 into a third current I.sub.3 directed to the third node N3. In a third embodiment that is an extension of the second embodiment, a second source follower SF2 comprising a second PMOST PM2 is further added and configured to receive a third input signal V.sub.i3 and output a second voltage V.sub.2 at the second node N2.

[0027] The first input signal V.sub.i1 is a RF (radio frequency) voltage signal that can be mathematically modeled by the following equation:

[00001]$\begin{array}{cc}{V}_{i1}=V_{\mathrm{dc}1}+A\left(t\right)\sin \left(t+\left(t\right)\right)& \left(1\right)\end{array}$

[0028] Here, V.sub.dc1 denotes a first DC (direct current) voltage, denotes an angular frequency, t denotes a time variable, A(t) denotes an amplitude function of time, and (t) denotes a phase function of time. Since V.sub.i1 is a gate voltage of NM1, V.sub.dc1 determines a biasing condition of CSA1. Note that V.sub.dc1 is a DC component of V.sub.i1, while A(t)sin(t+(t)) is an AC component of V.sub.i1.

[0029] The second input signal V.sub.i2 is a RF voltage signal that is an inversion of the first input signal V.sub.i1 and can be mathematically modeled by the following equation:

[00002]$\begin{array}{cc}{V}_{i2}=V_{\mathrm{dc}2}-{}_{2}A\left(t\right)\sin \left(t+\left(t\right)\right)& \left(2\right)\end{array}$

[0030] Here, V.sub.dc2 denotes a second DC voltage, and .sub.2 is a scaling factor that is positive. In an embodiment, .sub.21. It is clear from equations (1) and (2) that V.sub.i2 is an inversion of V.sub.i1, as far as an AC component is concerned. Since V.sub.i2 is a gate voltage of PM1, V.sub.dc2 determines a biasing condition of SF1.

[0031] The third input signal V.sub.i3 is a RF voltage signal that is an inversion of the first input signal V.sub.i1 and can be mathematically modeled by the following equation:

[00003]$\begin{array}{cc}{V}_{i3}=V_{\mathrm{dc}3}-{}_{3}A\left(t\right)\sin \left(t+\left(t\right)\right)& \left(3\right)\end{array}$

[0032] Here, V.sub.dc3 denotes a third DC voltage, and .sub.3 is a scaling factor that is positive. In an embodiment, .sub.31. It is clear from equations (1) and (3) that V.sub.i3 is an inversion of V.sub.i1, as far as an AC component is concerned. Since V.sub.i3 is a gate voltage of PM2, V.sub.dc3 determines a biasing condition of SF2.

[0033] Consider the first embodiment, wherein CGA2 and SF2 are absent and DL1 is a solid connection. In this case, the cascode amplifier 100 is the same as a conventional cascode amplifier except for the addition of SF1, which is incorporated to complement CSA1. CSA1 is a voltage-to-current conversion circuit (converting V.sub.i1 to I.sub.1) and is subject to an inherent nonlinearity of NM1, particularly when A(t) is large. On the contrary, SF1 is a voltage-to-voltage conversion circuit and has increased linearity, because there is local negative feedback, wherein a larger source-to-gate voltage of PM1 will cause PM1 to draw a larger current from the first node N1 to lower down V.sub.1 and thus reduce the source-to-gate voltage of PM1. Therefore, the cascode amplifier 100 can have a better linearity than a conventional cascode amplifier.

[0034] In the second embodiment, CGA2 is added to enhance a revere isolation and mitigate a kickback from N3 to N2.

[0035] In the third embodiment, SF2 is added to further enhance linearity.

[0036] In an optional embodiment, the cascode amplifier 100 further comprises a first neutralization capacitor CN1 configured to directly couple V.sub.i2 to V.sub.1. Capacitive coupling is inherently linear; therefore, this can improve linearity.

[0037] In another optional embodiment, the cascode amplifier 100 further comprises a second neutralization capacitor CN2 configured to directly couple V.sub.i2 to V.sub.2. Capacitive coupling is inherently linear; therefore, this can improve linearity.

[0038] In an alternative embodiment, SF1 is replaced with a distributed source follower DSF1 shown in FIG. 2. DSF1 comprises a parallel connection of a plurality of source followers; by way of example but not limitation, two source followers SF1a and SF1b embodied by PMOST PM1a and PM1b, respectively, are shown in FIG. 2. When using DSF1 to replace SF1, the second input signal V.sub.i2 received by SF1 is replaced by V.sub.i2a and V.sub.i2b received by SF1a and SF1b, respectively. V.sub.i2a and V.sub.i2b can be mathematically modeled by the following two equations:

[00004]$\begin{array}{cc}{V}_{i2a}=V_{\mathrm{dc}2a}-{}_{2a}A\left(t\right)\sin \left(t+\left(t\right)\right)& \left(4\right)\end{array}$$\begin{array}{cc}{V}_{i2b}=V_{\mathrm{dc}2b}-{}_{2b}A\left(t\right)\sin \left(t+\left(t\right)\right)& \left(5\right)\end{array}$

[0039] Here, V.sub.dc2a and V.sub.dc2b denote two DC voltages, and .sub.2a and .sub.2b denote two scaling factors that are positive. In an embodiment, .sub.2a1 and .sub.2b1. Note that in SF1, V.sub.dc2 determines a bias condition of PM1; in DSF1, on the other hand, V.sub.dc2a and V.sub.dc2b determine a bias condition of PM1a and PM1b, respectively. An advantage of using DSF1 to replace SF1 is that there is a higher degree of freedom in circuit design, as PM1a and PM1b can be biased in different bias conditions to allow DSF1 to remain at least partly turned on over a wider range of the amplitude function A(t) and thus improve linearity. In an embodiment, V.sub.i2a and V.sub.i2b are derived from V.sub.i2 using an AC (alternating current) coupling network ACCN1 shown in FIG. 3. ACCN1 comprises capacitors 311 and 321 configured to provide AC coupling from V.sub.i2 to V.sub.i2a and V.sub.i2b, respectively, and two resistors 312 and 322 configured to provide DC (direct current) coupling from V.sub.dc2a and V.sub.dc2b to V.sub.i2a and V.sub.i2b, respectively. Those skilled in the art may freely opt to use other AC coupling schemes, e.g., by using transformer, to fulfill AC coupling function to establish DC voltages of V.sub.i2a and V.sub.i2b at their discretion. In any case, a DC component of a signal can be altered while at the same time an AC component of the signal can remain substantially intact using an AC coupling scheme chosen by those skilled in the art at their discretion.

[0040] Similarly, SF2 may be replaced by a distributed source follower like DSF1, which will be obvious to those of ordinary skill in the art and thus not explained in detail here.

[0041] In an alternative embodiment, CSA1 is replaced with a distributed common-source amplifier DCSA1 shown in FIG. 4. DCSA1 comprises a parallel connection of a plurality of common-source amplifiers; by way of example but not limitation, two common-source amplifiers CSA1a and CSA1b embodied by NMOST NM1a and NM1b, respectively, are shown in FIG. 4. When using DCSA1 to replace CSA1, the first input signal V.sub.i1 received by CSA1 is replaced by V.sub.i1a and V.sub.i1b received by CSA1a and CSA1b, respectively. V.sub.i1a and V.sub.i1b can be mathematically modeled by the following two equations:

[00005]$\begin{array}{cc}{V}_{i1a}=V_{\mathrm{dc}1a}+{}_{1a}A\left(t\right)\sin \left(t+\left(t\right)\right)& \left(6\right)\end{array}$$\begin{array}{cc}{V}_{i1b}=V_{\mathrm{dc}1b}+{}_{1b}A\left(t\right)\sin \left(t+\left(t\right)\right)& \left(7\right)\end{array}$

[0042] Here, V.sub.dc1a and V.sub.dc1b denote two DC voltages, and .sub.2a and .sub.2b denote two scaling factors that are positive. In an embodiment, .sub.1a1 and .sub.1b1. Note that in CSA1, V.sub.dc1 determines a bias condition of NM1; in DCSA1, on the other hand, V.sub.dc1a and V.sub.dc1b determine a bias condition of NM1a and NM1b, respectively. An advantage of using DCSA1 to replace CSA1 is that there is a higher degree of freedom in circuit design, as NM1a and NM1b can be biased in different bias conditions to allow DCSA1 to remain at least partly turned on over a wider range of the amplitude function A(t) and thus improve linearity. In an embodiment, V.sub.i1a and V.sub.i1b are derived from V.sub.i1 using an AC (alternating current) coupling network in the same way as that V.sub.i2a and V.sub.i2b are derived from V.sub.i2 using an AC (alternating current) coupling network ACCN1 of FIG. 3; this is obvious to those of ordinary skill in the art and thus not described in detail here. Again, those skilled in the art can freely opt to use other AC coupling schemes, e.g., by using transformer, to fulfill AC coupling function to establish DC voltages of V.sub.i1a and V.sub.i1b for at their discretion.

[0043] The cascode amplifier 100 shown in FIG. 1 is a single-ended circuit embodiment; this is merely an example but not limitation. By adding a replica copy of the cascode amplifier 100 and applying respective complementary input signals (wherein a DC component is the same, while an AC component is inverted), one can construct a differential circuit embodiment. This will be obvious to those of ordinary skill in the art and thus not described in detail.

[0044] Now refer to FIG. 1. A purpose of the first capacitor C1 is to form a resonance with the first inductor L1 at the angular frequency . However, Cl is optional and may not be needed if a parasitic capacitance at the third node N3 is readily adequate to form the resonance with the first inductor L1.

[0045] For any given circuit comprising NMOST and/or PMOST, a function of said circuit remains the same if every NMOST is replaced with a PMOST, every PMOST is replaced with a NMOST, every power supply node is replaced with a ground node, and every ground node is replaced with a power supply node; in other words, NMOST and PMOST are swapped, and power supply node and ground node are also swapped. Therefore, in the appended claims, NMOST and PMOST are not explicitly stated; instead, MOST of a first type and MOST of a second type are stated; in one embodiment, MOST of a first type and MOST of a second type refer to NMOST and PMOST, respectively; in another embodiment, MOST of a first type and MOST of a second type refer to PMOST and NMOST, respectively. Likewise, power supply node and ground node are not explicitly stated; instead, a first DC node and a second DC node are used.

[0046] As shown in a flow diagram shown in FIG. 5, a method in accordance with an embodiment of the present disclosure comprises: (step 510) receiving a first signal and a second signal that is an inversion of the first signal; (step 520) converting the first signal into a first current directed to a first node using a first common-source amplifier (CSA) comprising a first MOST (metal oxide semiconductor transistor) of a first type, wherein a source, a gate, and a drain of the first MOST of the first type connect to a first DC (direct current) node, the first signal, and the first node, respectively; (step 530) transporting the first current into a second current directed to a second node using a first common-gate amplifier (CGA) comprising a second MOST of the first type, wherein a source, a gate, and a drain of the second MOST of the first type connect to the first node, a first bias node, and the second node, respectively; (step 540) imposing the second signal on a first voltage at the first node using a first source follower (SF) comprising a third MOST of a second type, wherein a source, a gate, and a drain of the third MOST of the second type connect to the first node, the second signal, and the first DC node, respectively; and (step 550) establishing a third voltage at a third node by directing the second current to the third node through a DC (direct current) path and terminating the third node with a load comprising an inductor configured to provide DC (direct current) coupling between the third node and a second DC node.

[0047] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made within the scope and spirit of the invention. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.