Reducing solder pad topology differences by planarization

Abstract

A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

Claims

1. A method comprising: providing an electronic device with a first surface and a second surface opposite the first surface; providing a first solder pad at a first distance above the first surface and a second solder pad at second distance above the first surface, the first distance being different from the second distance; providing a dielectric layer between the first solder pad and the second solder pad; after the step of providing the dielectric layer, plating a first metal layer portion over the first solder pad above a height of the dielectric layer so that, immediately after the step of plating, the first metal layer portion extends above any insulating material; after the step of providing the dielectric layer, plating a second metal layer portion, concurrently with plating the first metal layer portion, over the second solder pad above the height of the dielectric layer so that, immediately after the step of plating, the second metal layer portion extends above any insulating material; planarizing the first metal layer portion and the second metal layer portion, so that the step of planarizing planarizes only the material forming the first metal layer portion and the second metal layer portion, resulting in the first metal layer and the second metal layer having a third and a fourth surface respectively, wherein the third surface and the fourth surface are in the same plane and still have a height above the height of the dielectric layer, depositing a first solder layer over the first metal layer portion; and depositing a second solder layer over the second metal layer portion, such that a top surface of the first solder layer is in the same plane as a top surface of the second solder layer.

2. The method of claim 1: wherein the plated first metal portion has a fifth surface connected to the first solder pad and a sixth surface opposite the fifth surface, wherein the plated second metal portion has a seventh surface connected to the second solder pad and an eight surface opposite the seventh surface, and wherein the dielectric layer is closer to the first surface than any point of the sixth and eight surfaces.

3. The method of claim 1 wherein the electronic device is a chip after singulation from a wafer.

4. The method of claim 3 further comprising: positioning the chip with respect to a substrate having a third solder pad corresponding to the first solder pad and having a fourth solder pad corresponding to the second solder pad; bonding the first solder layer to the third solder pad; and bonding the second solder layer to the fourth solder pad.

5. The method of claim 4 wherein bonding the first solder layer to the third solder pad and bonding the second solder layer to the fourth solder pad are by solder reflow.

6. The method of claim 4 wherein bonding the first solder layer to the third solder pad and bonding the second solder layer to the fourth solder pad are by ultrasonic bonding.

7. The method of claim 1: wherein planarizing the first metal layer portion and the second metal layer portion comprises planarizing the first metal layer portion and the second metal layer portion to be higher than the dielectric portion.

8. The method of claim 1 wherein the electronic device is a chip after singulation from a wafer, and wherein the chip is a flip chip light emitting diode.

9. The method of claim 1 wherein the electronic device is a chip after singulation from a wafer, and wherein the chip is an integrated circuit.

10. The method of claim 1 wherein the plane is parallel to the first surface.

11. The method of claim 1 wherein the first surface of the electronic device forms a first plane, and wherein the plane of the top surface of the first solder layer and top surface of the second solder layer form a second plane that is not parallel to the first plane.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a cross-sectional simplified view of a prior art chip having solder pads or solder areas of different heights, resulting in solder bumps having different heights.

(2) FIG. 1B illustrates the chip of FIG. 1A being positioned over a substrate.

(3) FIG. 1C illustrates the structure of FIG. 1B after reflow, resulting in low reliability electrical connections due to the different heights of the solder bumps.

(4) FIG. 2A is a cross-sectional simplified view of a prior art chip having solder pads or solder areas of different heights, resulting in recessed solder bumps having different heights.

(5) FIG. 2B illustrates the chip of FIG. 2A positioned on a substrate, resulting in low reliability electrical connections due to the different heights of the solder bumps.

(6) FIG. 3 illustrates a simplified topology of a chip where the solder pads or solder areas have different heights, and where a dielectric portion is formed between the solder pads/areas.

(7) FIG. 4 illustrates a metal seed layer blanket-deposited and a patterned resist layer formed over portions that are not to be plated.

(8) FIG. 5 illustrates the chip after a plating process.

(9) FIG. 6 illustrates the chip with the planarization target as a dashed line.

(10) FIG. 7 illustrates the chip after planarization to planarize the metal pads so their top surfaces are in the same plane.

(11) FIG. 8 illustrates a uniform layer of solder deposited over the metal pads.

(12) FIG. 9 illustrates the resist removal and seed layer etch back.

(13) FIG. 10 illustrates the resulting chip positioned over a substrate, where the solder over all pads either touches the corresponding pads on the substrate or is separated by an insubstantial distance so that the reflow process causes the solder to form a reliable bond between the opposing pads.

(14) FIG. 11 illustrates how the plated metal layer may be formed lower than the resist layer, so both the metal layer and the resist layer are subsequently planarized.

(15) FIG. 12 is a flowchart identifying various steps that may be used in one embodiment of the invention.

(16) Elements that are the same or similar are labeled with the same numeral.

DETAILED DESCRIPTION

(17) Generally, the invention enables the use of less solder to ensure reliable connections are made between a chip and a substrate. The invention is particularly useful where solder pads are desired to be small and/or closely spaced.

(18) FIG. 3 illustrates a chip 40 that may be any electronic device, such as a flip chip light emitting diode (LED), an integrated circuit, a ceramic submount, an interposer, etc.

(19) A solder pad 42 is formed on the chip 40. The pad 42 may be a metal layer contacting a semiconductor region or the pad 42 may itself be a semiconductor layer. An area 44 is also shown, which may be another metal pad or semiconductor region where a metal connection is required. Pad 42 and area 44 are an exemplary embodiment which includes two different starting heights of areas where a solder interconnection is to be made. Both the pad 42 and area 44 may be metal layers having different heights. The difference in heights may only be a few microns.

(20) The pads 42 and area 44 may be electrically connected to semiconductor regions or other circuitry in or on the chip 40.

(21) Patterned dielectric layer 46 is formed between the pad 42 and area 44 as well as over other areas that are to be protected.

(22) In FIG. 4, a metal seed layer 48 is deposited over the surface of the chip 40 such as by sputtering. The seed layer 48 may be the same metal that will be plated over the seed layer, such as copper or other suitable material, or may be a different conductive material.

(23) If the plating process requires applying a potential to all of the plated areas, the seed layer 48 provides the conducting surface at the desired potential.

(24) A patterned resist layer 50 is formed over the portions of the seed layer 48 that are not to be plated.

(25) In FIG. 5, a potential is coupled to the seed layer 48, such as at an edge of the chip, and the chip is immersed in a plating solution. A copper electrode (or other metal to be deposited) is also immersed in the plating solution and the copper atoms migrate to the seed layer 48 to form a relatively thick plating layer 52. Layer 52 may be more than 10 microns thick. Electroless plating may also be used. The plating technique used may be conventional and need not be described in detail. A wide variety of metals may be deposited. The seed layer is no longer shown since it is assumed to be merged with the plating layer 52.

(26) The plating layer 52 extends over the dielectric layer 46 somewhat since the seed layer 48 is exposed around the edges of the dielectric layer 46. The plating layer 52 may be an irregular or a mushroom shape. The plating layer 52 may have higher and lower points relative to the surface of chip 40. In the alternative, plating layer 52 may be relatively smooth, but will still have a lowest point relative to chip 40.

(27) FIG. 6 illustrates a target planarization line 56 somewhat below the lowest point of the plating layer 52. The planarization line 56 may be even with the dielectric layer 46 or above it.

(28) In FIG. 7, a CMP process, or other planarization process, is performed to planarize the plating layer 52 to the planarization line 56 (FIG. 6). Note that the plating layer 52 still extends above the resist layer 50 so that the planarization only planarizes only one material. The top surfaces of all the plating layer portions are now in the same plane.

(29) In FIG. 8, a relatively thin and uniform solder layer 58 is deposited over the planarized plating layer 52 so that the top surface of the solder layer 58 over each pad 12 and area 14 is substantially planar. The solder layer 58 may be deposited by screen printing, plating, sputtering, or other suitable method. The solder layer 58 may be any conventional metal or metal combination, such as gold, tin, silver, nickel, or other metals and alloys thereof. The solder layer 58 may be made very thin due to the planar surface of the plating layer 52. This results in substantial cost savings if the solder is a precious metal. One or more interface layers may he deposited between the plating layer 52 and the solder layer 58 such as for improved wetting or bonding to the plating layer 52.

(30) In FIG. 9, the resist layer 50 and exposed seed layer 48 are etched away to electrically isolate the solder layer 58 over each plating layer 52 portion. Typically, the etch is a chemical etch.

(31) FIG. 10 illustrates the resulting chip 40 positioned over a substrate 62, where the solder layer 58 either touches the corresponding metal pads 64 on the substrate 62 or is separated by an insubstantial distance so that the reflow process causes the solder layer 58 to form a reliable bond between the opposing pads. The substrate 62 may be a printed circuit board, a submount, another chip, an interposer, or any other type of substrate.

(32) If an ultrasonic bond process is used, the pressure of the bonding process pushes the solder layer 58 against the pads 64 while softening and fusing the solder layer 58 to the pads 64. Therefore, there will be a reliable connection between all the solder layer 58 portions and the pads 64.

(33) FIG. 11 illustrates how the plated metal layer 65 may be formed lower than the resist layer 66 on the chip 67, so both the metal layer 65 and the resist layer 66 are subsequently planarized during the same planarization process. The target planarization line 68 is shown.

(34) FIG. 12 is a flowchart identifying various steps that may be used in one embodiment of the invention.

(35) In step 70, a chip is provided with solder pads that may have different heights.

(36) In step 72, a relatively thick metal layer is deposited over the solder pads, such as by plating.

(37) In step 74, the metal layer is planarized so that the top surface of the metal layer over each pad is in the same plane. In one embodiment, the plane of the metal layer over each pad is at an angle relative to a plane of the first surface.

(38) In step 76, a substantially uniformly thin layer of solder is deposited over the planarized metal layer so the top surface of the solder over each pad is in the same plane.

(39) In step 78, the chip is positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

(40) The present invention may be performed on a wafer scale prior to the chips being singulated or performed after the chips are singulated.

(41) The present invention is applicable to improving solder connections between any two opposing surfaces having solder pads and is not limited to chips.

(42) While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.