METHOD FOR CONTROLLING DIGITAL-TO-ANALOGUE CONVERTERS AND RF TRANSMIT CIRCUIT ARRANGEMENT

Abstract

The invention relates to a method for controlling digital-to-analogue converters (DAC), the method comprising: providing a plurality of digital-to-analogue converters (DAC) of a multi-channel converter array wherein each DAC includes a separate clock generator; generating, by each clock generator, a RF carrier signal; converting, by each DAC, digital data signals into analogue RF data signals based on the carrier signals of the corresponding clock generators; providing a separate control signal for each clock generator wherein the control signals comprise control information such that when the control signals are applied to the corresponding clock generators the different analogue RF data signals provided at respective output terminals of each DAC comprise a pre-defined phase shift to each other; controlling the clock generator of each DAC directly and independently based on the provided control signals. The invention further relates to a converter arrangement RF transmit circuit arrangement.

Claims

1. A method for controlling digital-to-analogue converters (DAC), the method comprising: providing a plurality of digital-to-analogue converters (DAC) of a multi-channel converter array wherein each DAC includes a separate clock generator; generating, by each clock generator, a RF carrier signal; converting, by each DAC, digital data signals into analogue RF data signals based on the carrier signals of the corresponding clock generators; providing a separate control signal for each clock generator wherein the control signals comprise control information such that when the control signals are applied to the corresponding clock generators the different analogue RF data signals provided at respective output terminals of each DAC comprise a predefined phase shift to each other; controlling the clock generator of each DAC directly and independently based on the provided control signals.

2. The method of claim 1, wherein the generated analogue RF data signals are each provided to antenna elements of an antenna array.

3. The method of claim 1, wherein the method is used for beamforming.

4. The method of claim 1, wherein the data signals are based on the JESD204 transport protocol standard or on the JESD204B transport protocol standard.

5. The method of claim 1, wherein the control signals are based on the JESD204 transport protocol standard or on the JESD204B transport protocol standard.

6. The method of claim 1, further comprising: coding an information of the starting phase, an increment and a point of time of switching into the control signal; analysing this information by the corresponding DAC; sample exact switching the clock generator of the corresponding DAC based on the analysed information.

7. The method of claim 1, wherein at least one control information per sample is provided to each clock generator.

8. The method of claim 1, wherein each DAC is individually synchronized with regard to the frequency and phase of the carrier signal.

9. The method of claim 1, wherein each DAC is individually synchronized with regard to the frequency and phase of the analogue RF data signals.

10. A RF transmit circuit arrangement, comprising: a digital serial interface circuit; a multi-channel converter array coupled on its digital input side to the digital interface circuit and having a plurality of digital-to-analogue converters (DAC) wherein each DAC includes a separate clock generator and wherein each DAC is configured to convert digital data signals provided by the digital serial interface circuit into analogue RF data signals; wherein the digital serial interface circuit further comprises a control circuit which is configured to provide control signals for controlling the clock generators of each DAC directly and independently and wherein each control signal comprises control information such that the different analogue RF data signals provided at respective output terminals of each DAC comprise a predefined phase shift to each other.

11. The arrangement of claim 10, wherein the digital serial interface circuit is a JESD204 interface.

12. The arrangement of claim 11, wherein the digital serial interface circuit is a JESD204B interface.

13. The arrangement of claim 10, wherein at least one clock generator is a numerically controlled oscillator (NCO).

14. The arrangement of claim 10, wherein at least one clock generator is a digitally controlled oscillator (DCO).

15. The arrangement of claim 10, wherein the RF transmit circuit arrangement is used for beamforming of the wirelessly transmitted RF data signals.

16. The arrangement of claim 10, further comprising an antenna array having a plurality of antenna elements, wherein each antenna element is connected on their input terminals to a corresponding output terminal of a DAC in order to provide the analogue RF data signals to the corresponding antenna elements.

17. The arrangement of claim 10, wherein the RF transmit circuit arrangement is configured to transmit radar signals.

18. The arrangement of claim 10, wherein the RF transmit circuit arrangement is configured to transmit high speed wireless communication signals.

19. The arrangement of claim 10, wherein the RF transmit circuit arrangement is configured to transmit radar signals or high speed wireless communication signals according to the LTE or 5G standard.

20. The arrangement of claim 10, wherein the digital serial interface circuit is connected to each of the DACs via a plurality of data lines for the RF data transmission and via a first control line for synchronizing the DAC with each other and via a second control line for setting the predefined phase shift.

Description

CONTENTS OF THE DRAWINGS

[0030] The present invention is described in greater detail in the following on the basis of the embodiments shown in the schematic figures of the drawings, in which:

[0031] FIG. 1 illustrates a partial view of a telecommunication device which comprises a multi DAC arrangement according to the invention for interfacing between a digital section and an analogue section;

[0032] FIG. 2 is a detailed block diagram for the multi DAC arrangement of FIG. 1;

[0033] FIG. 3 is a signal-time diagram for illustrating the phase shift between two transmit signals generated by different DACs of the RF transmit circuit arrangement of FIG. 2.

[0034] The appended drawings are intended to provide further understanding of the embodiments of the invention. They illustrate embodiments and, in conjunction with the description, help to explain principles and concepts of the invention. Other embodiments and many of the advantages mentioned become apparent in view of the drawings. The elements in the drawings are not necessarily shown to scale.

[0035] In the drawings, like, functionally equivalent and identically operating elements, features and components are provided with like reference signs in each case, unless stated otherwise.

DESCRIPTION OF EMBODIMENTS

[0036] As a non-limiting example, FIG. 1 illustrates a partial view of a telecommunication device 10 which comprises a digital section 11, an analogue section 12 and a multi DAC (digital-to-analogue converter) arrangement 13 for interfacing between the digital and analogue sections 11, 12. The digital and analogue sections 11, 12 can contain any components typically included in a conventional telecommunication device 10. For example, the digital section 11 can include a data processor 14 such as a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit) and/or a FPGA (Field Programmable Gate Array). The digital section 11 of the telecommunication device 10 typically comprises a digital radio circuit 15 such as a digital frequency up-converter. This digital radio circuit 15 may also be implemented as part of the DSP.

[0037] The analogue section 12 can include a filter 16, a power amplifier 17 and an output device 18. The analogue section 12 may also comprise other components, such as up-conversion circuits if for example frequency up-conversion is not performed by the digital section 11. The output device 18 comprises an antenna array 19 having a plurality of antenna elements for transmitting analog signals over the air (OTA) from the telecommunication device 10 to receiver devices, for example within a base station, a user equipment and the like. Alternatively, the output circuit 18 may comprise an array of output terminals.

[0038] The multi DAC arrangement 13 is configured to convert between digital signals from the digital section 11 to corresponding analogue signals towards the analogue section 12. For this purpose, the multi DAC arrangement 13 comprises a DAC array 20 having a plurality of single DACs 21, which hereinafter are also referred to as DAC element 21. The plurality of DACs 21 are arranged in parallel to each other for converting a digital signal from the digital section 11 to an analogue signal provided to the analogue section 12. Typically, each DAC path has a different analogue phase response. This can be achieved by using multiphase clocking to control operation of the DACs 21. In particular, the inputs and outputs of the DACs 21 can be delayed (i.e. phase shifted) with respect to each other in order to ensure that each DAC path has a different analogue phase response.

[0039] The multi DAC arrangement 13 further comprises a digital serial interface circuit 22 which is configured to provide a serial data stream X1 to the plurality of DACs 21. The digital serial interface circuit 22 further provides control information X2, X3 to each DACs 22. This control information X2, X3 comprises on the one hand side synchronization information X2 for synchronization of the different parallel arranged DAC elements 21. On the other hand side the control information X2, X3 comprises phase shift information X3 for setting a predefined phase shift for the analogue output data signals provided at the output side of the different DAC elements 21. The structure and functionality of the digital serial interface circuit 22 and DAC elements 21 is hereinafter described in more detail with regard to FIG. 2.

[0040] The digital serial interface circuit 22 may be implemented as part of the data processor 14 which is included in the digital section 11 of the telecommunication device 10. However, the digital serial interface circuit 22 may also be implemented separate from the data processor 14.

[0041] The telecommunication device 10 as a whole or parts of it denote the RF transmit circuit arrangement in the terminology of the present invention.

[0042] FIG. 2 shows a detailed block diagram for the multi DAC arrangement of FIG. 1. Here, the digital serial interface circuit 22 is a JESD204 interface 22 and in particular a JESD204B interface 22. Thus, the signal stream (data and control signals) produced by the digital serial interface circuit 22 is based on the JESD204 transport protocol standard.

[0043] The converter array 20 comprises an array of M DAC elements 21-1 to 21-M. In the present case, the converter array 20 comprises M=2 DAC elements 21-1, 21-2.

[0044] The digital serial interface circuit 22 is configured to provide an N-bit data stream X1-1, X1-2 to each of the DAC elements 21-1, 21-2.

[0045] Each DAC element 21-1, 21-2is an N-bit DAC 21-1, 21-2 which is configured to convert an N-bit digital signal X1-1, X1-2 into a corresponding analogue output signal X4-1, X4-2. For this purpose, each DAC element 21-1, 21-2 comprises at its input interface a de-serializer 23-1, 23-2. This deserializer 23-1, 23-2 is configured to convert the N-bit serial data stream X1-1, X1-2 in N different input signals which are provided to respective internal input terminals of the DAC element 21-1, 21-2.

[0046] The digital serial interface circuit 22 is further configured to provide a synchronization signal X2-1, X2-2 to each DAC element 21-1, 21-2. This synchronization signal X2-1, X2-2 is used for synchronization of the different DAC elements 21-1, 21-2 within the converter array 20.

[0047] According to one aspect of the present invention, each of the DAC elements 21-1, 21-2 of the converter array 20 comprises an independent internal numerically controlled oscillator (NCO) 24-1, 24-2. This NCO is used to generate a carrier signal. Within the corresponding DAC 21-1, 21-2 this carrier signal is then used as a carrier for the data which is modulated on the carrier signal.

[0048] According to a further aspect of the present invention, the digital serial interface circuit 22 provides a control signal X3-1, X3-2 to the NCO 24-1, 24-2. This control signal X3-1, X3-2 comprises control and phase shift information. If these control and phase shift information are provided to the corresponding NCOs 24-1, 24-2 of different DAC elements 21-1, 21-2, then the analogue output signals X4-1, X4-2 produced by the DAC elements 21-1, 21-2 comprise a predefined phase shift to each other. This relationship is illustrated in FIG. 3.

[0049] The generated analogue output signals X4-1, X4-2 are then forwarded to the antennas of the output device 18. With the beamforming technique, so-called smart antennas are used within the antenna array 19. Smart antennas are arrays of antenna elements, wherein each of these antenna elements receive an analogue signal X4-1, X4-2 to be transmitted with a predetermined phase offset and a relative gain. The net effect of the antenna array 19 is to direct a transmit beam in a predefined direction. The beam is steered and formed by controlling the phase and gain relationships of the signals that excite the antenna elements of the antenna array 19.

[0050] FIG. 3 shows a signal-time diagram for illustrating the phase shift between the transmit signals generated by two different DACs of the RF transmit circuit arrangement of FIG. 2.

[0051] Two analogue RF data signals X4-1, X4-2 are produced by the two DAC elements 21-1, 21-2 of FIG. 2. The two analogue RF data signals X4-1, X4-2 have a predefined phase shift X5 to each other. This predefined phase shift is set and controlled via the phase shift information comprised within the control signals X3-1, X3-2 provided to the corresponding DAC elements 21-1, 21-2. This way, according to the present invention, it is possible to transfer digital data with a predefined phase shift from the digital side to the analogue side of a DAC array 20. In particular, only one control information per sample is needed for each NCO 24-1, 24-2.

[0052] Although the present invention has been described in the above by way, it is not limited thereto, but rather can be modified in a wide range of ways. In particular, the invention can be changed or modified in various ways without deviating from the core of the invention.

REFERENCE SIGNS

[0053] 10 telecommunication device, RF transmit circuit arrangement [0054] 11 digital section [0055] 12 analogue section [0056] 13 multi DAC system/arrangement [0057] 14 data processor, DSP [0058] 15 digital radio circuit [0059] 16 filter [0060] 17 power amplifier [0061] 18 output device, output circuit [0062] 19 antenna array [0063] 20 DAC array [0064] 21, 21-1, 21-2 digital-to analogue converter, DAC, DAC element [0065] 22 digital serial interface circuitry [0066] 23-1, 23-2 de-serializer [0067] 24-1, 24-2 clock generator, numerically controlled oscillator, NCO [0068] X1, X1-1, X1-2 data stream, serial data signal [0069] X2, X2-1, X2-2 synchronization signal [0070] X3, X3-1, X3-2 control signal [0071] X4, X4-1, X4-2 analogue RF data signal [0072] X5 phase shift