TIME-TO-DIGITAL CONVERTER WITH PHASE-SCALED COURSE-FINE RESOLUTION

Abstract

A time-to-digital converter (TDC) measures a time interval T.sub.Tot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals T.sub.NOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals T.sub.NOR. A Vernier core for measures a residual time interval T.sub.R where T.sub.R=T.sub.TotmT.sub.NOR to obtain a value for the time interval T.sub.Tot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.

Claims

1. A time-to-digital converter for measuring a time interval T.sub.Tot between a leading signal and a triggering signal, comprising: a phase regulator incorporating a looped delay line to create pre-defined sub-intervals T.sub.NOR determined by the length of said delay line, said phase regulator having an input receiving said leading signal whereby said leading signal loops around said delay line; a counter for counting the number of times m said leading signal loops around said delay line before said triggering signal arrives to obtain a coarse measurement of said time interval defined in terms of said sub-intervals T.sub.NOR; and a Vernier core for measuring a residual time interval T.sub.R where T.sub.R=T.sub.TotmT.sub.NOR to obtain a value for the time interval T.sub.Tot.

2. A time-to-digital converter as claimed in claim 1, further comprising an evaluator responsive to outputs from said phase regulator, said counter, and said Vernier core to output said value for the time interval T.sub.Tot.

3. A time-to-digital converter as claimed in claim 1, comprising a first chain of delay elements, a portion of said first chain of delay elements forming part of said phase regulator, a second chain of delay elements, said delay elements in said first chain introducing a delay different from the delays introduced by said delay elements in said second chain, and an arbiter between said first and second chains of delay elements to create said Vernier core.

4. A time-to digital converter as claimed in claim 3, wherein said first and second chains of delay elements each comprise a NAND gate followed by a series of inverters, and said arbiter comprises a series of flip-flops arranged between outputs of pairs of delay elements from each said chain.

5. A time-to digital converter as claimed in claim 1, wherein said Vernier core comprises a first chain of delay elements, a second chain of delay elements, said delay elements in said first chain introducing a delay different from the delays introduced by said delay elements in said second chain, and a first arbiter between said first and second chains of delay elements to create said Vernier core, and wherein said phase regulator comprises a second arbiter coupled to a sub-set of said delay elements in said first chain, said sub-set of delay elements being looped in a ring structure.

6. A time-to digital converter as claimed in claim 5, wherein said first chain includes as a delay element a first NAND gate at the input to said sub-set of delay elements receiving at its inputs said leading signal and an output of said subset of delay elements, and a second NAND gate immediately downstream of said subset of delay elements receiving at its inputs the output of said sub-set of delay elements and the triggering signal.

7. A time-to digital converter as claimed in claim 5, wherein said triggering signal is a reference-retimed-by DCO (RRD) signal provided by a pre-logic module.

8. A time-to digital converter as claimed in claim 5, wherein said counter provides a coarse resolution output, said phase regulator provides a moderate resolution output, and said Vernier core provides a fine resolution output.

9. A time-to digital converter as claimed in claim 8, further comprising an evaluator responsive to outputs from said counter, said phase regulator, and said Vernier core for outputting the value for said time interval at a selected resolution.

10. A time-to digital converter as claimed in claim 1, wherein said phase regulator comprises a first chain of delay elements receiving the leading signal, an output of said first chain of delay elements being looped to an input thereof, said counter counting the number of passes of said first chain of delay elements, and a first arbiter responsive to a triggering signal to provide a measurement of said time interval at moderate resolution, and wherein said Vernier core comprises second and third chains of delay elements, with a second arbiter between said first and second chains of delay elements, said second chain having an input NAND gate with a first input receiving an output of said first chain and a second input receiving said leading signal, and said third chain having an input receiving said triggering signal.

11. A time-to-digital converter as claimed in claim 10, wherein said third chain has an input NAND gate with a first input receiving said triggering signal and a second input receiving an enable signal.

12. A method of obtaining a digital representation of a time interval T.sub.Tot between a leading signal and a triggering signal, comprising: creating pre-defined sub-intervals T.sub.NOR with a looped delay line; looping said leading signal through said looped delay line until a triggering signal arrives; counting the number of times m said leading signal loops around said delay line before said triggering signal arrives to obtain a coarse measurement of said time interval defined in terms of said sub-intervals T.sub.NOR; and measuring a residual time interval T.sub.R where T.sub.R=T.sub.TotmT.sub.NOR with a Vernier core to obtain a value for the time interval T.sub.Tot.

13. A method as claimed in claim 12, further comprising evaluating the outputs from said looped delay line, said counter, and said Vernier core to output said value for the time interval T.sub.Tot.

14. A method as claimed in claim 12, comprising looping said leading signal a portion of a first chain of delay elements, and applying said triggering signal to a second chain of delay elements, said delay elements in said first chain introducing a delay different from the delays introduced by said delay elements in said second chain, and deriving said residual time interval T.sub.R from an arbiter between said first and second chains of delay elements, said first and second chains of delay elements and said arbiter forming said Vernier core.

15. A method as claimed in claim 14, further comprising asserting an enable signal at an input of said second chain of delay elements after arrival of said triggering signal.

16. A method as claimed in claim 12, further comprising providing a first chain of delay elements, and a second chain of delay elements, said delay elements in said first chain introducing a delay different from the delays introduced by said delay elements in said second chain, a first arbiter between said first and second chains of delay elements to create said Vernier core, and a second arbiter coupled to a sub-set of said delay elements in said first chain, said sub-set of delay elements being looped in a ring structure, and obtaining a coarse measurement of said time interval from the number of times said leading signal loops around said sub-set of said delay elements, a moderate resolution measurement from said second arbiter, and a fine resolution measurement from said first arbiter.

17. A method as claimed in claim 16, further comprising applying said leading signal to a first input of a first NAND gate at the input said sub-set of delay elements and an output of said sub-set to a second input of said first NAND gate, and applying the output of said sub-set of delay elements and said triggering signal to respective inputs of a second NAND gate immediately downstream of said subset of delay elements.

18. A method as claimed in claim 17, wherein said triggering signal is a reference-retimed-by-DCO (RRD) signal.

19. A method as claimed in claim 12, further comprising applying the leading signal to a first chain of delay elements, and the triggering signal to a first arbiter, looping an output of said first chain of delay elements to an input thereof, counting the number of passes of said first chain of delay elements before the arrival of said triggering signal, applying said triggering signal to said first arbiter to obtain a measurement of said time interval at moderate resolution, and further providing said Vernier core comprising second and third chains of delay elements with a second arbiter between said first and second chains of delay elements, said second chain having an input NAND gate, said method further comprising applying an output of said first chain to a first input of said input NAND gate and said leading signal to a second input of said input NAND gate, and said triggering signal to an input of said third chain.

20. A method as claimed in claim 20, further comprising applying said triggering signal to an enable input of a NAND gate at the input of said third chain and an enable signal to a second input of said input NAND gate to said third chain.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] This invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:

[0024] FIG. 1a is a schematic diagram a prior art time-to-digital converter (TDC) employing an inverter-based digital delay line;

[0025] FIG. 1b is a timing chart for the TDC shown in FIG. 1a;

[0026] FIG. 2 is a schematic diagram of a prior art ring-oscillator TDC;

[0027] FIG. 3 is a schematic diagram of a prior art Vernier TDC;

[0028] FIG. 4 is a schematic diagram of a prior art Vernier ring TDC;

[0029] FIG. 5 is a schematic diagram of a typical digital PLL;

[0030] FIG. 6 is a schematic diagram of a phase-scaled Vernier TDC in accordance with one embodiment of the invention;

[0031] FIG. 7 is a timing diagram showing the way in which the phase (time) is sliced up in accordance with the invention;

[0032] FIG. 8 is an equivalent diagram of a TDC in accordance with an embodiment of the invention;

[0033] FIG. 9 is a schematic diagram of a second embodiment of the invention;

[0034] FIGS. 10a and 10b are block diagram and a timing chart illustrating the operation of the embodiment shown in 9; and

[0035] FIG. 11 is a schematic diagram of a third embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0036] FIG. 5 is a schematic diagram of a typical digital phase-locked loop (DPLL). The accumulator 10 receives a frequency control word FCW as one input and a reference-retimed-by DCO input (RRD) from TDC 12, which compares the output of the DPLL with a reference source REF. The generation of the RRD signal is described below. The remaining components of the DPLL are the adder 14, divider 16, digital low pass filter 18, digitally controlled oscillator 20, accumulator 22, and flip-flop 24. The digital PLL ideally requires the TDC 12 to perform over a wide phase (time) detection range, have a fine resolution, have a low power consumption while occupying a compact chip area, and allow for a high reference frequency REF.

[0037] FIG. 6 illustrates the principles of a phase-scaled Vernier TDC in accordance with a basic embodiment of the invention. This embodiment employs a partial-ring in a slow delay chain 35. A pre-logic input module 30 receives as inputs a digitized reference signal REF from a master clock and an output DCO from the digital controlled oscillator 20. The pre-logic module 30 receives REF and DCO signals as inputs, and outputs a leading signal and a triggering signal as shown in FIG. 7. In this example the leading and triggering signals go high at the transition edge of the REF and DCO signals. The ultimate objective is to determine the time interval between the transition edges of the REF and DCO signals.

[0038] The leading signal is applied to one input of NAND gate 32. The triggering signal is applied to one input of NAND gate 34 and to an input of normal phase counter 48.

[0039] The output of the NAND gate 32 is coupled to a chain 35 of inverter delay elements 36.sub.1, 36.sub.2 . . . 36.sub.N, each introducing a delay .sub.2. The output of NAND gate 34 is applied to a chain 37 of inverter delay elements 38.sub.1, 38.sub.2 . . . 38.sub.N, each introducing a delay .sub.1. It should be noted that the NAND gates 32, 34 also act as delay elements, introducing respective delays .sub.2 and .sub.1, typically 10 ps40 ps.

[0040] An arbiter 40 comprising respective D flip-flops 42 is arranged between the chains 35 and 37. The chains 37 and D flip-flops 42 form an N-stage fine resolution Vernier TDC core 54.

[0041] The Q outputs of the D flip-flops 42 are coupled to register bank and encoder 46, which provides the output representing the time difference between the leading and triggering signals as a thermometer code. It will be noted that the second input to the NAND gate 32 is taken from a point part-way down the chain 35, in this example, after the second inverter delay element 362. The second input to the NAND gate 34 is decoupled from the output of the chain 37, and acts as a fine-resolution enable input as will be described in more detail below.

[0042] In this exemplary embodiment the first three delay elements, NAND gate 32 and inverters 36.sub.1 and 36.sub.2 form a looped delay line in the form of a ring structure with a 3.sub.2 delay. The objective is to determine the delay between the leading signal and the triggering signal, given that the delay is likely to be less than the clock period of the master clock (REF). As shown in FIG. 7, the time interval or phase difference between the leading signal and the triggering signal is T.sub.Tot. In accordance with embodiments of the invention this period T.sub.Tot is broken up into a series of pre-defined sub-intervals, referred to herein as normal intervals, of length T.sub.Nor plus a residual interval T.sub.R.

[0043] In FIG. 6 the sub-interval T.sub.Nor is defined by the phase regulator 50 comprising the three delay elements 32, 36.sub.1 and 36.sub.2. The leading signal is looped through an odd number of delay elements, in this example delay elements 32, 36.sub.1 and 36.sub.2, each time incrementing the normal-phase counter 48 until the triggering signal occurs, at which point the normal phase counter stops incrementing. The count m in the phase counter 48 gives a coarse measure of the time interval T.sub.Tot based on the number of normal intervals that have passed when the triggering signal occurs without regard to the residual interval T.sub.R. The resolution of the output of the normal-phase counter 48 is the length of the delay line comprising delay elements 32, 36.sub.1 and 36.sub.2.

[0044] The remaining task is to find the value of the residual interval T.sub.R. This is achieved by the N-stage Vernier core 54. As the normal-phase counter 48 increments the enable signal input is asserted on the fine gear enable input of the NAND gate 34. The triggering signal propagates along the chain 37 consisting of delay elements 34, 38.sub.1 . . . 38.sub.N, each with a delay .sub.1. As the leading signal re-enters the chain 37 after each pass through the three delay elements 32, 36.sub.1 and 36.sub.2, corresponding together to the sub-interval T.sub.Nor, coincidence of the edge of the leading signal and the triggering signal as detected by the flip-flops 42 will give the fraction of the period T.sub.Nor in which the triggering signal occurs, or in other words T.sub.R.

[0045] The contents of the register 46 at the instant of coincidence give T.sub.R in a similar manner to a conventional Vernier TDC core except that in this case the reference point is the start of an interval T.sub.Nor, rather than an edge of the master clock pulse, namely the leading signal. The total time T.sub.tot is then given by the expression T.sub.tot=T.sub.Norm+T.sub.R, where m is the count in counter 48, namely the number of times the leading edge has looped through the phase regulator 50.

[0046] The value of N should be picked so as to allow the fine resolution Vernier TDC to just cover the normal-length sub-interval, T.sub.NOR. That means:

[00001]$N=\frac{T_{\mathrm{Nor}}}{T_{\mathrm{res}}}=\frac{T_{\mathrm{Nor}}}{.Math..Math.}$

[0047] where Tres is the desired resolution and is the difference in delays .sub.2.sub.1, of the slow and fast chains 35, 37.

[0048] For instance, if T.sub.NOR is set to be 60 ps and the desired resolution equals 5 ps, N should be 12. The output of the Vernier TDC (Q.sub.R) is:

Q.sub.R=T.sub.R/

[0049] where the value of Q.sub.R is between 0 and N.

[0050] The total delay .sub.Tot is then given by the expression;

T.sub.Tot=M.Math.N.Math.+Q.sub.R.Math.=(M.Math.N+Q.sub.R).Math.

[0051] This basic concept is illustrated in FIG. 8. The pre-logic module 30 generates the leading and triggering signals from the inputs REF and DCO coming respectively from a master clock and the DCO 20 of a DPLL. The leading signal is applied to the phase regulator 50. The triggering signal is applied to the normal-phase counter 48, the phase regulator 50, and the Vernier TDC core 54.

[0052] As previously noted, the count in the normal-phase counter 48 gives a coarse measure determined by the interval T.sub.NOR of the time interval T.sub.tot. The interval T.sub.NOR is determined by the length of the phase regulator 50. The fine resolution TDC core 54 provides the fractional interval T.sub.R, which is represented by a binary number output by the register bank and encoder 46. The evaluator 52 collates the information from the three sources 48, 50, 54 and produces a final output representing the total time T.sub.tot between the leading and triggering signals in the form of an output word Q.sub.Fin.

[0053] An alternative embodiment, which offers a 3-level switchable coarse/moderate/fine resolution, is shown in FIG. 9. In this embodiment the pre-logic module 130, which comprises a D flip-flop 131, outputs the leading signal to a phase regulator 150 forming a 5-stage 16 ps-resolution TDC core with a total delay of 80 ps. It should be noted that this embodiment employs RRD (reference-retimed-by-DCO) as the triggering signal and the reference signal itself as the leading signal.

[0054] The phase regulator 150 comprises a separate arbiter array 160 comprising a chain of D flip-flops 162 and a sub-set of delay elements 136.sub.1 . . . 136.sub.N of the delay chain 135. The last delay element 136.sub.N of the subset is followed by a NAND gate 180, which also serves as a delay element, that receives at its inputs the output of the last delay element 136.sub.N and the reference-retimed-by DCO (RRD) signal from pre-logic module 130 (described below) for achieving moderate resolution. In the moderate resolution mode the period T.sub.NOR is separated into five regions. The leading signal is applied to the phase regulator 150, which forms a 5-stage 16 ps resolution ring structure, and loops through in the same manner as shown in FIG. 6, with the number of rotations being counted by the normal-phase counter 148.

[0055] In addition this embodiment comprises a 40-stage 2 ps resolution Vernier TDC core 154 comprising delay chains 135, 137 and flip-flops 142. The respective delay chains have incremental delays .sub.2 and .sub.1.

[0056] The normal-phase counter 148 offers an 80 ps resolution defined by the length of the phase regulator 150 comprising NAND gate 132 and delay elements 136.sub.1 . . . 136.sub.N. In this mode the measured time interval is determined by the count in the normal-phase counter 148, which is output as an 8-bit word, M.

[0057] The core circuit comprising NAND gate 132 and delay elements 136.sub.1 . . . 136.sub.N acts as a ring oscillator TDC giving a resolution of 16 ps, namely the delay introduced by each stage. This additional interval, namely the location within T.sub.NOR to a resolution equal to the delay of each stage of the delay chain, is output as a 5-bit word Q.sub.M. Finally, with the 40-stage Vernier TDC core 154 enabled by fine gear enable input to NAND gate 134, the embodiment shown in FIG. 9 offers a 2 ps resolution output as a 40-bit word Q.sub.R. The alternative modes allow the user to choose between higher resolution performance and lower power consumption.

[0058] In this embodiment the rising edge of the leading signal (REF) enables the NAND gate 132, launching the run of the leading signal along the ring oscillator 132, 136.sub.1 . . . 136.sub.N.

[0059] The other input terminal of NAND gate 132 is high already. The leading signal starts travelling in the loop of the ring oscillator and it triggers the counting of the normal-phase counter 148 each time it completes a rotation (passes the last stage of the loop). The propagation along the ring will not stop until the triggering signal (RRD) appears. The counter 148 can tell how many rotations (M) of the leading signal has experienced around this ring structure. The time period of a single rotation around the ring is actually the normal-length phase (T.sub.Nor), which is set to be 80 ps in this case. The number of the stages of the phase regulator can be 3 or 5 or 7 (odd) to make ring oscillator work correctly and efficiently. In this non-limiting example, the number of delay stages of the ring oscillator (N.sub.ring) is set to 5. The propagation delay of each stage of the inverter in the phase regulator (t_ring) can be found from the expression:

[00002]$.Math..Math.t_{\mathrm{ring}}=\frac{T_{\mathrm{Nor}}}{N_{\mathrm{ring}}}=\frac{80.Math..Math.\mathrm{ps}}{5}=16.Math..Math.\mathrm{ps}={}_2$

[0060] In this case the delay .sub.2 equals to t.sub.ring.

[0061] The Vernier core 154 is not used during most of the phase detection operation, and is only used to measure the last fractional piece, T.sub.R. The arrival of the triggering signal (RRD) is used not only to start the run of the RRD signal along the fast path delay chain 137 but also to activate the sixth stage of the inverter in the slow path delay chain 135. The signal RRD controls NAND gate 180. At this point the triggering signal starts chasing the leading signal, and the position where the triggering signal just catches up with the leading signal is indicated by the transition of the arbiters' output Q.sub.R. The number of stages of the Vernier TDC core (N_core) 154 is determined by the desired normal-length phase and the desired resolution:

[00003]$N_{\mathrm{core}}=\frac{T_{\mathrm{Nor}}}{.Math..Math.}=\frac{80.Math..Math.\mathrm{ps}}{2.Math..Math.\mathrm{ps}}=40$

[0062] The slow-path 135 inverter delay (.sub.2) and the fast-path 137 inverter delay (.sub.1) should be equal to 16 ps and 14 ps respectively. The final TDC output Q.sub.Fin can be determined by acquired the M, N=40 and Q.sub.R.

[0063] Compared to the Vernier Ring TDC solution where two arrays of arbiters are needed for odd-rotation and even-rotation respectively, this solution only needs one array of arbiters due to the ring-less structure of the fast path. This means that the complexity of a 40-stage Vernier core in this solution is actually equivalent to that of a 20-stage Vernier ring solution.

[0064] Because the completion of the odd rotation corresponds to the falling edge of the input signal of the normal-phase counter and even rotation corresponds to the rising edge, the phase counter 148 should be a both-edge triggered counter to record each rotation of the signal. According to the phase detection range of 12.5 ns and 80 ps for T.sub.Nor, the phase counter 148 may record 156 rotations maximum. Thus, an 8 bit normal-phase Counter, which has a maximum count of 256, is sufficient.

[0065] A block diagram of this embodiment as well as a timing chart illustrating the operation are shown in FIGS. 10a and 10b. The pre-logic module 130 outputs the RRD signal to the normal phase counter 148, the phase regulator 150, and the fine TDC core 154.

[0066] FIG. 10a shows more details of the evaluator 52. The evaluator 52 calculates the output of the normal-phase counter, M (the number of normal length phase pieces between phase difference) and the output of the Vernier core unit in thermometer-code format (Q.sub.R<1:40>) which is determined by the equation Q.sub.R=T.sub.R/. Thus Q.sub.Fin for a 40 stage fine TDC core is determined by the expression:

Q.sub.Fin=M.Math.40+Q.sub.R

[0067] Usually a 40/6 bit thermometer-to-binary encoder is employed to convert Q.sub.R from thermometer code to binary code. The complexity of the thermometer-to-binary encoder increases exponentially with the digit number of thermometer code; although it is already much simpler than that of a priority type decoder, which is commonly used in a Vernier Ring TDC due to the possibility of the presence of multiple fake transitions. However, a 40/6 bit thermometer-to-binary encoder is still viewed as a complicated conversion and deserving of further simplification into an 8/3 bit simple encoder by applying the coordinated-determination device in the evaluator.

[0068] As shown in FIG. 10a, Q.sub.M<1:5>is the output of the arbiter 160 located in the phase-regulator (5-stage ring-oscillator), that actually can be regarded as the arbiter of a ring-oscillator TDC. The setting of T.sub.Nor (normal-length phase) of 80 ps is covered by a 5-stage ring-oscillator with a propagation delay of each stage at 16 ps (i.e. coarse resolution); also covered by a 40 stage Vernier TDC core with 2 ps resolution (fine resolution). Q.sub.M<1:5>and Q.sub.R<1:40>indicate the quantitative measurement value of T.sub.R with 16 ps and 2 ps resolution respectively. Each bit in Q.sub.M<1:5>sequentially corresponds to eight bits in Q.sub.r<1:40>as shown in FIG. 10b. In the evaluator 152, the exact position of the transition can be determined by the following steps: [0069] a) First Q.sub.M<1:5>passes through an array of XOR gates 190 (a)) to find the position of its values' transition (transferring the thermometer code format of data to simple code format Q.sub.M<1:5>). Q.sub.R<1:40>can be distributed into five sections, which correspond to Q.sub.M<1>Q.sub.M<5>. [0070] b) Second, the exclusive bit of high in Q.sub.M<1:5>is used to select through multiplexer 191 the corresponding section of Q.sub.r<1:40>which should be the section that contains the position of the edge transition in higher precision (labeled Q.sub.r<1:8>). [0071] c) Third, Q.sub.M<1:5>is converted by a simple 8/3 encoder 192 into a three bit output, B<3:5>which represents the three most significant bits of a 6 bit binary number which shows the effective remaining phase difference (T.sub.R) in coarse resolution of 16 ps. [0072] d) Meanwhile, Q.sub.r<1:8>is converted by an edge finder and a simple 8/3 encoder 193 into a three bit output, B<0:2>, which represents the three least significant bits of the above mentioned 6 bit binary number to exhibit the fine part of T.sub.R in 2 ps resolution. [0073] e) The key point is the 3-bit output of the coarse-detection (B<3:5>) from arbiters of the phase regulator can be just easily stacked onto the 3-bit of the fine-detection (B<0:2>), avoiding additional computation and conversion, provided the equation N.sub.core/N.sub.ring=2.sup.K holds (where K is a positive integer).

[0074] By reducing the processed bit number by 5 times (from 40 bits in Q.sub.R<1:40>to 8 bits in Q.sub.R<1:8>) the coordinated-determination device 197 not only facilitates the simplification of logic circuitry in the evaluator but also removes the possibility of the error due to the appearance of the fake transitions in other sections.

[0075] The multiplication arithmetic (M.Math.N.sub.core) is implemented by an adder 194 that adds the output of 5-bit shifter 198 and 3-bit shifter 199. Because the number 40 is expressed as 101000 in binary format, and M is shifted by 3 bits and 5 bits respectively, and the two shifted numbers are added, the result is a 13-bit binary number for M.Math.40. Finally, Q.sub.Fin will be determined by one more addition in adder 195 that adds M.Math.40 and Q.sub.R to give a total of 14 bits.

[0076] A still further embodiment is illustrated in FIG. 11. In this embodiment, which also employs RRD as the triggering signal, the phase regulator 250 is decoupled from the Vernier TDC core 254. This decoupling from the phase regulator circuitry and the fine TDC core circuitry makes the implementation easier. For example, in the embodiment of former architecture, .sub.2 has to be equal to t.sub.ring of 16 ps; while in the latter, .sub.2 can be set at 30 ps to reduce the area of the transistors in the TDC core circuit. This makes the device easier to implement and permits more flexibility in the management of the device parameters.

[0077] In the embodiment shown in FIG. 11, the phase regulator 250 comprises a chain 235 of delay elements comprising NAND gate 272 and inverters 266.sub.1 . . . 266.sub.N, and flip-flops 262. The phase regulator 250 comprises a 5-stage TDC core with 16 ps resolution structured as a typical ring oscillator. The normal-phase counter 248 counts the passes of the lead signal through the delay chain 255 and thus gives a measure of the time interval with a resolution of 80 ps. The arbiter array 260 operates as an inverter-based delay line and provides a 5-bit output, which increases the resolution to 16 ps. The arbiter 260 resolves the time to the particular flip-flop stage within each cycle of the ring structure as counted by the phase counter 248.

[0078] The separate Vernier TDC core 254 comprises delay chain 235 consisting of NAND gate 232 and inverter delay elements 236.sub.1 . . . 236.sub.N, and delay chain 237 NAND gate 234 and inverter delay elements 286.sub.1 . . . 286.sub.N. Arbiter array 240 comprises flip-flops 242.

[0079] As in the previous embodiments the pre-logic module generates the leading and triggering signals. The leading signal is applied to the phase regulator 250, and the number of loops that the leading signal passes through the chain 255 is counted by the normal-phase counter 248. The triggering signal is applied to the arbiter array 260 and to the input of the NAND gate 234 forming part of the 40-stage Vernier TDC core 254.

[0080] The normal-phase counter offers a resolution of 80 ps, namely the length of each cycle of the chain 255. The arbiter array acts as typical TDC and offers a resolution equal to the delay introduced by each stage, namely 16 ps. As in the FIG. 9 embodiment, the arbiter array 260 resolves the time measurement within each interval T.sub.NOR defined by the phase regulator 250 to a precision determined by the delay of the individual delay elements 266.sub.1 to 266.sub.N.

[0081] The output of the phase regulator 250 is applied to one input of the NAND gate 232 of the Vernier TDC core 254. The second input of the NAND gate 232 receives the leading signal from the pre-logic module 230. The triggering signal is also applied to an input of NAND gate 234, whose second input is an enable input.

[0082] The output of the chain 255 is applied to the input of chain 235. When an enable signal is asserted on the enable input of the NAND gate 234, the Vernier core 254 is activated and a 40-bit output with 2 ps resolution appears at the output of the arbiter array 240. The 40-bit word is taken from the Q-outputs of each flip-flop 242.

[0083] Because the phase regulator 250 is decoupled from the Vernier TDC core, this solution is easier to implement and offers a more flexible management of the device parameters. Embodiments of the invention offer a novel phase-scaled Vernier time-to-digital converter (TDC) architecture with a coarse/moderate/fine (80 ps/16 ps/2 ps) time resolution function is presented to achieve both large phase (time) detection range (32.7 ns in 14-bit) and fine time resolution (2 ps) as well as compact size and ultra-low power consumption simultaneously. The phase noise (caused by TDC) can also be improved allowing higher reference frequency compared to other types of TDC architectures. A phase-regulator has been created and embedded into a traditional Vernier TDC core circuitry for the purpose of separating a new-defined mandatory phase length (no longer than the normal-length phase, 80 ps) from the random phase (time) difference (up to 32 ns) to be measured. The mandatory phase length will be the only part for fine-resolution (2 ps) measurement and the rest of the phase length will be counted in coarse resolution (80 ps). The required number of stages of the traditional Vernier TDC core can be remarkably reduced from 6250 to 40 at a fixed 2 ps time resolution. Furthermore, compared to a typical Vernier ring TDC, the proposed architecture being combined with a reverse-triggered pre-logic unit and the coordinated-determination scheme facilitates a much simpler and faster determination procedure, which allows several times reduction of the power consumption as well as the raise of the reference frequency in order to achieve a 2-3 dB improvement of the phase noise performance.

[0084] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. For example, a processor may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term processor should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included. The functional blocks or modules illustrated herein may in practice be implemented in hardware or software running on a suitable processor.