Optimized hardware architecture and method for ECC point doubling using Jacobian coordinates over short Weierstrass curves

Abstract

An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptical Curve Cryptography point doubling algorithm for Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values.

Claims

1. A data cryptographic apparatus comprising: computational logic configured to perform an elliptic curve cryptography (ECC) point doubling operation using Jacobian coordinates over a short Weierstrass curve of the form y=x.sup.3+ax+b where a=3; a register memory configured to store a point in the Jacobian coordinates, wherein the register memory is configured for two temporary storage variables, T.sub.1 and T.sub.2; a modular multiplier electrically coupled to the register memory, wherein the modular multiplier is configured to perform at most one modular multiplication for each step in a sequence of steps in the ECC point doubling operation; and a simple arithmetic processor configured; to perform modular subtraction, modular multiplication by two, and modular division by two in support of the ECC point doubling operation utilizing four logical one bit left shifters, an adder, and a subtractor to output either 3C, AB/2, AB, A2B, or 2AB for an input of variables A, B, and C, wherein the simple arithmetic processor is electrically coupled to the register memory and the modular multiplier, wherein the simple arithmetic processor outputs a result of the ECC point doubling operation in the Jacobian coordinates.

2. A mobile device comprising the apparatus of claim 1.

3. A smartcard comprising the apparatus of claim 1.

4. The mobile device of claim 2, wherein the mobile device is a smartphone.

5. A method for performing an elliptic curve cryptography (ECC) point doubling operation using Jacobian coordinates over a short Weierstrass curve of the form y=x.sup.3+ax+b where a=3, comprising: accepting, as variable input at a simple arithmetic processor of a computational device, a point in the Jacobian coordinates; configuring the simple arithmetic processor of the computational device for modular subtraction, modular division by two, and modular multiplication by two utilizing four logical one bit left shifters, an adder, and a subtractor, wherein an input of variables A, B, and C to the simple arithmetic processor results in an output of either 3C, AB/2, AB, A2B, or 2AB; enabling, a modular multiplier of the computational device to execute a sequence of steps to perform the ECC point doubling operation of the point in the Jacobian coordinates, wherein the modular multiplier performs at most one modular multiplication for each step in the sequence of steps, wherein the sequence of steps requires no more than two temporary variables; and outputting, by the computational device, a result of the ECC point doubling operation in the Jacobian coordinates.

6. The method of claim 5, wherein the computational device is part of a mobile device.

7. The method of claim 6, wherein the mobile device is a smartphone.

8. The method of claim 5, wherein the computational device is part of a smartcard.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows stages 101, 102 and 103 that are needed to realize the Elliptical Curve Digital Signature Algorithm (ECDSA).

(2) FIG. 2 shows a prior art point doubling algorithm.

(3) FIG. 3 shows an embodiment in accordance with the invention.

(4) FIG. 4 shows an embodiment in accordance with the invention.

(5) FIG. 5 shows an embodiment in accordance with the invention.

(6) FIG. 6 shows an embodiment in accordance with the invention.

(7) FIG. 7 shows an embodiment in accordance with the invention.

DETAILED DESCRIPTION

(8) PDBL algorithm 300 in accordance with the invention is shown in FIG. 3. PDBL algorithm 300 requires fewer steps and reduces the storage requirements compared to PDBL algorithm 200 for the same modular point doubling. PDBL algorithm 300 requires only two temporary storage registers, T.sub.1 and T.sub.2. PDBL algorithm 300 is implemented over an optimized hardware architecture shown in FIG. 6 and FIG. 7 and specifically designed to take advantage of PDBL algorithm 300.

(9) As input in step 301, PDBL algorithm 300 shown in FIG. 3 takes point P=(X.sub.1, Y.sub.1, Z.sub.1) in Jacobian coordinates. T.sub.1 and T.sub.2 are temporary storage variables. Note that all mathematical operations shown are in modular arithmetic and all coordinates are Jacobian. In step 302 of PDBL algorithm 300, if P= (the identity element) the value is returned. In step 303, the coordinate Z.sub.1 is squared (Z.sub.1*Z.sub.1) and subtracted from X.sub.1 with the resulting value stored in temporary register T.sub.2. In step 304, 3T.sub.2*(2X.sub.1T.sub.2) is calculated and the resulting value stored in temporary register T.sub.2. In step 305, T.sub.2 is squared and the result stored in X.sub.3. In step 306, 2Y.sub.1*Z.sub.1 is calculated, the result stored in Z.sub.3. In step 307, 2Y.sub.1 is calculated and squared (2Y.sub.1*2Y.sub.1) with the result stored in Y.sub.3. In step 308, X.sub.32Y.sub.3*X.sub.1 is calculated and the result stored in X.sub.3. In step 309, (Y.sub.3*X.sub.1X.sub.3) is calculated and multiplied by T.sub.2 and the result is stored in T.sub.1. Note that the quantity Y.sub.3*X.sub.1 was already calculated in step 308 so step 309 only requires a single modular multiplication (by T.sub.2). In step 310, T.sub.1Y.sub.3*Y.sub.3/2 is calculated and the result is stored in Y.sub.3. Finally, in step 311 the result of the point doubling of P is returned in Jacobian coordinates as (X.sub.3, Y.sub.3, Z.sub.3).

(10) The most computationally intensive operation in PDBL algorithm 300 in FIG. 3 is modular multiplication denoted by *. Because most of the steps described in PDBL algorithm 300 depend on the previous steps of the algorithm, it is typically most efficient to implement PDBL algorithm 300 in hardware using a single modular multiplier although more than one modular multiplier may be used in accordance with the invention which allows more than one modular multiplication to be performed in a step. Using only one modular multiplier restricts each step in PDBL algorithm 300 to having no more than one modular multiplication.

(11) It is important to note that besides the modular multiplication steps performed in steps 303, 308 and 309 of PDBL algorithm 300, additional, comparatively simple operations are performed as well: modular subtraction and addition and modular multiplication and division by 2. Note that multiplication or division by a power of 2 in binary is merely a shift operation. In order to accelerate execution of PDBL algorithm 300 and eliminate the need for additional temporary registers, an embodiment in accordance with the invention of simple arithmetic unit (SAU) 400 with the inputs and outputs as shown in FIG. 4 is used.

(12) FIG. 5 shows how steps 303, 304, 306, 307, 308, 309 and 310 are broken down to take advantage of SAU 400 which has inputs A, B and C with outputs D and E. Note that the input and output labels of SAU 400 correspond to the respective variable names in FIG. 5. Block 501 shows how step 303 of PDBL algorithm 300 is broken down using SAU 400 and involves setting inputs A=X.sub.1 and B=Z.sub.1.sup.2 with output E=AB. Block 502 shows how step 304 of PDBL algorithm 300 is broken down using SAU 400 and involves setting inputs A=X.sub.1, B=T.sub.2 and C=T.sub.2 with outputs D=3C and E=2AB. Outputs D and C are then multiplied together and the result is stored in temporary register T.sub.2. Block 503 shows how step 306 of PDBL algorithm 300 is broken down using SAU 400 and involves setting A=Y.sub.1 and B=0 with output E=2AB. Output E is then multiplied by Z.sub.1 and the result is stored in Z.sub.3. Block 504 shows how step 307 of PDBL algorithm 300 is broken down using SAU 400 and involves setting inputs A=Y.sub.1 and B=0 with output E=2AB. Output E is then multiplied by itself and the result is stored in Y.sub.3. Block 505 shows how step 308 of PDBL algorithm 300 is broken down using SAU 400 and involves setting inputs A=X.sub.3 and B=X.sub.1*Y3 with output E=A2B. Output E is stored in X.sub.2. Block 506 shows how step 309 of PDBL algorithm 300 is broken down using SAU 400 and involves setting input A=X.sub.1*Y.sub.3 and B=X.sub.3 with output E=A2B. Note that step 309 reuses the result of step 308 for X.sub.1*Y.sub.3 (stored in the output register of the multiplier). Output E is stored in X.sub.3. Block 507 shows how step 310 of PDBL algorithm 300 is broken down using SAU 400 and involves setting inputs A=T.sub.1 and B=Y.sub.3.sup.2 with output E=AB/2. Note that don't care indicates the value is irrelevant to the calculation being performed in the respective steps.

(13) FIG. 6 shows embodiment 600 in accordance with the invention comprising multi-cycle multiplier 610 with output register (not shown), SAU 400, multiplexer (MUX) 620 and MUX 630 with input registers X.sub.1, Y.sub.1, Z.sub.1, (x.sub.2, y.sub.2not used), output registers X.sub.3, Y.sub.3, Z.sub.3 and temporary registers T.sub.1 and T.sub.2 that are all part of register memory 695. Note the individual register labels correspond to variable names in FIGS. 3 and 5. MUX 620, 630 and 740 (part of SAU 400, see FIG. 7) are controlled by the microprocessor (not shown) which schedules the steps of PDBL algorithm 300. As noted above, each step in PDBL algorithm 300 involve at most one modular multiplication by multi-cycle multiplier 610 (not counting multiplication or division by 2 which in binary representation is merely a shift operation).

(14) SAU 400 shown in FIG. 7 comprises subtractor 710 and adder 711, logical one bit left shifter 715 (multiplication by 2), logical one bit right shifter 716 (division by 2), logical one bit left shifter 717 (multiplication by 2), logical one bit left shifter 718 (multiplication by 2), MUX 720 and MUX 725.

(15) Input A goes to both input 0 of MUX 720 and logical one bit left shifter 715 on line 671. Logical one bit left shifter 715 multiplies input A by two and outputs 2A on line 771 to the 1 input of MUX 720. Output line 776 of MUX 720 provides the minuend input for subtractor 710. Input B goes to logical one bit right shifter 716, logical one bit left shifter 717 and input 1 of MUX 725 on line 672. Logical one bit right shifter 716 divides input B by two and outputs B/2 on line 772 to input 0 of MUX 725. Logical one bit left shifter 717 multiplies input B by two and outputs 2B on line 774 to input 2 of MUX 725. Output line 777 of MUX 725 connects to the subtrahend input of subtractor 710. Input C connects to adder 722 and to logical one bit left shifter 718 on line 673. Logical one bit left shifter 718 multiplies input C by two and outputs 2C to adder 722 on line 775. Subtractor 710 outputs E (see FIG. 4) on line 696. Adder 722 outputs D (=3C) on line 690.

(16) Multi-cycle multiplier 610 functions by multiplying the values on lines 635 and 640 together and outputting the result on lines 650 and 650. Steps 301-302 of PDBL algorithm 300 are performed on the microprocessor (not shown) without using multi-cycle multiplier 610 and SAU 400.

(17) Step 303 utilizes both multi-cycle multiplier 610 and SAU 400. Register memory 695 provides X.sub.1 on line 665 to input 0 of MUX 620 with MUX 620 set to 0 and Z.sub.1 is provided from register memory 695 on both lines 635 and 640 to multi-cycle multiplier 610. Multi-cycle multiplier 610 computes Z.sub.1.sup.2 which is output on line 650 to input 1 of MUX 630 with MUX 630 set to 1. MUX 620 sends X.sub.1 to input A of SAU 400 on line 671 and MUX 630 sends Z.sub.1.sup.2 to input B of SAU 400 on line 672. MUX 720 in SAU 400 is set to 0 and MUX 720 sends A on line 776 from line 671 to the minuend input of subtractor 710 on line 776. MUX 725 in SAU 400 is set to 1 and MUX 725 sends on line 777 B from line 672 to the subtrahend input of subtractor 710 on line 777. Subtractor 710 computes E (which is AB=X.sub.1Z.sub.1.sup.2) of which is passed to register memory 695 on line 696 and stored in temporary register T.sub.2.

(18) Step 304 utilizes both multi-cycle multiplier 610 and SAU 400. Register memory 695 provides X.sub.1 on line 665 to input 0 of MUX 620 and MUX 620 is set to 0. MUX 620 sends X.sub.1 to input A of SAU 400 on line 671. Register memory 695 provides T.sub.2 on line 660 to input 0 of MUX 630 with MUX 630 set to 0 and register memory 695 also provides T.sub.2 to input C of SAU 400 on line 673. MUX 720 in SAU 400 is set to 1 and MUX 720 sends 2A from line 771 on line 776 to the minuend input of subtractor 710. MUX 725 in SAU 400 is set to 1 and MUX 725 sends B from input line 672 on line 777 to the subtrahend input of subtractor 710 on line 777. Input C (T.sub.2) of SAU 400 on line 673 is sent to both logical one bit left shifter 718 and adder 720. The output 2C on line 775 from logical one bit left shifter 718 goes to adder 720. Adder 720 outputs D (which is 3C=3T.sub.2) on line 690 and subtractor 710 computes E (which is 2AB=2X.sub.1T.sub.2) on line 696 to register memory 695 which passes E and D on lines 635 and 640, respectively, to multi-cycle multiplier 610 which computes E*D and sends the result on line 650 to register memory 695 where the result is stored in temporary register T.sub.2.

(19) Step 305 utilizes multi-cycle multiplier 610. T.sub.2 is provided from register memory 695 to both lines 635 and 640 to multi-cycle multiplier 610 which computes and outputs T.sub.2.sup.2 on line 650 to register memory 695 where the result is stored in X.sub.3.

(20) Step 306 utilizes both multi-cycle multiplier 610 and SAU 400. Register memory 695 provides Y.sub.1 on line 665 to input 0 of MUX 620 and MUX 620 is set to 0. MUX 620 sends Y.sub.1 to input A of SAU 400 on line 671. Logical one bit left shifter 718 takes input A on line 671, multiplies input A by two and outputs 2A on line 771 to MUX 720. MUX 720 in SAU 400 is set to 1 and MUX 720 sends 2A on line 776 to the minuend input of subtractor 710. Binary 0 is supplied on line 660 to input 0 of MUX 630 with MUX 630 set to 0. MUX 630 sends binary 0 from line 660 to input B of SAU 400 on line 672. MUX 725 in SAU 400 is set to 1 and MUX 725 sends binary 0 on line 777 to the subtrahend input of subtractor 710. Subtractor 710 computes 2AB on line 696 to register memory 695 as E (which is 2AB=2Y.sub.1) which passes the value through on line 635 to multi-cycle multiplier 610 and register memory 695 provides Z.sub.1 on line 640 to multi-cycle multiplier 610. Multi-cycle multiplier 610 computes E*Z.sub.1 (2Y.sub.1*Z.sub.1) and sends the result on line 650 to register memory 695 where it is stored in Z.sub.3.

(21) Step 307 utilizes both multi-cycle multiplier 610 and SAU 400. Register memory 695 provides Y.sub.1 on line 665 to input 0 of MUX 620 and MUX 620 is set to 0. MUX 620 sends Y.sub.1 to input A of SAU 400 on line 671. Logical one bit left shifter 715 takes input A on line 671, multiplies input A by two and outputs 2A on line 771 to input 1 of MUX 720. MUX 720 in SAU 400 is set to 1 and MUX 720 sends 2A on line 776 to the minuend input of subtractor 710. Binary 0 is supplied on line 660 to input 0 of MUX 630 with MUX 630 set to 0. MUX 630 sends binary 0 from line 660 to input B of SAU 400 on line 672. MUX 725 in SAU 400 is set to 1 and MUX 725 sends binary 0 on line 777 to the subtrahend input of subtractor 710. Subtractor 710 computes 2AB (which is 2Y.sub.1) as E on line 696 to register memory 695 which passes E through both on line 635 and on line 640 to multi-cycle multiplier 610. Multi-cycle multiplier 610 computes E.sup.2 (which is (2Y.sub.1).sup.2) and sends the result to register memory 695 on line 650 where it is stored in Y.sub.3.

(22) Step 308 utilizes both multi-cycle multiplier 610 and SAU 400. Register memory 695 provides X.sub.3 on line 665 to input 0 of MUX 620 and MUX 620 is set to 0. MUX 620 sends X.sub.3 to input A of SAU 400 on line 671 which connects to input 0 of MUX 720 with MUX 720 set to 0. MUX 720 sends A on line 776 to the minuend input of subtractor 710. Register memory 695 provides Y.sub.3 on line 635 to multi-cycle multiplier 610 and provides X.sub.1 on line 640 to multi-cycle multiplier 610. Multi-cycle multiplier 610 computes Y.sub.3*X.sub.1 and sends the result to input 1 of MUX 630 and MUX 630 is set to 1. MUX 630 sends Y.sub.3*X.sub.1 to input B of SAU 400 on line 672. Logical one bit left shifter 717 takes input B on line 672, multiplies input B by two and outputs 2B (2Y.sub.3*X.sub.1) on line 774 to input 2 of MUX 720. MUX 720 is set to 2 and sends 2B on line 777 to the subtrahend input of subtractor 710. Subtractor 710 computes E (which is A2B=X.sub.32Y.sub.3*X.sub.1) on line 696 to register memory 695 where it is stored in X.sub.3.

(23) Step 309 utilizes both multi-cycle multiplier 610 and SAU 400. In step 308, Y.sub.3*X.sub.1 was computed by multi-cycle multiplier 610. Hence, Y.sub.3*X.sub.1 is still present in the output register (not shown) of multi-cycle multiplier 610 and in Step 309 is sent on line 650 to input 1 of MUX 620 and MUX 620 is set to 1. MUX 620 provides Y.sub.3*X.sub.1 to input A of SAU 400 on line 671 which connects to input 0 of MUX 720. MUX 720 in SAU 400 is set to 0 and MUX 720 sends A (which is Y.sub.3*X.sub.1) on line 776 to the minuend input of subtractor 710. Register memory 695 provides X.sub.3 on line 660 to input 0 of MUX 630 and MUX 630 is set to 0. MUX 630 sends X.sub.3 to input B of SAU 400 on line 672 which connects to input 1 of MUX 725. MUX 725 is set to 1 and provides B on line 777 to the subtrahend input of subtractor 710. Subtractor 710 computes E (AB=Y.sub.3*X.sub.1) which is sent on line 696 to register memory 695 which passes the value through on line 635 to multi-cycle multiplier 610 and register memory 695 provides T.sub.2 on line 640 to multi-cycle multiplier 610. Multi-cycle multiplier 610 computes E*T.sub.2 (which is (Y.sub.3*X.sub.1X.sub.3)*T.sub.2) and sends the result on line 650 to register memory 695 where it is stored in temporary register T.sub.1.

(24) Step 310 utilizes both multi-cycle multiplier 610 and SAU 400. Register memory 695 provides T.sub.1 on line 665 to input 0 of MUX 620 and MUX 620 is set to 0. MUX 620 sends T.sub.1 to input A of SAU 400 on line 671 which connects to input 0 of MUX 720. MUX 720 in SAU 400 is set to 0 and MUX 720 sends A (T.sub.1) on line 776 to the minuend input of subtractor 710. Y.sub.3 is provided from register memory 695 to both lines 635 and 640 to multi-cycle multiplier 610 which computes Y.sub.3.sup.2 and which is output on line 650 to input 1 of MUX 630 with MUX 630 set to 1. MUX 630 provides Y.sub.3.sup.2 on line 672 to input B of SAU 400. Logical one bit right shifter 716 takes input B on line 672, divides input B by two and outputs B/2 (Y.sub.3.sup.2/2) to input 0 of MUX 725 and MUX 725 is set to 0. MUX 725 sends B/2 on line 777 to the subtrahend input of subtractor 710. Subtractor 710 computes E (AB/2=T.sub.1Y.sub.3.sup.2/2) which is sent on line 696 to register memory 695 where it is stored in Y.sub.3.

(25) Step 311 is performed in the microprocessor and returns the result of PDBL algorithm 300 which is (X.sub.3, Y.sub.3, Z.sub.3) for input (X.sub.1, Y.sub.1, Z.sub.1).