DIFFERENTIAL INPUT CIRCUITS WITH INPUT VOLTAGE PROTECTION

Abstract

Differential input circuits employ protection transistors and feedback paths to limit the differential voltage applied to input transistors. In an example arrangement, a differential input voltage is applied to terminals of the protection transistors, and current paths couple the respective protection transistors to control terminals of the input transistors, respectively. A control terminal drive voltage source is coupled to the control terminals of the input protection transistors to control the drive voltage applied to those terminals. Feedback paths, one for each of the input transistors, control voltages applied to the control terminals of the input transistors, maintaining the input differential voltage at a relatively low level and defined by the product of a specified current value and a specified resistance value.

Claims

1. A differential input circuit, comprising: a first input voltage protection transistor having a control terminal and a first input terminal of the differential input circuit; a second input voltage protection transistor having a control terminal and a second input terminal of the differential input circuit; a first input transistor having a control terminal coupled to the first input voltage protection transistor by a first current path; a second input transistor having a control terminal coupled to the second input voltage protection transistor by a second current path; a control terminal drive voltage source coupled to the control terminals of the first and second input protection transistors; a first feedback path coupled to the control terminal of the first input voltage protection transistor; and a second feedback path coupled to the control terminal of the second voltage protection transistor.

2. The differential input circuit of claim 1, wherein the control terminal drive voltage source includes a control current source and a control transistor coupled to the control current source.

3. The differential input circuit of claim 2, wherein the first feedback path includes a first feedback control component coupled to the control current source and to the control terminal of the of the first input voltage protection transistor.

4. The differential input circuit of claim 2, wherein the second feedback path includes a second feedback control component coupled to the control current source and to the control terminal of the of the second input voltage protection transistor.

5. The differential input circuit of claim 3, wherein the first feedback control component includes a first transistor coupled to a first terminal of the control transistor and the control terminal of the first input voltage protection transistor; and a second transistor coupled between the first transistor and a second terminal of the control transistor.

6. The differential input circuit of claim 5, wherein the first feedback path includes a branched current path, one branch of which includes a third transistor and another branch of which includes a resistor and a fourth transistor coupled to the resistor.

7. The differential input circuit of claim 4, wherein the second feedback control component includes a first transistor coupled to a first terminal of the control transistor and the control terminal of the second input voltage protection transistor; and a second transistor coupled between the first transistor and a second terminal of the control transistor.

8. The differential input circuit of claim 7, wherein the second feedback path includes a branched current path, one branch of which includes a third transistor and another branch of which includes a resistor and a fourth transistor coupled to the resistor.

9. The differential input circuit of claim 1, comprising: a tail current source coupled to a common terminal of the first and second input transistors, wherein another terminal of the first input transistor is a first output terminal of the differential input circuit and another terminal of the second input transistor is a second output terminal of the differential input circuit.

10. The differential input circuit of claim 9, comprising: a first compensating transistor coupled between the second current path and ground; and a second compensating transistor coupled between the first current path and ground.

11. The differential input circuit of claim 1, wherein the first feedback path is coupled to a first current source configured to generate a current having a value of 2I.sub.0, the first feedback path including a first resistor having a set resistance value, and the second feedback path is coupled to a second current source configured to generate a current having a value of 2I.sub.0 and a second resistor having the set resistance value.

12. The differential input circuit of claim 11, wherein a differential input voltage determined by a voltage applied to the control terminal of the first input transistor and a voltage applied to the control terminal of the second input transistor is defined by the product of I.sub.0 and the set resistance value.

13. A differential input circuit, comprising: an input section to which a differential input voltage is applied; a protection section coupled to the input section; a control current source and control transistor coupled to the control current source to control a gate voltage of the protection section; and feedback paths configured to control gate voltages of the input section.

14. The differential input circuit of claim 13, comprising: a compensation section configured to compensate for leakage at gates of the input section.

15. The differential input circuit of claim 14, wherein the compensation section is configured to start to operate when the protection section turns off.

16. The differential input circuit of claim 13, wherein the feedback paths comprise a first feedback path configured to control a first input voltage to the input section, and a second feedback path configured to control a second input voltage to the input section, the differential input voltage being based on the first and second input voltages.

17. The differential input circuit of claim 16, wherein the protection section includes first and second input voltage protection transistors, the first feedback path includes a pair of transistors configured to decrease a drive voltage applied to a control terminal of the first input voltage protection transistor, and the second feedback path includes a pair of transistors configured to decrease a drive voltage applied to a control terminal of the second input voltage protection transistor.

18. A method comprising: applying a differential input voltage to control terminals of input transistors through two current paths, one extending from a first input terminal formed by a terminal of a first input voltage protection transistor to the control terminal of one of the input transistors and the other extending from a second input terminal formed by a terminal of a second input voltage protection transistor to the control terminal of another of the input transistors; controlling a gate drive voltage of the first and second input voltage protection transistors using a control current source and a control transistor coupled to the control current source; and controlling the differential input voltage using multiple feedback paths.

19. The method of claim 18, comprising: decreasing the gate drive voltage of the first and second input voltage protection transistors when the differential input voltage exceeds an offset value.

20. The method of claim 19, comprising: compensating for leakage at the input transistors when the first and second input voltage protection transistors turn off.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Features of the disclosure may be understood from the following figures taken in conjunction with the detailed description.

[0014] FIG. 1 is a circuit diagram of a prior art high voltage differential amplifier.

[0015] FIG. 2 is circuit diagram of another prior art high voltage differential amplifier.

[0016] FIG. 3 is a circuit diagram of still another prior art high voltage differential amplifier.

[0017] FIG. 4 is a circuit diagram of a differential input circuit.

[0018] FIG. 5 is a graph showing control of the differential input voltage at the gates of the input transistors over a range of differential input voltages applied to the drains of protection transistors.

[0019] FIG. 6 is a flow diagram of an example method of operating a differential input circuit, such as that shown in FIG. 4.

[0020] The same reference numbers are used in the drawings to designate the same or similar (structurally and/or functionally) features.

DETAILED DESCRIPTION

[0021] Specific examples are described in detail below with reference to the accompanying figures. These examples are not intended to be limiting. In the drawings, corresponding numerals and symbols generally refer to corresponding parts unless otherwise indicated. The objects depicted in the drawings are not necessarily drawn to scale.

[0022] In example arrangements, the differential input voltage of differential circuits, e.g., differential amplifiers, is limited to improve over-time accuracy of these circuits and the circuits (e.g., op amps and comparators) in which the differential circuits are incorporated. In an example, input transistors that receive a differential input voltage are protected by protection transistors, with their gate drive voltage source implemented by a current source and a control transistor. In an example, feedback paths, one for each input transistor, limit the differential input voltage. In an example, when the differential input voltage rises above an offset value, transistors in each of the feedback loops act to decrease the gate drive voltages of the input voltage protection transistors. In an example, the differential input voltage remains low and well defined by the product of a current value I.sub.0 and a value of a resistor R.sub.0 in each of the feedback loops. In an example, compensating transistors operate to compensate for leakages at the gates of the input transistors when the protection transistors are turned off.

[0023] FIG. 4 is a circuit diagram of an example differential input circuit 400, which may be implemented with complementary metal-oxide-semiconductor (CMOS) technology. Circuit 400 includes first and second input transistors M.sub.0 and M.sub.1, which form an input differential transistor pair. Each of transistors M.sub.0 and M.sub.1 may be a p-type metal-oxide-silicon field-effect transistor (MOSFET). M.sub.0 and M.sub.1 are preferably balanced, have substantially the same threshold voltage, and are oriented to compensate for any slight misalignment during fabrication.

[0024] Transistors M.sub.0 and M.sub.1 and the input voltages applied thereto are protected by transistors M.sub.6 and M.sub.7, respectively. In an example, each of input voltage protection transistors M.sub.6 and M.sub.7 is an n-type MOSFET. A first current path extends between a first differential input terminal (Vin+), which may be a drain of M.sub.6, and a control, e.g., gate, terminal 402 of M.sub.0. Similarly, a second current path extends between a second differential input terminal (Vin−), which may be a drain of M.sub.7, and a control, e.g., gate, terminal 404 of M.sub.1. The drains of input differential transistor pair M.sub.0 and M.sub.1 may be coupled to (+) and (−) terminals of a next stage, which may be a differential amplifier, e.g., an op amp, which may be configured as a linear amplifier, integrator, or other special purpose amplifier as is known in the art. The drain of input transistor M.sub.0 may form a first output terminal 432 of differential input circuit 400, and the drain of input transistor M.sub.1 may form a second output terminal 434 of differential input circuit 400.

[0025] N-type transistors M.sub.6 and M.sub.7 are preferably balanced, and configured to withstand a higher gate-to-drain voltage than input transistors M.sub.0 and M.sub.1. This may be accomplished by, for example, fabricating transistors M.sub.6 and M.sub.7 as drain extended n-type transistors as is known in the art. Alternatively, n-type transistors M.sub.6 and M.sub.7 may be fabricated with a thicker gate dielectric than transistors M.sub.0 and M.sub.1.

[0026] One terminal of a current source 406 is coupled to a supply voltage terminal VDD or positive rail. The other terminal of current source 406 is coupled to control, e.g., gate, terminals 408 and 410 of protection transistors M.sub.6 and M.sub.7, respectively, to a source terminal of a control transistor M.sub.12, which may be a p-type MOSFET, and to drain terminals of transistors M.sub.9 and M.sub.11, each of which may be an n-type MOSFET. The drain of transistor M.sub.12 is coupled to ground. Current source 406, which is configured to deliver a current I.sub.1, and control transistor M.sub.12 form a control, e.g., gate, drive voltage source to provide the gate drive voltage for protection transistors M.sub.6 and M.sub.7.

[0027] A current source 412 coupled at one terminal to VDD and coupled at the other terminal to the source of input transistor M.sub.0 and to the source of input transistor M.sub.1 via the gate of switch transistor M.sub.12. Current source 412 is configured to deliver tail current I.sub.tail to input transistors M.sub.0 and M.sub.1. The delivery terminal of current source 412 is also coupled to the gate of transistor M.sub.11 and to the gate of transistor M.sub.9 via the gate of switch transistor M.sub.12.

[0028] Differential input circuit 400 also includes two current sources 414 and 418, each coupled to VDD and configured to deliver a current 2*I.sub.0. The delivery terminal of current source 414 is coupled to the source of transistor M.sub.2 and to one end of resistor 416, the other end of which is coupled to the source of transistor M.sub.2A. The delivery terminal of current source 418 is coupled to the source of transistor M.sub.3 and to one end of resistor 422, the other end of which is coupled to the source of transistor M.sub.3A. Each of transistors M.sub.2, M.sub.2A, M.sub.3 and M.sub.3A may be a p-type MOSFET. Resistors 416 and 418 may have the same resistance value R.sub.0. In an example, R.sub.0 may be 100 KΩ. In other examples, R.sub.0 may be a different resistance value.

[0029] The source of transistor M.sub.10 is coupled to the source of transistor M.sub.11, and the source of transistor M.sub.8 is coupled to the source of transistor M.sub.9. The drains of transistors M.sub.11 and M.sub.8 are coupled together and to control terminals 408 and 410 of protection transistors M.sub.6 and M.sub.7, respectively. Each of transistors M.sub.10 and M.sub.8 may be a p-type MOSFET.

[0030] A common drain of transistors M.sub.2A, M.sub.3A, M.sub.10 and M.sub.11 is coupled to ground.

[0031] Differential input circuit 400 includes compensating transistors M.sub.4 and M.sub.5, each of which may be a p-type MOSFET. The source of transistor M.sub.4 is coupled to the first current path extending between first differential input terminal Vin+ and the control, e.g., gate, terminal 402 of M.sub.0, and the source of transistor M.sub.5 is coupled to the second current path extending between second differential input terminal Vin− and the control, e.g., gate, terminal 404 of M.sub.1. The drains of transistors M.sub.4 and M.sub.5, through which very small leakage currents (e.g., in the pA range) run, may be coupled to ground. The gate of transistor M.sub.4 is coupled to the gate of transistor M.sub.10 and also coupled to the drain of transistor M.sub.2. The gate of transistor M.sub.5 is coupled to the gate of transistor M.sub.8 and also coupled to the drain of transistor M.sub.3.

[0032] A current source 424 is coupled between the drain of transistor M.sub.2 and ground or a negative supply rail, and current source 426 is coupled between the drain of transistor M.sub.3 and ground or a negative supply rail. Each of current source 424 and 426 is configured to generate a current I.sub.0.

[0033] In operation of differential input circuit 400, the differential input voltage at the gates of input transistors M.sub.0 and M.sub.1 is accurately limited within a relatively narrow range by two feedback paths or loops, one for each of input transistors M.sub.0 and M.sub.1. A first feedback path or loop, which is for input transistor M.sub.0, is formed by transistors M.sub.2, M.sub.2A, M.sub.10 and M.sub.11. A second feedback path or loop, which is for input transistor M.sub.1, is formed by transistors M.sub.3, M.sub.3A, M.sub.8 and M.sub.9. The first feedback path is coupled to control, e.g., gate, terminal 408 of input voltage protection transistor M.sub.6, and the second feedback path is couple to control, e.g., gate, terminal 410 of input voltage protection transistor M.sub.7.

[0034] The first feedback path includes two current path branches, both coupled to current source 414. One branch includes transistor M.sub.2 and the other includes resistor 416 and transistor M.sub.2A coupled to resistor 416. The second feedback path also includes two current path branches, which are coupled to current source 418. One branch includes transistor M.sub.3 and the other includes resistor 422 and transistor M.sub.3A coupled to resistor 422.

[0035] When the input differential voltage at the gates of M.sub.0 and M.sub.1 increases above an offset (e.g., 10-200 mV) of these feedback paths, the voltage defined I.sub.0R.sub.0 and transistor pair M.sub.5-M.sub.9 and/or transistor pair M.sub.10-M.sub.11 start to decrease the gate drive voltages at transistors M.sub.6 and/or M.sub.7 to maintain the input differential voltage at the gates of transistors M.sub.0 and M.sub.1 at a low value and well defined by I.sub.0R.sub.0. Each of transistor pair M.sub.5-M.sub.9 and transistor pair M.sub.10-M.sub.11 act as a feedback control component. As the gate drive voltages of transistors M.sub.6 and M.sub.7 decrease, transistors M.sub.4 and M.sub.5 start operating to compensate for leakage at the gates of transistors M.sub.0 and M.sub.1.

[0036] Each of current sources 406, 412, 414, 418, 424 and 426 in differential input circuit 400 may be implemented as a p-type MOSFET current mirror circuit as is known in the art.

[0037] FIG. 5 is a graph showing control of the differential input voltage at the gates of input transistors M.sub.0/M.sub.1 (δgM0/M1) as the differential input voltage applied at terminals Vin+ and Vin− (δV.sub.in) varies. In this example, I.sub.0 is approximately 1 μA, and R.sub.0 is approximately 100 KΩ. As can be seen, the differential input voltage at input transistors M.sub.0/M.sub.1 remains low and within a relatively narrow range for a wide range of differential input voltages at Vin+ and Vin−.

[0038] FIG. 6 is a flow diagram 600 of an example method of operating a differential input circuit, such as that shown in FIG. 4. An example method includes applying a differential input voltage (e.g., difference between Vin+ and Vin−) to control terminals (e.g., 402 and 404) of input transistors (e.g., M.sub.0 and M.sub.1) through two current paths, one extending from a first input terminal (e.g., Vin+) formed by a terminal of a first input voltage protection transistor (e.g., M.sub.6) to the control terminal (e.g., 402) of one of the input transistors (e.g., M.sub.0) and the other extending from a second input terminal (e.g., Vin−) formed by a terminal of a second input voltage protection transistor (e.g., M.sub.7) to the control terminal (e.g., 404) of another of the input transistors (e.g., M.sub.1). The example method further includes controlling a gate drive voltage of the first and second input voltage protection transistors using a control current source (e.g., 406, I.sub.1) and a control transistor (e.g., Mia) coupled to the control current source, and controlling the differential input voltage using multiple feedback paths (e.g., M.sub.2, M.sub.2A, M.sub.10 and M.sub.11; and M.sub.3, M.sub.3A, M.sub.8 and M.sub.9).

[0039] In an example, the further comprises decreasing the gate drive voltage of the first and second input voltage protection transistors when the differential input voltage exceeds an offset value, which may be in the range of 10-200 mV. In an example, the method further comprises compensating for leakage at the input transistors when the first and second input voltage protection transistors turn off.

[0040] FIG. 6 depicts one possible order of operations in operating a differential input circuit. Not all operations need necessarily be performed in the order described. Some operations may be combined into a single operation. Additional operations may be performed as well.

[0041] Various examples of differential input circuits that improve accuracy by decreasing over-time drift of the differential input voltage offset by accurately limiting the differential input voltage. In examples, feedback paths are incorporated to limit the differential input voltage by a well-defined value, e.g., I.sub.0R.sub.0, and thus set an upper limit that the differential input voltage may reach. Such examples advantageously provide circuits that operate on relatively small differential input voltages while maintaining the input bias current parameter for the downstream differential amplifier low.

[0042] The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A.

[0043] A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

[0044] As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronic or semiconductor component.

[0045] A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.

[0046] While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-type MOSFET may be used in place of an n-type MOSFET, and vice versa, with little or no changes to the circuit. Furthermore, other types of transistors may be used (such as bipolar junction transistors (BJTs)).

[0047] Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

[0048] Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a signal ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means+/−10 percent of the stated value.

[0049] Modifications of the described examples are possible, as are other examples, within the scope of the claims. Moreover, features described herein may be applied in other environments and applications consist with the teachings provided.