SYNAPTIC DEVICE, RESERVOIR COMPUTING DEVICE INCLUDING THE SYNAPTIC DEVICE, AND RESERVOIR COMPUTING METHOD USING THE COMPUTING DEVICE

Abstract

Disclosed is a synaptic device, a reservoir computing device using the synaptic device, and a reservoir computing method using the reservoir computing device. The synaptic device includes a substrate and a plurality of units cells on the substrate, wherein the unit cells each include a channel layer and a first electrode and second electrode intersecting the channel layer, wherein the first electrode and the second electrode are spaced apart from each other, and define a gap region exposing a portion of the channel layer, and the channel layer includes a 2-dimensional semiconductor material or a 2-dimensional ferroelectric material.

Claims

1. A synaptic device comprising: a substrate; and a plurality of units cells on the substrate, wherein the unit cells each comprise a channel layer and a first electrode and second electrode intersecting the channel layer, wherein the first electrode and the second electrode are spaced apart from each other, and define a gap region exposing a portion of the channel layer, and the channel layer comprises a 2-dimensional semiconductor material or a 2-dimensional ferroelectric material.

2. The synaptic device of claim 1, wherein the channel layer has a thickness of about 1 nm to about 50 nm.

3. The synaptic device of claim 1, wherein the 2-dimensional semiconductor material is one of MoS.sub.2, MoSe.sub.2, MoTe.sub.2, WS.sub.2, WSe.sub.2, SnS, SnS.sub.2, graphene oxide, or black phosphorous, and the 2-dimensional ferroelectric material is one of SnS, SnSe, SnTe, InSe, or In.sub.2Se.sub.3.

4. The synaptic device of claim 1, wherein the gap region has a width of about 0.5 μm to about 3 μm.

5. The synaptic device of claim 1, wherein the channel layer has an integrated shape traversing the unit cells.

6. The synaptic device of claim 1, wherein the channel layer is provided in plurality, wherein the channel layers are spaced apart from each other, and a portion of the substrate is exposed therebetween.

7. The synaptic device of claim 1, wherein the channel layer has a characteristic in which a current reduces according to repeated electric pulse signals and a characteristics in which the current increases according to repeated optical pulse signals.

8. The synaptic device of claim 7, wherein the channel layer has a characteristic in which the current changes nonlinearly in response to pulses having the same magnitude and repeated at the same interval.

9. A reservoir computing device comprising: an input signal generation unit configured to generate an input signal corresponding to a learning target pattern; a measurement unit configured to measure a result according to the input signal; and a learning unit configured to learn the learning target pattern through values measured by the measurement unit, wherein the measurement unit comprises: a substrate; and a plurality of units cells on the substrate, wherein the unit cells each comprise a channel layer and a first electrode and second electrode intersecting the channel layer, wherein the first electrode and the second electrode are spaced apart from each other, and define a gap region exposing a portion of the channel layer, and the channel layer comprises a 2-dimensional semiconductor material or a 2-dimensional ferroelectric material.

10. The reservoir computing device of claim 9, wherein the learning target pattern is a consonant, vowel, syllable, word, sentence, nonverbal symbol, picture, or figure.

11. The reservoir computing device of claim 9, wherein the input signal is a signal that changes over time.

12. The reservoir computing device of claim 11, wherein the input signal includes at least one of an electric pulse signal or an optical pulse signal.

13. The reservoir computing device of claim 9, wherein the result according to the input signal, measured by the measurement unit, is an electric conductivity value of the channel layer, which changes according to the input signal.

14. The reservoir computing device of claim 9, wherein the learning target pattern is expressed by a plurality of rows, and each of the plurality of rows is expressed by a plurality of input signals.

15. The reservoir computing device of claim 9, wherein the learning unit uses single-layer perceptron, multi-layer perceptron, random forest, support vector machine, or logistic regression.

16. A reservoir computing method comprising: preparing a learning target pattern; representing the learning target pattern by pulse signals; inputting each of the pulse signals to a memristor; and training with the learning target pattern through conductivity values of the memristor, wherein the memristor comprises a channel layer and a first electrode and second electrode intersecting the channel layer, wherein the first electrode and the second electrode are spaced apart from each other, and define a gap region exposing a portion of the channel layer, and the channel layer comprises a 2-dimensional semiconductor material or a 2-dimensional ferroelectric material.

17. The reservoir computing method of claim 16, wherein each of the pulse signals is a binary pulse signal.

18. The reservoir computing method of claim 16, wherein the representing the learning target pattern by the pulse signals comprises: representing the learning target pattern by a plurality of rows; and representing each of the plurality of rows by the pulse signals.

19. The reservoir computing method of claim 16, wherein the training with the learning target pattern through the conductivity values of the memristor comprises: extracting the conductivity values from a conductivity graph of the memristor; and inputting the conductivity values to a machine learning model.

20. The reservoir computing method of claim 16, wherein the pulse signals include at least one of an electric pulse signal or an optical pulse signal, wherein the electric pulse signal is input through the first electrode or the second electrode, and the optical pulse signal is input through the gap region.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0028] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain principles of the inventive concept. In the drawings:

[0029] FIG. 1 is a conceptual diagram for describing a reservoir computing device according to an embodiment of the inventive concept;

[0030] FIGS. 2A and 2B are perspective views for describing a synaptic device according to embodiments of the inventive concept;

[0031] FIG. 3A is a conceptual diagram for describing a unit cell of a synaptic device according to embodiments of the inventive concept;

[0032] FIGS. 3B, 3C, 3D, and 3E are graphs for describing characteristics of a synaptic device according to embodiments of the inventive concept;

[0033] FIGS. 3F, 3G, and 3H are band diagrams for describing characteristics of a synaptic device according to embodiments of the inventive concept;

[0034] FIGS. 4A and 4B are graphs for describing a result of inputting various input signals to a synaptic device according to embodiments of the inventive concept;

[0035] FIG. 5 is a flowchart for describing a reservoir computing method according to embodiments of the inventive concept;

[0036] FIG. 6A is a conceptual diagram for describing a reservoir computing method according to embodiments of the inventive concept;

[0037] FIG. 6B is a conceptual diagram for describing extraction of conductivity values of a synaptic device in a reservoir computing method according to embodiments of the inventive concept;

[0038] FIGS. 7A and 7B are graphs for describing a result of a reservoir computing method according to embodiments of the inventive concept;

[0039] FIG. 8A is a conceptual diagram for describing examples of a learning target pattern used in a reservoir computing method according to embodiments of the inventive concept; and

[0040] FIGS. 8B and 8C are graphs for describing a result of a reservoir computing method using the learning target patterns shown in FIG. 8A.

DETAILED DESCRIPTION

[0041] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings so that the configuration and effects of the inventive concept are sufficiently understood.

[0042] The inventive concept is not limited to the embodiments described below, but may be implemented in various forms and may allow various changes and modifications. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the accompanying drawings, the scale ratios among elements may be exaggerated or reduced for convenience.

[0043] The terminology used herein is not for limiting the invention but for describing particular embodiments. Furthermore, the terms used herein may be interpreted as the meanings known in the art unless the terms are defined differently.

[0044] The terms of a singular form may include plural forms unless otherwise specified. It will be further understood that the terms “includes”, “including”, “comprises”, and/or “comprising”, when used in this description, specify the presence of stated elements, steps, operations, and/or components, but do not preclude the presence or addition of one or more other elements, steps, operations, and/or components.

[0045] The terms “first”, “second”, and the like are used herein to describe various regions, directions, shapes, etc., but these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish one region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in an embodiment may be referred to as a second part in another embodiment. The embodiments described herein also include complementary embodiments thereof. Like reference numerals refer to like elements throughout.

[0046] Hereinafter, a synaptic device, a reservoir computing device including the synaptic device, and a reservoir computing method using the reservoir computing device according to embodiments of the inventive concept will be described in detail with reference to the drawings.

[0047] FIG. 1 is a conceptual diagram for describing a reservoir computing device according to an embodiment of the inventive concept.

[0048] Referring to FIG. 1, a reservoir computing device according to an embodiment of the inventive concept may include an input signal generation unit 100, a measurement unit 200, and a learning unit 300.

[0049] A signal generated by the input signal generation unit 100 may be a pulse signal. A signal generated by the input signal generation unit 100 may be an electric signal or an optical signal.

[0050] The measurement unit 200 may include the synaptic device as described below with reference to FIGS. 2A and 2B. The synaptic device may include at least one memristor. Here, the memristor is a passive device capable of memorizing an amount of current that passed in the past. The memristor has such characteristics that a tendency of current that flowed in the past is memorized and resistance changes according to the tendency of current.

[0051] The learning unit 300 may be a machine learning model that is trained with learning target patterns through measured values (e.g., conductivity values) measured by the measurement unit 200. The machine learning model may use, for example, a supervised learning technique. The machine learning model may use, for example, techniques such as single-layer perceptron, multi-layer perceptron, random forest, support vector machine, logistic regression, or the like.

[0052] FIG. 2A is a perspective view for describing a synaptic device according to embodiments of the inventive concept.

[0053] Referring to FIG. 2A, a synaptic device (i.e., the measurement unit 200) according to an embodiment of the inventive concept may include a substrate S and a plurality of unit cells UC on the substrate S. The substrate S may be, for example, a semiconductor substrate such as a silicon substrate or a silicon on insulator (SOI) substrate. The substrate S may have an upper surface that is parallel with a first direction D1 and a second direction D2 intersecting the first direction D1 and is perpendicular to a third direction D3. The first to third directions D1 to D3 may be, for example, directions orthogonal to each other.

[0054] Each of the unit cells UC may include a channel layer CL extending in the first direction CL and first and second electrodes EL1 and EL2 intersecting the channel layer CL and extending in the second direction D2. Each of the unit cells UC may be a single memristor.

[0055] The channel layer CL, for example, may have an integrated shape arranged across the plurality of unit cells UC and extending in the first direction D1. A thickness of the channel layer CL in the third direction D3 may be, for example, about 1 nm to about 50 nm. Hereinafter, a thickness may refer to a thickness in the third direction D3. The channel layer CL may include a 2-dimensional semiconductor material or a 2-dimensional ferroelectric material. The 2-dimensional semiconductor material may be, for example, MoS.sub.2, MoSe.sub.2, MoTe.sub.2, WS.sub.2, WSe.sub.2, SnS, SnS.sub.2, graphene oxide, black phosphorous, or the like. The 2-dimensional ferroelectric material may be, for example, SnS, SnSe, SnTe, InSe, In.sub.2Se.sub.3, or the like.

[0056] Each of the first and second electrodes EL1 and EL2 may include a first part spaced apart from the channel layer CL and a second part that is connected to the first part, covers the channel layer CL, and extends in the second direction D2. The first part of the first electrode EL1 may be spaced apart from the first part of the second electrode EL2 with the channel layer CL therebetween. The second part of the first electrode EL1 and the second part of the second electrode EL2 may be spaced apart from each other in the first direction D1. A gap region G, which exposes at least a portion of the channel layer CL, may be defined by the second part of the first electrode EL1 and the second part of the second electrode EL2. A width of the gap region G in the first direction D1 may be about 0.5 μm to about 3 μm. In each of the first and second electrodes EL1 and EL2, a thickness of the second part may be smaller than a thickness of the first part. A portion of the second part of each of the first and second electrodes EL1 and EL2 may contact the upper surface of the substrate S. However, this is merely an example, and each of the first and second electrodes EL1 and EL2 may have various shapes that contact the channel layer CL and define the gap region G. The first and second electrodes EL1 and EL2 may include a conductive material such as metal or the like. For example, the first and second electrodes EL1 and EL2 may include gold (Au) or chromium (Cr).

[0057] A first input signal IS1 and a second input signal IS2 may be input to each of the unit cells UC. The first input signal IS1 may be an electric pulse signal input through one of the first electrode EL1 and the second electrode EL2. The second input signal IS2 may be an optical pulse signal input through a portion of the channel layer CL exposed by the gap region G between the first electrode EL1 and the second electrode EL2. The second input signal IS2, for example, may have a wavelength selected from a wavelength band of about 400 nm to about 850 nm.

[0058] FIG. 2B is a perspective view for describing a synaptic device according to embodiments of the inventive concept. Hereinafter, for convenience, descriptions that are substantially the same as those provided above with reference to FIG. 2A will not be provided, and differences therebetween will be described in detail.

[0059] Referring to FIG. 2B, the channel layer CL on the substrate S may be provided in plurality. Each of the channel layers CL may intersect the first electrode EL1 and the second electrode EL2. The channel layers CL may be spaced apart from each other in the first direction DE A portion of the substrate S may be exposed between the channel layer CL.

[0060] FIG. 3A is a conceptual diagram for describing a unit cell of a synaptic device according to embodiments of the inventive concept. FIGS. 3B, 3C, 3D, and 3E are graphs for describing characteristics of a synaptic device according to embodiments of the inventive concept.

[0061] Referring to FIG. 3A, the unit cell UC of a synaptic device according to an embodiment of the inventive concept may include the channel layer CL and the first and second electrodes EL1 and EL2 connected thereto. Each of the first and second electrodes EL1 and EL2 may cover a portion of the channel layer CL.

[0062] FIGS. 3A and 3B illustrate voltage-current (V-I) graphs corresponding to a result of performing, multiple times, a trial in which a voltage applied between the first electrode EL1 and the second electrode EL2 of the unit cell UC is decreased after being increased. Here, a unit of voltage is V, and a unit of current is μA. As a result of first to eighth trials T1 to T8, a current for the same voltage reduces as the number of repetitions of the trial is increased, which indicates that the channel layer CL exhibits synaptic plasticity (or memristor characteristic). Hereinafter, a current (or photocurrent) represents a current flowing through the channel layer CL, and is measured by the first electrode EL1 or the second electrode EL2.

[0063] FIG. 3C illustrates a graph showing a current change over time when the first input signal IS1 is input. Here, a unit of time is second (s), a unit of voltage is V, and a unit of current is μA. The first input signal IS1, for example, is a pulse signal having a pulse voltage of about 4.5 V, a pulse width of about 20 ms, and a pulse repetition interval (PRI) of about 30 ms. As a result of inputting the first input signal IS1 for about 0.75 s, the current reduces over time, and this result matches FIG. 3B.

[0064] FIG. 3D illustrates a graph showing a current change over time when the second input signal IS2 is input. Here, a unit of time is second (s), and a unit of current is μA. The second input signal IS2, for example, is a pulse signal having a wavelength of about 725 nm, pulse power of about 43 mW, and a pulse repetition interval of about 3 s. Here, a read voltage of about 0.5 V may be applied between the first electrode EL1 and the second electrode EL2 to measure a current induced by the second input signal IS2. As a result of inputting the second input signal IS2 for about 120 s, the current increases over time, and this result is opposite to FIGS. 3B and 3C.

[0065] Referring to FIGS. 3C and 3D, a current change according to the first input signal IS1 or the second input signal IS2 may be nonlinear. Namely, the current may change nonlinearly even if pulses having the same magnitude are repeated at the same interval.

[0066] FIG. 3E illustrates a graph showing a change in normalized photocurrent when pulse trains that are similar to the second input signal IS2 described with reference to FIG. 3D but have different wavelengths are input. The synaptic device according to an embodiment of the inventive concept exhibits a result matching FIG. 3D in at least a wavelength band of about 400 nm to about 850 nm.

[0067] FIGS. 3F, 3G, and 3H are band diagrams for describing characteristics of a synaptic device according to embodiments of the inventive concept. A reason why FIGS. 3B and 3C and FIG. 3D show opposite tendencies will be described with reference to FIGS. 3F, 3G, and 3H. Here, the channel layer CL includes, for example, p-type SnS.

[0068] FIG. 3F illustrates a band diagram of the channel layer CL that is in an equilibrium state. Here, a bias voltage V.sub.d applied between the first electrode EL1 and the second electrode EL2 may be lower than a threshold voltage V.sub.th, and an acceptor state E.sub.a may be filled with electrons.

[0069] FIG. 3G illustrates a band diagram of the channel layer CL when the bias voltage V.sub.d applied between the first electrode EL1 and the second electrode EL2 is higher than the threshold voltage V.sub.th (i.e., when an electric pulse signal such as the first input signal IS1 is applied). Here, portion of the electrons trapped in the acceptor state E.sub.a may recombine with holes, and thus a current in the channel layer CL may reduce.

[0070] FIG. 3H illustrates a band diagram of the channel layer CL when the bias voltage V.sub.d applied between the first electrode EL1 and the second electrode EL2 is lower than the threshold voltage V.sub.th, but an optical pulse signal such as the second input signal IS2 is input. Here, the electrons of the acceptor state E.sub.a may be excited and trapped in a donor state E.sub.d, and holes may be further generated from a valence band, and thus conductivity of the channel layer CL may increase. This phenomenon is referred to as a photo-gating effect.

[0071] FIGS. 4A and 4B are graphs for describing a result of inputting various input signals to a synaptic device according to embodiments of the inventive concept.

[0072] Referring to FIGS. 2A and 4A, a graph is described, which shows a read current change over time when the first input signals IS1 are input to the unit cell UC of the synaptic device according to an embodiment of the inventive concept. Here, a unit of time is second (s), and a unit of current is nA.

[0073] Each of the first input signals IS1 may include five signals input sequentially. Here, each of the five signals represents ‘1’ or ‘0’. A signal representing ‘1’, for example, is an electric pulse having a pulse voltage of about 4 V and a pulse width of about 50 ms. A period of the five signals is about 100 ms or less.

[0074] Referring to FIG. 4A, the first input signals IS1 may be binary pulse signals such as (00100), (01001), (01010), (11111), (11101), and (01110). The current reduces when a signal representing ‘1’ appears in the first input signals IS1. This is because portion of the electrons trapped in the acceptor state E.sub.a recombine with holes and are detrapped, as described above with reference to FIG. 3G. The current starts to increase when a signal representing ‘0’ appears in the first input signals IS1. This is because the electrons are trapped again in the acceptor state E.sub.a as described above with reference to FIG. 3F.

[0075] As described above with reference to FIG. 3C, since a current change according to each of the first input signals IS1 is nonlinear, final current amplitudes achieved after finishing inputting each of the first input signals IS1 may be different from each other.

[0076] Referring to FIGS. 2A and 4B, a graph is described, which shows a read current change over time when the second input signals IS2 are input to the unit cell UC of the synaptic device according to an embodiment of the inventive concept. Here, a unit of time is second (s), and a unit of current is nA.

[0077] Each of the second input signals IS1 may include five signals input sequentially. Here, each of the five signals represents ‘1’ or ‘0’. A signal representing ‘1’, for example, is an optical pulse having a wavelength of about 725 nm, pulse power of about 42 mW, and a pulse width of about 5 s. A period of the five signals is about 3 s.

[0078] Referring to FIG. 4B, the second input signals IS2 may be binary pulse signals such as (00100), (01001), (01010), (01110), (11101), and (11111). The current increases when a signal representing ‘1’ appears in the second input signals IS2. This is caused by a photo-gating effect in which the electrons of the acceptor state E.sub.a are excited and trapped in the donor state E.sub.d, and holes are further generated from a valence band, as described above with reference to FIG. 3H. The current starts to decrease when a signal representing ‘0’ appears in the second input signals IS2. This is because the electrons are trapped again in the acceptor state E.sub.a as described above with reference to FIG. 3F.

[0079] As described above with reference to FIG. 3D, since a current change according to each of the second input signals IS2 is nonlinear, final current amplitudes achieved after finishing inputting each of the second input signals IS2 may be different from each other.

[0080] FIG. 5 is a flowchart for describing a reservoir computing method according to embodiments of the inventive concept.

[0081] Referring to FIG. 5, a reservoir computing method according to an embodiment of the inventive concept may include preparing learning target patterns (S100), representing each of the learning target patterns by electric pulse signals and/or optical pulse signals (S200), inputting each of the pulse signals to a memristor (S300), and training with each of the learning target patterns through conductivity values (or current values) of the memristor (S400). The reservoir computing method according to an embodiment of the inventive concept will be described in more detail with reference to FIGS. 6A and 6B.

[0082] Here, reservoir computing (RC) is one of learning algorithms for learning data that changes over time, and uses a scheme of projecting (i.e., mapping) information of an input signal according to time to a high-dimensional space by using a reservoir having a short-term memory characteristic and nonlinear function characteristic. In the reservoir computing, since only an input/output function is required to be learned, a network to be trained may be minimized, and thus a signal that changes over time may be learned and analyzed with relatively low energy and low cost.

[0083] FIG. 6A is a conceptual diagram for describing a reservoir computing method according to embodiments of the inventive concept. FIG. 6B is a conceptual diagram for describing extraction of conductivity values of a synaptic device in a reservoir computing method according to embodiments of the inventive concept.

[0084] Referring to FIGS. 5A and 6A, learning target patterns P may be prepared (S100). The learning target patterns P may be, for example, Korean consonants and vowels. However, this is merely an example, and the learning target patterns P may be syllables, words, or sentences of Korean language, alphabets, words, or sentences of other languages, or nonverbal symbols, pictures, or figures. A learning process for Korean consonant “” among the plurality of learning target patterns P will be described as an example with reference to FIG. 6A.

[0085] Thereafter, each of the learning target patterns P may be expressed by electric pulse signals and/or optical pulse signals (S200). Representing each of the learning target patterns P by electric pulse signals and/or optical pulse signals (S200) may include representing each of the learning target patterns P by a plurality of rows (or columns) and representing each of the plurality of rows by an electric pulse signal and/or optical pulse signal. According to embodiments, each of the learning target patterns P may be expressed by a single matrix.

[0086] “”-shaped pattern, for example, may be expressed by first to fifth rows R1 to R5. The first to fifth rows R1 to R5 may be expressed by a plurality (e.g., five) of input signals IS. Each of the input signals IS may be a binary pulse signal. Each of the input signals IS may be an electric signal or optical signal. The first to fifth rows R1 to R5 of the “”-shaped pattern, for example, may be expressed by input signals IS such as (11111), (10000), (11111), (10000), and (11111).

[0087] Thereafter, each of the input signals IS may be input to a memristor M of the measurement unit 200. The memristor M may correspond to a reservoir having a short-term memory characteristic and nonlinear function characteristic. The memristor M may correspond to the unit cell UC of the measurement unit 200 described with reference to FIGS. 1 and 2A.

[0088] Thereafter, training may be performed with each of the learning target patterns P through conductivity values of the memristor M (S400). Training with each of the learning target patterns P through conductivity values of the memristor M (S400) may include extracting the conductivity values from a conductivity graph EC of the memristor M and inputting the conductivity values to a machine learning model. For example, each of the input signals IS of the “”-shaped pattern may change electric conductivity of the memristor M, and a plurality of conductivity values may be extracted from the conductivity graph EC of the memristor relative to time.

[0089] Referring to FIGS. 6A and 6B, the conductivity graph EC is described, which is changed according to the signal (11111) (i.e., signal corresponding to any one of the first row R1, the third row R3, and the fifth row R5 of the “”-shaped pattern) among the input signals IS. A plurality of conductivity values may be extracted from the conductivity graph EC. The plurality of conductivity values may include an initial conductivity value C.sub.i and first to fifth pulse conductivity values C.sub.1 to C.sub.5 which change according to the signal (11111). The first pulse conductivity value C.sub.1 may be greater than the initial conductivity value C.sub.i. Conductivity values may decrease from the first pulse conductivity value C.sub.1 to the fifth conductivity value C.sub.5.

[0090] The machine learning model may correspond to the learning unit 300 described with reference to FIG. 1. The learning unit 300 may include a plurality of layers. Each of the plurality of layers may include a plurality of nodes, wherein the nodes may have a weight and may be connected to each other. For example, the learning unit 300 may include an input layer IL and an output layer OL. The learning unit 300 may further include at least one additional layer between the input layer IL and the output layer OL. The initial conductivity value C.sub.i and the first to fifth pulse conductivity values C.sub.1 to C.sub.5 may be input to the input layer IL of the learning unit 300.

[0091] FIGS. 7A and 7B are graphs for describing a result of a reservoir computing method according to embodiments of the inventive concept.

[0092] Referring to FIGS. 6A and 7A, a graph is described, which shows accuracy according to an epoch number when the first input signal IS1 that is an electric pulse signal is used as a signal indicating the learning target patterns P and when the second input signal IS2 that is an optical pulse signal is used. Here, the epoch number represents the number of repetitions of machine learning performed in the machine learning unit 300, and the accuracy represents classification accuracy for the learning target patterns P. When the first input signal IS1 is used, the accuracy of at least about 0.9 (i.e., 90%) may be obtained when the epoch number is at least about 50. When the second input signal IS2 is used, the accuracy of at least about 0.9 (i.e., 90%) may be obtained when the epoch number is at least about 75.

[0093] Referring to FIGS. 6A and 7B, a graph is described, which shows current measured as a result of inputting different binary pulse signals. Here, a unit of current is nA. Currents measured as a result of inputting different binary pulse signals to the memristor M are different from each other, and this result is caused by the short-term memory characteristic and nonlinear function characteristic of the memristor M. Therefore, the learning unit 300 may learn and analyze a signal that changes over time, such as the learning target patterns P, with relatively low energy and low cost.

[0094] FIG. 8A is a conceptual diagram for describing examples of a learning target pattern used in a reservoir computing method according to embodiments of the inventive concept. FIGS. 8B and 8C are graphs for describing a result of a reservoir computing method using the learning target patterns shown in FIG. 8A.

[0095] Referring to FIG. 8A, the learning target patterns P may be 2-syllable Korean words such as “” (Let's go), “” (Get out), “” (Let's buy), “” (Let's ride), and “” (Kick). Each of the learning target patterns, for example, may be expressed by first to fifth rows R1 to R5. The first to fifth rows R1 to R5 may be expressed by a plurality (e.g., five) of input signals IS. Each of the input signals IS may be a binary pulse signal.

[0096] FIG. 8B illustrates a graph showing the accuracy according to the epoch number when learning the learning target patterns P of FIG. 8A by using a reservoir computing method according to an embodiment of the inventive concept. Here, an electric pulse signal is used as a signal indicating the learning target patterns P, and the accuracy of at least about 0.9 (i.e., 90%) may be obtained when the epoch number is at least about 80.

[0097] FIG. 8C illustrates a graph showing a loss according to the epoch number. Here, the loss represents a cross entropy loss of machine learning, and decreases as the epoch number increases.

[0098] According to a reservoir computing method according to an embodiment of the inventive concept, since only an input/output function is required to be learned, a network to be trained may be minimized, and thus a signal that changes over time may be learned and analyzed with relatively low energy and low cost.

[0099] Although the embodiments of the present invention have been described, it is understood that the present invention should not be limited to these embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the present invention as hereinafter claimed.