Coherent Phase-Synchronizing Circuit

Abstract

Embodiments of the invention provide advances in liquid-crystal technology for use as tunable phase-delay lines. The amount of phase delay through the liquid crystal is adaptively tuned, in order to coherently combine two signals, regardless of their phase differences. By adaptively adjusting the phase delays in the two signal paths, maximum coherent power combining is ensured. This ability to coherently combine the power of two signals regardless of their initial phase differences can greatly simplify, for example, antenna-diversity techniques used in MIMO applications as well as other applications.

Claims

1. A circuit for coherent phase-synchronization configured to automatically synchronize phases of a first and second signal that are out of phase with respect to one another, the circuit comprising: a first liquid crystal voltage-controlled delay line configured to receive the first signal and propagate the first signal to a first output; a second liquid crystal voltage-controlled delay line configured to receive the second signal and propagate the second signal to a second output; a mixer configured to multiply the first and second signals to produce a phase-difference induced direct current (DC) voltage; a first transistor; a second transistor; a first integrator; and a second integrator, wherein the DC voltage produced by the mixer causes an imbalance in the conduction of the first and second transistors, and wherein the imbalance in the conduction causes a higher voltage of the imbalance to be applied to one of the first and second liquid crystal voltage-controlled delay lines decreasing a propagation velocity through the liquid crystal voltage controlled delay line, and wherein the imbalance in the conduction causes a lower voltage of the imbalance to be applied to the other of the first and second liquid crystal voltage-controlled delay lines increasing a propagation velocity through the liquid crystal voltage-controlled delay line, and wherein the first and second integrators are configured to hold the applied voltages to the respective first and second liquid crystal voltage-controlled delay lines.

2. The circuit of claim 1, wherein the first and second liquid crystal voltage-controlled delay line comprises a signal path passing through each respective liquid crystal.

3. The circuit of claim 2, wherein the signal paths comprise a co-planar waveguide, stripline, microstrip, or any other transmission line that passes through a liquid-crystal medium.

4. The circuit of claim 1, wherein the mixer additionally produces a high-frequency voltage, the circuit further comprising: a low pass filter configured to eliminate the high-frequency voltage.

5. A method for automatically synchronizing phases of a first and a second signal that are out of phase with respect to one another, the method comprising: receiving the first signal by a first liquid crystal voltage-controlled delay line configured to propagate the first signal to a first output; receiving a second signal by a second liquid crystal voltage-controlled delay line configured to propagate the second signal to a second output; detecting a phase difference between the first signal and second signal; applying an increasing voltage to one of the first or second liquid crystal voltage-controlled delay line to decrease propagation of the first or second signal; simultaneously applying a decreasing voltage to the other of the first or second liquid crystal voltage-controlled delay lines to increase propagation of the other of the first or second signal; and holding voltage levels of the first and second liquid crystal voltage-controlled delay lines when the detected phase difference goes to zero.

6. A method for automatically synchronizing phases of a first and second signal that are out of phase with respect to one another, the method comprising: receiving the first signal by a first liquid crystal voltage-controlled delay line configured to propagate the first signal to a first output; receiving the second signal by a second liquid crystal voltage-controlled delay line configured to propagate the second signal to a second output; multiplying the first and second signals with a mixer to produce a phase-difference induced direct current (DC) voltage, wherein the DC voltage produced by the mixer causes an imbalance in the conduction of a first and a second transistor; applying a higher voltage of the imbalance to one of the first and second liquid crystal voltage-controlled delay lines decreasing a propagation velocity through the liquid crystal voltage controlled delay line; applying a lower voltage of the imbalance to the other of the first and second liquid crystal voltage-controlled delay lines increasing a propagation velocity through the liquid crystal voltage-controlled delay line; and holding the applied voltages to the first and second liquid crystal voltage-controlled delay lines with a respective first and second integrator.

7. The method of claim 6, wherein the mixer additionally produces a high-frequency voltage, the circuit further comprising: eliminating the high-frequency voltage with a low pass filter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above, and the detailed description given below, serve to explain the invention.

[0009] FIG. 1 is schematic of an exemplary embodiment a coherent phase-synchronizing circuit using voltage-controlled liquid-crystal delay lines;

[0010] FIGS. 2A-2C are diagrams depicting a liquid crystal with parallel polarization (no applied voltage), a partial polarization, and transverse polarization (maximum applied voltage), respectively;

[0011] FIG. 3 is a graph of phase change;

[0012] FIG. 4 is a graph of applied voltage vs. electrical phase delay of liquid crystal delay lines;

[0013] FIGS. 5A-5D are simulated outputs of two signals that are 90-degrees out of phase, as the liquid crystal delay-line circuit automatically brings them into phase synchronization at times of less than 0.5 ms, 2 ms, 3 ms, and 4 ms respectively; and

[0014] FIG. 6 is a schematic of an alternate open-loop embodiment of a coherent phase-synchronizing circuit using voltage controlled liquid-crystal delay lines.

[0015] It should be understood that the appended drawings are not necessarily to scale, presenting a somewhat simplified representation of various features illustrative of the basic principles of the invention. The specific design features of the sequence of operations as disclosed herein, including, for example, specific dimensions, orientations, locations, and shapes of various illustrated components, will be determined in part by the particular intended application and use environment. Certain features of the illustrated embodiments have been enlarged or distorted relative to others to facilitate visualization and clear understanding. In particular, thin features may be thickened, for example, for clarity or illustration.

DETAILED DESCRIPTION OF THE INVENTION

[0016] Polarization properties of liquid crystals allow for their use as tunable phase-delay lines for the purpose of coherently combining two signals with arbitrary phases. Applied DC voltages change the permittivity of the liquid crystal, which in turn changes the propagation delay. A feedback network can be constructed which adaptively increases the delay in the leading signal path, while simultaneously decreasing the delay in the lagging path. The two signals are brought in phase with each other, and then combined coherently in a power combiner.

[0017] Embodiments of the invention provide a coherent phase-synchronizing circuit that automatically synchronizes phases of two signals that are out of phase with each other, using liquid crystal as voltage-controlled delay lines. An exemplary embodiment, as shown in FIG. 1, include two delay lines LC1, LC2 through a liquid-crystal medium 10, 12. These delay lines consist of signal paths passing through the liquid crystal, which may be a co-planar waveguide, stripline, micros trip, or any other transmission line that passes through the liquid-crystal medium. The two input signals may be multiplied together using a mixer 14, which produces a phase-difference induced direct-current (DC) voltage, as well as a high-frequency voltage. Since only the DC term is used for phase detection, the high-frequency term may be eliminated with a simple passive low-pass filter, represented by L3 and C7 in FIG. 1. This DC voltage is applied to the base of transistor, Q2 in the differential-pair amplifier shown in FIG. 1. Alternatively, in some embodiments, a MOSFET version of this differential pair could also be used. The Q2 base voltage is compared with the base voltage of Q1, which is held to 0 Volts by the connection to ground. When the phases between the two signals are equal, the DC voltage at the output of the multiplier is 0 Volts, and there is no voltage difference between the two transistor inputs. As a result, the voltages applied to the two liquid-crystal delay lines are equal.

[0018] However, any difference in phase will cause the DC voltage at the multiplier output to either be positive or negative, depending on which phase is leading and which is lagging. The 90-degree phase shifter 16 in FIG. 1 makes this positive and negative voltage possible by creating the sine of the phase difference, rather than the cosine. This DC voltage causes an imbalance in the conduction of the two transistors, Q1 and Q2, causing one of the collector voltages to decrease and the other to increase. The signal path with the leading phase will propagate through the liquid-crystal delay line that has the increasing applied voltage. The higher applied voltage causes the liquid crystal to be more polarized, as shown by increasing in FIGS. 2A-2C, which increases its permittivity, thus decreasing the propagation velocity through this delay line. Simultaneously, the signal with the lagging phase propagates through the liquid-crystal delay line with the decreasing voltage, which causes the permittivity in the liquid crystal to decrease, thus increasing the propagation velocity through this delay line. Therefore, the leading signal is slowed as the lagging signal is advanced until they are brought into phase synchronization. At that point, the corrective voltage at the output of the multiplier returns to 0 Volts. Two integrators, in the form of passive low-pass filters (L1, C8 and L2, C9 in FIG. 1) hold the applied voltages that caused the two phases to be synchronized. These integrator voltages are constantly adjusted by the output voltages of the differential-pair amplifier, which are controlled by the correcting output voltage of the multiplier. Alternately, in some embodiments, active integrators using operational amplifiers may also be used for this purpose. Transistors, Q3 and Q4 are simply used as a current source for the differential pair in the illustrated embodiment.

[0019] Nematic liquid crystals have been used in phase delay lines and may be used with embodiments of the invention, though other types of liquid crystals may also be used. FIGS. 2A-2C illustrate the polarization of liquid-crystal molecules 18, as an electric field is applied. By adaptively controlling the applied field, the polarization, and therefore permittivity, propagation velocity, and phase delay can be controlled. A simplified model for the orientation angle in FIGS. 2A-C can be written as

[00001]$\begin{array}{cc}=\left\{\begin{array}{cc}\frac{}{2}-2.Math..Math.{\tan }^{-1}\left[e^{-\left(V-V_C\right)/V_0}\right]& V>V_C\\ 0& V<V_C\end{array}\right\}& \left(1\right)\end{array}$

where V.sub.C is the threshold voltage-per-micron of thickness that is required to begin orienting the liquid crystal, V is the applied voltage, and V.sub.0 is a constant. The effective permittivity can be determined from

[00002]$\begin{array}{cc}{\mathrm{.Math.}}_{\mathrm{eff}}=\frac{{\mathrm{.Math.}}_p.Math.{\mathrm{.Math.}}_t}{{\cos \left(\right)}^2.Math.{\mathrm{.Math.}}_t+{\sin \left(\right)}^2.Math.{\mathrm{.Math.}}_p}& \left(2\right)\end{array}$

where .sub.p and .sub.t are the parallel (no applied field) and transverse (maximum applied field) permittivities, respectively. This difference in polarization yields a phase difference of

[00003]$\begin{array}{cc}=\frac{2.Math.}{}.Math.d.Math.\sqrt{.Math..Math.{\mathrm{.Math.}}_{\mathrm{eff}}}& \left(3\right)\end{array}$

where .sub.eff=.sub.eff.sub.p is the applied field-dependent change in permittivity, is the signal wavelength in a vacuum, and d is the length of the delay line. The phase response defined in equations (1)-(3) is represented by curve in FIG. 3 as phase in degrees vs. applied voltage with f=5 GHz, V.sub.0=5, V.sub.c=2, and d=5 cm.

[0020] As set forth above, the applied DC voltage, required to tune the liquid crystal delay lines, can be supplied with the exemplary circuit in FIG. 1. This circuit detects the phase difference between two signal paths and creates opposing DC voltages based on the difference between the two phases. One of the directional coupler outputs are shifted by 90 in order to produce the multiplier output

sin(2t)+sin()(4)

where is the phase difference between the two channels. Again, as set forth above, the left sinusoidal term in (4) is low-pass filtered, leaving only a DC voltage that is proportional to sin() at the base of the right-most differential-amplifier transistor in FIG. 1. If there were no phase difference between the two signals, this DC term in (4) would be zero, and both diff-amp collector voltages would be equal, providing equal voltages to the two integrator inputs. As a result, the two liquid crystal delay lines would be equally biased. However, any phase difference would drive one of the differential-amplifier collectors high and the other low, reducing the delay in the lagging signal path, while increasing the delay in the leading path, following the transfer curves in FIG. 4. The purpose of the integrators is to hold those DC voltages as the mixer output returns to zero, due to the equalized phases. The common-emitter amplifiers scale the DC voltages to the required level in order for the liquid crystal to achieve 90 of tuning range in both delay lines.

[0021] When one signal path leads the other, its applied DC voltage will be increased, increasing the permittivity of the liquid crystal, thus decreasing the phase velocity by

[00004]$\begin{array}{cc}{v}_p=\frac{c}{\sqrt{{\mathrm{.Math.}}_{\mathrm{eff}}}}& \left(5\right)\end{array}$

[0022] As a result, the phase delay of this path will increase according to the phase vs. voltage relationship in FIG. 3. Simultaneously, the DC voltage that is applied to the opposite delay line will decrease, decreasing its permittivity, and thus decreasing the phase delay of the lagging path. As the leading signal is delayed and the lagging signal is advanced, the two signals are driven into phase and are coherently combined in, for example, a Wilkinson power combiner illustrate at the right in FIG. 1. As long as the two signals remain in phase, their respective delay lines will remain biased at these appropriate voltages, resulting in equal delay. Any phase drift will result in self-correcting DC biases.

[0023] It may be assumed for the embodiments of the invention that both channels have useable SNR. If one of the channels has unusable SNR, then the combiner would degrade the performance compared to the best channel. However, even such degradation of the combined signals would be preferable to only receiving one of the signals, if that received signal happened to be the one with the unusable SNR.

[0024] As proof of the circuit's functionality, this circuit was simulated using MULTISIM by National Instruments. The table below provides the values of the circuit elements in FIG. 1 used for the simulation.

TABLE-US-00001 TABLE 1 Circuit Element Values C1 0.1 F C2 0.1 F C3 0.1 F C4 0.1 F C5 0.1 F C6 0.1 F C7 0.1 F C8 10 F C9 10 F L1 10 mH L2 10 mH L3 10 mH R1 1 k R2 1 k R3 0 R4 0 R5 10 R6 100 R7 1 k R8 50 R9 100

[0025] V1.sub.OUT and V2.sub.OUT were determined across two 50 resistors. Since no MULTISIM model yet exists for the voltage-controlled liquid-crystal delay lines, behavior models were created to convert applied voltage into time delay. FIGS. 5A-5D compare the two output signals (V1.sub.OUT and V2.sub.OUT in FIG. 1), over time (Os, 0.4 ms, 2 ms, 3 ms, and 4 ms), as input, V1.sub.IN lags input, V2.sub.IN by 90 degrees. As FIGS. 5A-5D indicate, the two signals are automatically brought into phase within 4 ms of the start of the simulation.

[0026] An advantage of the embodiments of the invention utilizing this liquid-crystal phase-synchronizing circuit over a traditional PLL is the elimination of the need for a VCO, which is an active device. In contrast, the liquid-crystal delay line is passive, requiring no applied power. Since liquid crystal does not conduct electrical current, the voltage that is applied to the liquid crystal does not dissipate power. The only active components are in the differential-pair amplifier. The multiplier 14 may also be implemented with passive components.

[0027] The embodiment of the circuit in FIG. 1 uses a negative-feedback closed loop to lock the phases of the two signals together. An alternative configuration that may be implemented in other embodiments of the invention is to use an open-loop design, without feedback, such as the embodiment shown in FIG. 6. An advantage of this open-loop design is that it may be a simpler configuration to implement. However, the open-loop design may require more careful calibration of component values in order to achieve the same phase correction. An advantage of the closed-loop embodiment in FIG. 1 is that it is self-correcting. The closed-loop embodiment will automatically keep the phases locked, while adjusting for slight variations in component values, including manufacturing tolerances, temperature, etc.

[0028] While the present invention has been illustrated by a description of one or more embodiments thereof and while these embodiments have been described in considerable detail, they are not intended to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. The invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative examples shown and described. Accordingly, departures may be made from such details without departing from the scope of the general inventive concept.