FPGA Clock Signal Self-detection Method

Abstract

An FPGA clock signal self-detection method relates to the technical field of control module, and the technical problem to be solved is to improve operational reliability and safety of the FPGA chip. The method comprises introducing two clock signals to an FPGA chip, wherein one clock signal is a first clock signal, and the other clock signal is a second clock signal; using the first clock signal to control all synchronous logic operations in the FPGA chip, and using the second clock signal to detect the first clock signal for correctness. The method of the invention is particularly applicable to a system with the FPGA chip as a main controller or important control unit.

Claims

1. An FPGA clock signal self-detection method, characterized by comprising introducing two clock signals to an FPGA chip, wherein one clock signal is a first clock signal, and the other clock signal is a second clock signal; using the first clock signal to control all synchronous logic operations in the FPGA chip, and using the second clock signal to detect the first clock signal, comprising the following steps: detecting the first clock signal once when the second clock signal goes through every N cycles; if the number of cycles that the first clock signal goes through within such period of time is less than A or more than B, judging that the first clock signal has an error; wherein N is a preset threshold of cycle number, A is a preset lower limit of cycle number, and B is a preset upper limit of cycle number.

2. The FPGA clock signal self-detection method according to claim 1, characterized in that frequency of the first clock signal is different from that of the second clock signal.

3. The FPGA clock signal self-detection method according to claim 2, characterized in that the frequency of the first clock signal is higher than that of the second clock signal.

4. The FPGA clock signal self-detection method according to claim 3, characterized in that the frequency of the first clock signal is 50 MHZ, and the frequency of the second clock signal is 19.6608 MHZ (N=65536, A=166654, B=166680).

Description

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0013] The technical solution of the invention is described in detail in combination with the embodiment which is not used to limit the invention. Any structures and changes similar to the invention should be incorporated in the protection scope of the invention.

[0014] An FPGA clock signal self-detection method provided by the embodiment of the invention is characterized by comprising introducing two clock signals to an FPGA chip, wherein one clock signal is a first clock signal, and the other clock signal is a second clock signal;

[0015] using the first clock signal to control all synchronous logic operations in the FPGA chip, and using the second clock signal to detect the first clock signal, comprising the following steps:

[0016] detecting the first clock signal once when the second clock signal goes through every N cycles; if the number of cycles that the first clock signal goes through within such period of time is less than A or more than B, judging that the first clock signal has an error;

[0017] wherein N is a preset threshold of cycle number, A is a preset lower limit of cycle number, and B is a preset upper limit of cycle number.

[0018] In the embodiment of the invention, frequency of the first clock signal is different from that of the second clock signal, wherein the frequency of the first clock signal is 50 MHZ, and the frequency of the second clock signal is 19.6608 MHZ (N=65536, A=166654, B=166680).

[0019] The embodiment of the invention is particularly applicable to a system with the FPGA chip as a main controller or important control unit.