INTEGRATED CIRCUIT DIE HAVING A SPLIT SOLDER PAD

Abstract

The invention relates to an electronic system comprising: an integrated circuit die having: at least 2 bond pads a redistribution layer, said redistribution layer having: at least a solder pad comprising 2 portions arranged to enable an electrical connection between each other by a same solder ball placed on said solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least 2 redistribution wires, each one connecting one of the 2 portions to one of the 2 bond pads,
a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to testing said integrated circuit die a grounded printed circuit board track, a solder ball being placed between the solder pad and the printed circuit board track.

Claims

1. An electronic system comprising: an integrated circuit die having: at least 2 bond pads a redistribution layer, said redistribution layer having: at least a solder pad comprising 2 portions arranged to enable an electrical connection between each other by a same solder ball placed on said solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least 2 redistribution wires, each one connecting one of the 2 portions to one of the 2 bond pads, a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to testing said integrated circuit die a grounded printed circuit board track, a solder ball being placed between the solder pad and the printed circuit board track.

2. The electronic system according to the previous claim, wherein the portions have a shape of a demi-disk.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Other features and advantages of the present invention will appear more clearly upon reading the following detailed description, made with reference to the annexed drawings given by way of non-limiting examples:

[0012] FIG. 1 schematically illustrates a top view of a classical wire-bond package

[0013] FIG. 2 schematically illustrates a side view of the package of FIG. 1

[0014] FIG. 3 schematically illustrates a side view of a classical flip-chip package

[0015] FIG. 4 schematically illustrates an integrated circuit die according to the state of the art

[0016] FIG. 5 schematically illustrates an integrated circuit die according to a non-limited embodiment of the invention

[0017] FIG. 6 schematically illustrates the integrated circuit die of FIG. 5 used to prevent said die from being tested after a flip-chip packaging.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] FIG. 5 shows an integrated circuit die 10 similar to the integrated circuit die 10 of FIG. 4, with the difference that it comprises a solder pad 19 that is split in half. More precisely, the solder pad 19 comprises a first portion 33 and a second portion 34 facing each other, each having a shape of a demi-disk. The first portion 33 is connected to the VSS bond pad 20 via the redistribution wire 22, and the second portion 34 is connected to the test bond pad 37 via the redistribution wire 39.

[0019] When no solder ball is placed onto the solder pad 19, the first portion 33 and the second portion 34 are not in electrical contact with each other. However, when a solder ball is placed onto the solder pad 19, the first portion 33 and the second portion 34 become in electrical contact with each other. Naturally, the portions 33, 34 may have another shape or be laid out differently on the die 10, as long as a single solder ball can establish an electrical contact between them.

[0020] The key feature of the invention is that the electrical connections between the bond pads linked to the different portions are different depending on whether a solder ball is placed on the solder pad 19 or not. As a consequence, the split solder pad 19 may be used in order to prevent the integrated circuit die 10 from being tested after a flip-chip packaging, as illustrated on FIG. 6. In this example, the VSS bond pad 20 is chip-grounded.

[0021] As long as no solder ball is placed onto the solder pad 19, the die may be tested via the test circuitry 36. In order to do this, one terminal of a resistance 38 is generally connected to the test bond pad 37, and a potential VSS with a high state (1) is applied to the other terminal of the resistance 38. As a consequence, the test circuitry 36 is automatically enabled, and the die can be tested. However, after a solder ball 35 is placed onto the solder pad 19 in order to ground the VSS bond pad 20 via a printed circuit track 24, the test bond pad 37 becomes electrically connected to the VSS bond pad 20, and the test circuitry becomes disabled. This situation is wanted when the integrated circuit die is used in applications (that is to say after packaging), so as to avoid the die to enter a test mode.