METHOD FOR ULTRA-LOW-POWER AND HIGH-PRECISION REFERENCE GENERATION

Abstract

A reference generation circuit includes a reference circuit and a local supply regulation circuit connected between an input supply and the reference circuit to supply a local regulated input to the reference circuit. The local supply regulation circuit comprises an error amplifier and a pass device, and wherein the error amplifier senses an output voltage of the pass device and an output voltage of the reference generation circuit to generate an output to control a gate terminal of the pass device. The error amplifier uses a feedback network to sense the output voltage of the pass device for comparison with the output voltage of the reference generation circuit to generate the output to control the pass

Claims

1. A reference generation circuit, comprising: a reference circuit; and a local supply regulation circuit connected between an input supply and the reference circuit to supply a local regulated input to the reference circuit.

2. The reference generation circuit according to claim 1, wherein the local supply regulation circuit comprises an error amplifier and a pass device, and wherein the error amplifier senses an output voltage of the pass device and an output voltage of the reference generation circuit to generate an output to control a gate terminal of the pass device.

3. The reference generation circuit according to claim 2, wherein the error amplifier uses a feedback network to sense the output voltage of the pass device for comparison with the output voltage of the reference generation circuit to generate the output to control the pass device.

4. The reference generation circuit according to claim 3, wherein the feedback network comprises a potential divider.

5. The reference generation circuit according to claim 2, wherein the error amplifier is a skewed error amplifier.

6. The reference generation circuit according to claim 2, wherein the skewed error amplifier comprises a differential pair of transistors with a mismatch in dimensions of 1:K.sub.2 and a current mirror consisting of another differential pair of with a mirroring ratio K.sub.1:1, wherein K.sub.2=1/K.sub.1.

7. The reference generation circuit according to claim 1, wherein the reference circuit comprises a master reference circuit and a slave reference circuit, wherein the slave reference circuit is more power efficient than the master reference circuit, and wherein the master reference circuit is turned on only during startup or reset to calibrate the slave circuit to a specific level.

8. The reference generation circuit according to claim 7, wherein the slave reference circuit has multiple reference signal outputs for calibrating multiple analog blocks in a system.

9. The reference generation circuit according to claim 1, wherein the pass device is selected from the group consisting of NMOS, PMOS, NFIN, PFIN, npn BJT, and pnp BJT.

10. A method for generating a reference voltage or current using a reference generation circuit that comprising a reference circuit and a local supply regulation circuit, wherein the local supply regulation unit comprises an error amplifier and a pass device, the method comprising: sensing an output of the pass device and an output of the reference generation circuit; comparing, using the error amplifier, the output of the pass device and the output of the reference generation circuit to generate an output of the error amplifier; controlling a gate of the pass device, using the output of the error amplifier, to produce a local regulated signal from the pass device; and controlling, using the local regulated signal from the pass device, the reference circuit to generate the reference voltage or current.

11. The method according claim 10, wherein the reference circuit comprises a master reference circuit and a slave reference circuit, the method further comprising: calibrating the slave reference circuit using the master reference circuit.

12. The method according claim 11, further comprising: generating multiple reference output signals with the slave reference circuit to control multiple analog blocks in a system.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0016] The appended drawings illustrate several embodiments of the invention and are not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

[0017] FIG. 1 shows a schematic diagram of a prior art bipolar-based reference generation circuit.

[0018] FIG. 2 shows a schematic diagram of a prior art bipolar-less reference generation circuit.

[0019] FIG. 3 shows a block diagram of a reference generation circuit with improved PSR in accordance with one embodiment of the invention.

[0020] FIG. 4 shows a schematic of a reference generation circuit with improved PSR using a PMOS pass device in accordance with one embodiment of the invention.

[0021] FIG. 5 shows a schematic of a reference generation circuit with improved PSR using a PMOS pass device and using a skewed error amplifier in accordance with one embodiment of the invention.

[0022] FIG. 6 shows the input-output characteristics of the skewed error amplifier.

[0023] FIG. 7 shows a skewed error amplifier implementation in CMOS technology.

[0024] FIG. 8 shows a calibration circuit for an inaccurate reference generation circuit.

[0025] FIG. 9 shows a timing diagram of the calibration circuit in accordance with one embodiment of the invention.

[0026] FIG. 10 shows a calibration of an inaccurate reference driving multiple loads using an accurate master reference in accordance with one embodiment of the invention.

DETAILED DESCRIPTION

[0027] Aspects of the present disclosure are shown in the above-identified drawings and are described below. In this description, like or identical reference numerals are used to identify common or similar elements. The drawings are not necessarily to scale and certain features may be shown exaggerated in scale or in schematic in the interest of clarity and conciseness.

[0028] Embodiments of the invention relate to an accurate low-power reference generation circuit. This invention enables generation of high-quality ultra-low power and high accuracy reference generation circuits, which are required for multiple low power applications, including Internet of Things (IoT) applications. In one or more embodiments of the invention, a master reference circuit with high accuracy is available and used to calibrate a low power, low accuracy reference circuit, named slave reference circuit. In one or more embodiments of this invention, the calibration scheme is independent of the type of slave and master reference circuits. In one more embodiment of the invention, an accurate voltage reference is applied to a package pin used for test purposes.

[0029] In one or more embodiments of the invention, the power supply rejection (PSR) of any reference circuit is improved by creating a local regulated supply.

[0030] In one or more embodiments, the accurate low-power reference circuit is implemented on a microchip, such as in semiconductor integrated circuits. Throughout this disclosure, the terms reference circuit, reference generation circuit, bandgap reference circuit, bandgap reference circuit generator, and bandgap circuit may be used interchangeably depending on the context.

[0031] As noted above, FIG. 1 shows a prior art accurate bandgap reference circuit generator that achieves accurate output voltages, while consuming power levels not suitable for ultra-low-power solutions. FIG. 2 shows a prior art ultra-low-power voltage reference generation circuit, while achieving moderate accuracies it is not suitable for most high-accuracy systems.

[0032] In order to improve supply rejection behavior, FIG. 3 shows a block diagram of a reference generation circuit (300) with improved power supply rejection using a local regulated supply based on the circuit output in accordance with one embodiment of the invention. The circuit is supplied by V.sub.IN (301) and GND (302). V.sub.IN (301) may also be referred to as an input supply in this description. The reference generation circuit/block (303) can be any suitable reference circuit (e.g., the bipolar reference generation circuit (100) shown in FIG. 1, or the bipolar-less reference generation circuit (200) shown in FIG. 2). The input supply of the reference circuit (303), named V local (310), is produced by a local supply regulation circuit (311) that senses V local (310) as well as V.sub.out (304) and feeds them into the inputs of the error amplifier circuit (306): V.sub.2 (309) and V.sub.1 (308), respectively, to produce an output of this error amplifier V.sub.EA (307) such that V.sub.EA=f(V.sub.1,V.sub.2). The local regulated supply voltage is passed through a pass device (305). The relationship between V.sub.local and V.sub.out depends on the implementation and function of the error amplifier. As a result, if the local supply regulation circuit (311) provides a supply rejection of PSR(reg)=V.sub.local/V.sub.IN and the reference circuit (303) provides a supply rejection of PSR(ref)=V.sub.out/V.sub.local then the overall circuit provides a supply rejection of PSR(total)=PSR(reg)+PSR(ref). Possible implementations of the pass device (305) may include any suitable transistor devices, including the field effect types (FET) or the bipolar junction types (BJT). Examples of these include, but are not limited to, NMOS, PMOS, NFIN, PFIN, npn BJT, and pnp BJT.

[0033] In accordance with embodiments of the invention, FIG. 4 shows an exemplary implementation (400) for the idea presented in FIG. 3 (300). The circuit (400) is supplied with V.sub.IN (401) and GND (402). The local regulator circuit (405) comprises a feedback network (409) and an error amplifier (410). The feedback network consists of a potential divider (voltage divider) R1 (407) and R2 (408). The output of this feedback network is then compared with the V.sub.out signal (404) through the error amplifier (410). As a result, V.sub.local can be expressed as

[00001]$36.Math..Math.V_{\mathrm{local}}=V_{\mathrm{out}}\frac{R_1+R_2}{R_2}.$

[0034] FIG. 5 shows another implementation (500) that does not use feedback network resistors and hence is suitable for use in ultra-low-power systems. FIG. 5 is a low-power implementation of the proposed circuit in (300). The circuit is supplied by VIN (501) and GND (502). The local regulator (505) comprises a skewed error amplifier (507) with an input/output transfer function shown in FIG. 6 (600) and a PMOS pass transistor (506). The output of the skewed error amplifier (507) controls the gate terminal of the pass transistor (506) to produce the proper V.sub.local. FIG. 6 shows the input (601)-output (602) characteristics (600) of the skewed error amplifier used in FIG. 5 (507). The response has a high gain at a differential input (601) of a value of V.sub.offset (603). As a result, the output V.sub.local (508) of the circuit in (500) will relate to V.sub.out (504) as follows: V.sub.local=V.sub.out+V.sub.offset.

[0035] FIG. 7 shows a CMOS implementation example (700) of a skewed error amplifier (507) used in FIG. 5, the input/output characteristics of which resembles that of FIG. 6 (600). V.sub.+ (701) and V_ (702) are the differential inputs of the error amplifier. The skewed error amplifier circuit consists of a differential pair M.sub.1 (703) and M.sub.2 (704) with a mismatch in dimensions of 1:K.sub.2 and a current mirror consisting of transistors M.sub.3 (705) and M.sub.4 (706) with a mirroring ratio of K.sub.1:1, wherein K.sub.2=1/K.sub.1. Accordingly, the output V.sub.EAout (707) will relate to the inputs (701) and (702) with a function similar to the skewed error amplifier in (600), where V.sub.offset (603) is a function of K.sub.1 and K.sub.2.

[0036] FIG. 8 shows a schematic block diagram of proposed reference generation circuit (800) that creates an accurate voltage reference, while consuming ultra-low current levels in the normal mode of operation. The block diagram comprises an ultra-low power reference circuit generator, named slave reference circuit (801) that provides a stable output V.sub.SBGR (802) over temperature, while achieving a high PSR using any of the techniques proposed in (300), (400) and (500). The output of this slave reference circuit (801) can be digitally controlled using a digital code (808). The output V.sub.SBGR changes proportional to the digital code. For a fixed digital code, the output V.sub.SBGR varies with the silicon process corner and hence is not accurate enough.

[0037] The embodiment shown in FIG. 8 further comprises an accurate reference circuit, named master reference (803) that is used to provide an accurate output level V.sub.ref1 (804.a). In case of the availability of an extra external PAD (814), an external reference voltage can be provided V.sub.ref2 (804.b). The multiplexer (MUX) (812) selects one of the two references, based on the value of the digital selector signal Sel (813), and passes it to V.sub.ref (804.c) to calibrate the slave reference circuit. The master reference circuit is enabled only at the start of operation or during a reset condition to calibrate the slave reference circuit.

[0038] At startup, V.sub.SBGR is compared to the reference voltage V.sub.ref using an accurate comparator (805). The output of the comparator COMP (806) controls a digital state machine (807) that changes the digital code (808) to match V.sub.SBGR as close as possible to the reference voltage V.sub.ref. Once this is achieved the state machine (807) sends a signal CALIB (809) to the master reference (803) as well as the comparator (805) to turn both of them OFF. Therefore, during normal operations, the master reference block and the comparator are turned OFF, resulting in an accurate, high-PSR, ultra-low power V.sub.SBGR output.

[0039] FIG. 9 shows a timing diagram (900) that controls the operation of the calibration loop in (800). The CLK signal (901) dictates the speed of calibration. The CALIB signal (902) is high as long as the calibration cycle is in progress and functions as the signal that enables the master reference block and comparator. At the beginning of the calibration cycle, V.sub.SBGR (802) will be lower (or higher) than V.sub.ref (804.c). FIG. 9 shows an example when V.sub.SBGR (802) is lower than V.sub.ref (804.c), but the same principle applies for the opposite case. The state machine (807) keeps changing the digital code (808) as long as V.sub.SBGR (802) is lower (or higher) than V.sub.ref (804.c). Once this condition is violated, that is, V.sub.SBGR (802) is no longer lower or higher than V.sub.ref, the calibration is done, and the master reference and comparator are turned OFF to save power consumption.

[0040] In one or more embodiments of the invention, a state machine is used to select the digital code (807) that minimizes the difference between V.sub.SBGR (802) and V.sub.ref (804.c). Those skilled in the art, can adapt the state machine to allow V.sub.SBGR (803) to track the V.sub.ref (804.c) regardless of the initial value of V.sub.SBGR (803) with respect to V.sub.ref (804.c).

[0041] In one or more embodiments of the invention, the calibration code (808) should provide a range of values for V.sub.SBGR (802) that covers the value of V.sub.ref (804.c).

[0042] FIG. 10 shows a block diagram (1000) of a system that uses the idea described in FIG. 8 (800) to calibrate multiple analog blocks in a system. The block diagram comprises an accurate Master Reference (1001) that is used to calibrate a Slave Reference (1002) that has multiple Reference Signal outputs (1017, 1018, 1019). This example shows the three outputs (1017, 1018, 1019) driving three Analog Blocks (1014, 1015, 1016). This is for illustration only. In general, the number of outputs can be any value equal to or greater than two.

[0043] The multiple outputs (1017, 1018, 1019) of the Slave Reference (1002) may be calibrated individually under the control of a State Machine (1004). Block diagram (1000) shows a system that calibrates the Slave Reference (1002) outputs (1017, 1018, 1019) sequentially as an example. However, the system can be implemented to calibrate all of the outputs (1017, 1018, 1019) in parallel by adding an additional comparator (1005) for each output and by removing the multiplexer (1003).

[0044] The operation of the calibration of the system (1000) is controlled by the Clock (1006). After power-up or reset, the State machine (1004) enables the Master Reference (1001) and Comparator (1005) with Enable signals (1008) and (1009). One of the three Local Reference signals (1020) is selected based on a Select input (1010) from the State Machine (1004) to drive the output of the Multiplexer (1003), Mux out (1011). The Comparator (1005) compares Mux out (1011) with the Reference Output (1012) of the Master Reference (1001). The output of the Comparator (1005), Comp (1007) is an input to the State Machine (1004). The State Machine (1004) adjusts the Calibration Bits (1013) corresponding to the Analog Block (1014, 1015, 1016) being calibrated. When the State Machine (1004) determines that the Local Reference signal (1020) is close enough to the Master Reference (1001) Reference Output (1012), calibration of the selected Local Reference Signal (1020) is complete, and the State Machine (1004) changes the Select input (1010) of the Multiplexer (1003) to perform calibration on the next Local Reference Signal (1020).

[0045] After all of the Local Reference Signals (1020) have been calibrated, the State Machine (1004) turns off the Comparator (1005) and the Master Reference (1001) to save power. After the power-up or reset calibration sequence has been completed, the State Machine (1004) can optionally perform periodic calibration sequences. The periodic calibration may be needed due to drift in environmental conditions, such as temperature or voltage, or due to aging of the components that generate the Local Reference Signals (1020).

[0046] This block diagram (1000) shows a system that calibrates the value of Local Reference Signals (1020) that are generated in the Analog Blocks (1014, 1015, 1016) instead of calibrating the value of the Reference Signals (1017, 1018, 1019) generated by the Slave Reference (1002). This is done to reduce or eliminate errors due to component mis-match in the Analog Blocks (1014, 1015, 1016), I-R drop in the Local Reference Signals (1020), and/or power-supply or ground voltage differences between the Slave Reference (1002) and the Analog Blocks (1014, 1015, 1016).

[0047] While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.