Package substrate and structure

Abstract

A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.

Claims

1. A package substrate, comprising: a plurality of dielectric layers; a plurality of conductive vias formed in the dielectric layers; and a plurality of circuit layers being metal layers alternately stacked with the dielectric layers with the circuit layers being electrically connected to one another via the conductive vias, wherein one of the dielectric layers is a core layer, the circuit layers are symmetrically formed on two opposite sides of the core layer, and each of upper circuit layers above the core layer is greater in thickness than each of lower circuit layers below the core layer, and wherein the uppermost circuit layer closest in position to an upper surface of the package substrate is greater in thickness than the other circuit layers, the lowermost circuit layer closest in position to a lower surface of the package substrate is less in thickness than the other circuit layers, the upper circuit layers except the uppermost circuit layer have a same thickness, and the lower circuit layers except the lowermost circuit layer have a same thickness.

2. The substrate of claim 1, wherein the upper surface of the package substrate is a chip mounting surface and the lower surface of the package substrate is a non-chip mounting surface.

3. The substrate of claim 1, wherein the sum of the thicknesses of half of the circuit layers close in position to the upper surface of the package substrate is greater than the sum of the thicknesses of half of the circuit layers close in position to the lower surface of the package substrate.

4. The substrate of claim 1, wherein the thickest circuit layer and the thinnest circuit layer have a thickness ratio of 1.2:1 to 2:1.

5. The substrate of claim 4, wherein the thickest circuit layer and the thinnest circuit layer have a thickness ratio of 1.5:1.

6. The substrate of claim 1, wherein the thickest circuit layer and the thinnest circuit layer have a thickness difference of 3 to 15 um.

7. The substrate of claim 6, wherein the thickest circuit layer and the thinnest circuit layer have a thickness difference of 5 to 10 um.

8. The substrate of claim 1, wherein the number of the circuit layers is an odd or even number.

9. A package structure, comprising: a package substrate having a plurality of dielectric layers, a plurality of conductive vias formed in the dielectric layers, and a plurality of circuit layers being metal layers alternately stacked with the dielectric layers with the circuit layers being electrically connected to one another via the conductive vias, wherein one of the dielectric layers is a core layer, the circuit layers are symmetrically formed on two opposite sides of the core layer, and each of upper circuit layers above the core layer is greater in thickness than each of lower circuit layers below the core layer, and wherein the uppermost circuit layer closest in position to an upper surface of the package substrate is greater in thickness than the other circuit layers, the lowermost circuit layer closest in position to a lower surface of the package substrate is less in thickness than the other circuit layers, the upper circuit layers except the uppermost circuit layer have a same thickness, and the lower circuit layers except the lowermost circuit layer have a same thickness; and a chip mounted on an upper surface of the package substrate.

10. The structure of claim 9, wherein the sum of the thicknesses of half of the circuit layers close in position to the upper surface of the package substrate is greater than the sum of the thicknesses of half of the circuit layers close in position to the lower surface of the package substrate.

11. The structure of claim 9, wherein the thickest circuit layer and the thinnest circuit layer have a thickness ratio of 1.2:1 to 2:1.

12. The structure of claim 11, wherein the thickest circuit layer and the thinnest circuit layer have a thickness ratio of 1.5:1.

13. The structure of claim 9, wherein the thickest circuit layer and the thinnest circuit layer have a thickness difference of 3 to 15 um.

14. The structure of claim 13, wherein the thickest circuit layer and the thinnest circuit layer have a thickness difference of 5 to 10 um.

15. The structure of claim 9, wherein the number of the circuit layers is an odd or even number.

16. A package substrate, comprising: a plurality of dielectric layers; a plurality of conductive vias formed in the dielectric layers; and a plurality of circuit layers being metal layers alternately stacked with the dielectric layers with the circuit layers being electrically connected to one another via the conductive vias, wherein one of the dielectric layers is a core layer, the circuit layers are symmetrically formed on two opposite sides of the core layer, and each of upper circuit layers above the core layer is greater in thickness than each of lower circuit layers below the core layer, and wherein the upper circuit layers have a same thickness and the lower circuit layers have a same thickness.

17. A package structure, comprising: a package substrate having a plurality of dielectric layers, a plurality of conductive vias formed in the dielectric layers, and a plurality of circuit layers being metal layers alternately stacked with the dielectric layers with the circuit layers being electrically connected to one another via the conductive vias, wherein one of the dielectric layers is a core layer, the circuit layers are symmetrically formed on two opposite sides of the core layer, and each of upper circuit layers above the core layer is greater in thickness than each of lower circuit layers below the core layer, and wherein the upper circuit layers have a same thickness and the lower circuit layers have a same thickness; and a chip mounted on an upper surface of the package substrate.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic cross-sectional view of a conventional flip-chip package substrate;

(2) FIG. 2 is a schematic cross-sectional view of a package substrate of the present invention; and

(3) FIG. 3 is a schematic cross-sectional view of a package structure of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(4) The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.

(5) It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as upper, lower etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.

(6) FIG. 2 is a schematic cross-sectional view of a package substrate of the present invention. Referring to FIG. 2, the package substrate 2 has: a plurality of dielectric layers 21; and a plurality of circuit layers 22 alternately stacked with the dielectric layers 21. At least two of the circuit layers 22 have a difference in thickness. One of the dielectric layers 21 is a core layer 21 and the circuit layers 22 are symmetrically formed on two opposite sides of the core layer 21.

(7) In the above-described package substrate, the circuit layer 22 on or close in position to an upper surface 2a of the package substrate 2 is greater in thickness than the circuit layer 22 on or close in position to a lower surface 2b of the package substrate 2. The upper surface 2a of the package substrate 2 is a chip mounting surface and the lower surface 2b of the package substrate 2 is a non-chip mounting surface.

(8) In an embodiment, the uppermost circuit layer 22 closest in position to the upper surface 2a is greater in thickness than the other circuit layers 22, the lowermost circuit layer 22 closest in position to the lower surface 2b is less in thickness than the other circuit layers 22, and the circuit layers 22 except the uppermost and lowermost circuit layers 22 have a same thickness. For example, six circuit layers 22 are provided. The six circuit layers 22, from the upper surface 2a to the lower surface 2b of the package substrate 2, can have thicknesses of 26 um, 19 um, 19 um, 19 um, 19 um and 12 um, respectively.

(9) In another embodiment, the thicknesses of the circuit layers 22 gradually decrease from the upper surface 2a to the lower surface 2b of the package substrate 2. For example, six circuit layers 22 can be provided. From the upper surface 2a to the lower surface 2b of the package substrate 2, the six circuit layers 22 can have thicknesses of 26 um, 23 um, 19 um, 19 um, 15 um and 12 um, respectively.

(10) In another embodiment, the sum of the thicknesses of half of the circuit layers 22 close in position to the upper surface 2a of the package substrate 2 is greater than the sum of the thicknesses of half of the circuit layers 22 close in position to the lower surface 2b of the package substrate 2. For example, six circuit layers 22 can be provided, and the thicknesses of the circuit layers 22 from the upper surface 2a to the lower surface 2b of the package substrate 2 are 26 um, 24 um, 20 um, 18 um, 14 um and 12 um, respectively.

(11) In another embodiment, referring to FIG. 2, six circuit layers 22 are provided, and the thicknesses of the circuit layers 22 from the upper surface 2a to the lower surface 2b of the package substrate 2 are 22 um, 22 um, 22 um, 16 um, 16 um and 16 um, respectively.

(12) In the above-described package substrate, the thickest circuit layer 22 and the thinnest circuit layer 22 have a thickness ratio of 1.2:1 to 2:1. Preferably, the thickest circuit layer 22 and the thinnest circuit layer 22 have a thickness ratio of 1.5:1.

(13) The thickest circuit layer 22 and the thinnest circuit layer 22 have a thickness difference of 3 to 15 um. Preferably, the thickest circuit layer 22 and the thinnest circuit layer 22 have a thickness difference of 5 to 10 um.

(14) In the package substrate of the present invention, the number of the circuit layers 22 can be an odd or even number.

(15) FIG. 3 is a schematic cross-sectional view of a package structure of the present invention. Referring to FIG. 3, a chip 31 is mounted on the upper surface 2a of the package substrate 2 and an encapsulant 32 is formed to encapsulate the chip 31.

(16) Therefore, by providing a thickness difference between the circuit layers, the present invention increases the rigidity of the package substrate so as to reduce warpage of the package substrate by 5% to 25%. Further, the sum of the thicknesses of the circuit layers can be kept unchanged so as to prevent increase of the overall thickness of the package substrate and structure and hence meet the miniaturization requirement of electronic products.

(17) The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.