Class AB amplifier with bias control

Abstract

An amplifier arrangement comprising first and second power amplifiers (T1, T2) having drains connected to positive and negative drive voltages, respectively, and gates connected to an input signal. The arrangement further comprises first and second current sensors (1, 2) for detecting first and second drain currents from the power amplifiers, processing circuitry (3) adapted to identify the smallest drain current, and a feedback control loop (5) and means for driving a bias current dependent on a feedback signal through a resistor connected between the input signal and the gate of an inactive one of the first and second power amplifiers. The control loop will keep the idle current constant in the transistor with the lowest current (the inactive transistor). Thereby, the current running in the transistor which does not deliver current to the load will be fixed at a desired value.

Claims

1. An amplifier arrangement comprising: a first power amplifier having a drain connected to a positive drive voltage and a gate connected to an input signal, a second power amplifier having a drain connected to a negative drive voltage and a gate connected to said input signal, wherein a source of the first power amplifier and a source of the second power amplifier are both connected to a load (RL), a first current sensor detecting a first drain current from said first power amplifier, a second current sensor detecting a second drain current from said second power amplifier, processing circuitry adapted to identify an idle current as a smallest drain current of said first and second drain currents, a bias control loop including: a comparator arranged to compare said idle current with a pre-set idle current set point, to provide an error signal, and a loop gain providing a feedback signal based on said error signal, a first current source connected to drive a bias current dependent on said feedback signal through a first resistor connected between the input signal and the gate of the first power amplifier to create a first bias voltage at the gate of said first power amplifier, in order to ensure that the first drain current from said first power amplifier is equal to the pre-set idle current when said first power amplifier is inactive, and a second current source connected to drive a bias current dependent on said feedback signal through a second resistor connected between the input signal and the gate of the second power amplifier to create a second bias voltage at the gate of said second power amplifier in order to ensure that the second drain current from said second power amplifier is equal to the pre-set idle current when said second power amplifier is inactive.

2. The arrangement according to claim 1, wherein each of said first current source and said second current source is configured to, if said first drain current or said second drain current is smaller the pre-set idle current, increase the bias current through said first resistor or said second resistor, respectively, until said first drain current or said second drain current becomes equal to the pre-set idle current.

3. The arrangement according to claim 1, wherein said processing circuitry is realized as an analogue circuit.

4. The arrangement according to claim 1, wherein said processing circuitry comprises a digital processor.

5. A method for controlling an idle current in an amplifier arrangement having a first and a second power amplifier, a positive drive voltage connected to a drain of said first power amplifier, a negative drive voltage connected to a drain of said second power amplifier, and an input signal connected to a gate of each power amplifiers, and wherein a source of the first power amplifier and a source of the second power amplifier are both connected to a load (RL), said method comprising: detecting a first drain current from said first power amplifier, detecting a second drain current from said second power amplifier, identifying an idle current as a smallest drain current of said first and second drain currents, comparing said idle current with a pre-set idle current set point, to provide an error signal, supplying said error signal to a loop gain, to provide a feedback signal, supplying said feedback signal to a first current source connected to drive a current through a first resistor to create a first bias voltage at a gate of said first power amplifier, and to a second current source connected to drive a current through a second resistor to create a second bias voltage at a gate of said second power amplifier, driving a bias current dependent on said feedback signal through one of said first resistor or said second resistor connected between the input signal and the gate of an inactive one of said first and second power amplifiers, thereby ensuring that a drain current from said inactive power amplifier is equal to said pre-set idle current.

6. The method according to claim 5, wherein said step of driving a bias current includes if said first drain current or said second drain current is smaller the pre-set idle current, increasing the bias current through said first resistor or said second resistor, respectively, until said first drain current or said second drain current becomes equal to the pre-set idle current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will be described in more detail with reference to the appended drawings, showing currently preferred embodiments of the invention.

(2) FIG. 1 is a schematic block diagram of an amplifier according to an embodiment of the invention.

(3) FIG. 2 is a flow chart of a method according to an embodiment of the invention.

(4) FIG. 3 is a more detailed circuit diagram of an amplifier of an embodiment of the invention.

(5) FIG. 4 is a diagram of output currents of the two branches in the circuit in FIG. 3.

DETAILED DESCRIPTION OF CURRENTLY PREFERRED EMBODIMENTS

(6) FIG. 1 shows an amplifier arrangement according to an embodiment of the invention with two MOSFET transistors; a top transistor T1 and a bottom transistor T2, delivering voltage V.sub.out to a load RL. The top transistor T1 is connected to a positive drive voltage, and its gate is connected to an input voltage via a resistor R1. The bottom transistor T2 is connected to a negative drive voltage, and its gate is connected to an input voltage via a resistor R2. The drain current in the top transistor T1 is referred to as i.sub.1 and the drain current in the bottom transistor T2 is referred to as i.sub.2. The drain of each transistor is connected to respective current sensors 1, 2, arranged to detect the two drain currents i.sub.1, i.sub.2.

(7) The arrangement further comprises processing circuitry arranged to rectify the signals from the current sensors 1, 2, and to identify the smallest current of i.sub.1 and i.sub.2. This smallest current, i represents the idle current running in the branch which does not deliver current to the output load RL. A bias control loop includes a comparator 4, arranged to compare the value of the smallest current i.sub.r with a value representing a desired idle current, i.sub.q. The control loop further comprises a loop gain 5 connected to two current sources C1 and C2. The current sources are respectively connected to resistors R1 and R2.

(8) The operation of the arrangement in FIG. 1 will now be briefly described with reference to FIG. 2. First, in step S1, the two drain currents i.sub.1, i.sub.2 are detected by the current sensors 1, 2, and signals representing the detected currents are supplied to the processing circuitry 3. In step S2, the smallest current of i.sub.1 and i.sub.2 is identified by the processing circuitry 3. In step S3, a feedback signal is formed by comparing the identified smallest current, ir, with the desired idle current, and amplifying the resulting error i.sub.e by a constant gain A in the loop gain 5. In step S4, the feedback signal is used to control the current sources C1 and C2 to draw a bias current through resistors R1 and R2, thereby influencing a bias voltage across the resistors R1, R2. The drain current feedback acts as a bias control loop, and ensures that if the smallest drain current of i.sub.1 or i.sub.2 is less than i.sub.q, the current through R1/R2 will increase until this smallest current becomes equal to i.sub.q. This ensures a constant idle current equal to i.sub.q through T1 and T2 when they are inactive.

(9) In addition, the feedback described above provides a linearizing effect as will be described in the following.

(10) FIG. 1 can be seen as a unity gain voltage follower. The relation ideally is V.sub.out=V.sub.in. The relation between drain current and gate source voltage, on the other hand, is non-linear.

(11) If T1 and T2 are perfectly matched, then the gate source voltage V.sub.GS1=V.sub.GS2 for the same drain current and the same drain-source voltage. For simplicity, R1 is assumed to be equal to R2. Under these conditions, the following holds:
V.sub.out=V.sub.in+i.sub.b*R1V.sub.GS11.
V.sub.out=V.sub.ini.sub.b*R1+V.sub.GS2V.sub.out=*V.sub.ini.sub.b*R1+V.sub.SG2,2.

(12) where V.sub.in is the input signal, V.sub.out is the output voltage, i.sub.b*R1 is the bias voltage and V.sub.GSx is the gate-source voltage. If V.sub.in=0 then V.sub.out=0 and V.sub.GS=V.sub.GS1=V.sub.Q=i.sub.bq*R1, where i.sub.bq is the bias current through R1. In a conventional bias system the voltage difference between V.sub.G1 and V.sub.G2 is held constant. In FIG. 1 this would correspond to breaking the control loop and consider the bias current i.sub.b as a constant, so V.sub.G1V.sub.G2=i.sub.bq*(R1+R1). If V.sub.in is positive, T1 will increase the output current into the load RL. This means that V.sub.GS1 will increase by some amount. So we let V.sub.GS1=V.sub.Q+V.sub.GS1V.sub.GS1=V.sub.Q+V.sub.GS1, where the added amount depends of un-linear parameters in the transistor. Equation 1 now becomes:
V.sub.out=V.sub.in+i.sub.b*R1V.sub.GS1=V.sub.in+i.sub.b*R1(V.sub.Q+V.sub.GS1)V.sub.out=V.sub.in+i.sub.b*R1V.sub.GS1=V.sub.in+i.sub.bQ*R1V.sub.out=V.sub.inV.sub.GS13.

(13) In a system according to an embodiment of the invention as illustrated in FIG. 1, as mentioned, the bias control loop will keep the idle current constant in the branch with the lowest current. Therefore, in this case, when T1 is driving the load, the control loop will increase i.sub.b until the desired idle current is obtained through T2.

(14) To simplify we choose to omit the very small change in idle current coming from the change in V.sub.SD2, so the current in T2 is only dependent of V.sub.SG2. Then the gate-source voltage of T2 is unchanged V.sub.SG2=V.sub.Q. Equation 1 and 2 becomes:
V.sub.out=V.sub.in+i.sub.b*R1(V.sub.Q+V.sub.GS1)4.
V.sub.out=V.sub.ini.sub.b*R1+((V.sub.Q+0)5.

(15) Adding two equations and dividing by two results in:
V.sub.out=V.sub.inV.sub.GS1/26.

(16) The same result appears when the investigation is made on a negative voltage input. Clearly, in an amplifier according to this embodiment of the invention, the non-linear component is reduced to half the value compared to a conventional system. If we substitute the MOSFET's with a complementary set of bipolar transistors we will find the same improvement in performance.

(17) FIG. 3 shows an example of a circuit realization of the schematic diagram in FIG. 1, with the processing circuitry 3 realized by analogue circuitry. Components in FIG. 3 corresponding to similar components in FIG. 1 have been given identical reference labels.

(18) The output transistors T1, T2 are here MOSFET transistors, which are complementary to the common source V.sub.in. The voltage drop across resistors R1 and R2 forms a bias voltage that generates gate-source voltages from the transistors. C1 and C2 are two current generators which track and input the same current as is drawn out so that the circuit is balanced.

(19) The drain currents of T1 and T2 are measured by the following manner. A diode 11, 12 is provided in the forward direction of each drain. In parallel with the diode is a resistor 13, 14. The resistor 13, 14 has a value which ensures that the voltage drop across the resistor is determined by the desired bias current, and not by the forward voltage of the diode. For example, at 10 mA there will be a voltage of about 100 mV across resistor 13 which is significantly below the forward voltage of the diode. When the output draws a lot of current, the diode takes over and ensure that the output stage continues to function, only with a diode forward voltage less in the supply voltage.

(20) The voltage drop across resistor 13 is detected by means of transistors T4, T5, and the value is supplied as a current. Similarly for the other branch, where transistors T6 and T7 detect the voltage across resistor 14. In the lower branch, the current signal is reversed by a current mirror 15. The voltage across resistor 16 now represents the current in the lower branch and the voltage across resistor 17 the current of the upper branch.

(21) Using diodes 18 and 19 the lower of the two voltages is found, and this represents the value to be maintained as a constant according to the invention. This signal passes an emitter follower 20 to be subsequently low-pass filtered in order to introduce a loop filter to ensure that the feedback system is stable.

(22) The filtered signal is connected to a differential amplifier 21 including transistors 22, 23. At the base of transistor 23 is provided a DC signal that corresponds to the desired minimum idle current, e.g. one Volt.

(23) The differential amplifier 21 has its output connected to an amplifier 24 including transistors 25, 26, 27, 28. The amplifier is designed to convert the output current from the differential amplifier 21 to the two current generators C1, C2 that provide a voltage drop across R1 and R2.

(24) The circuit also includes a number of RC components which aim to make the system fast and stable. There are also interposed some 1 mohm resistors which are irrelevant to the function. They only serve to provide a measure resistance in the simulation of the circuit.

(25) FIG. 4 shows a simulation of the current in the circuit in FIG. 3, showing the current through the top and bottom transistors T1, T2. It is evident that both output transistors T1, T2 are constantly drawing current, and that a minimum flow of current is maintained at all times, in this case at around 8 mA.

(26) The person skilled in the art realizes that the present invention by no means is limited to the preferred embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims. For example, the above description relates to an implementation with MOSFET transistors, but implementations with bipolar transistors are also possible. Further, the details of the circuit implementation may differ from that shown in FIG. 3, e.g. to include additional filters or feedback control.

(27) The processing circuitry 3, which above has been exemplified with analogue circuitry, can also be implemented by a digital processor. Such implementation would entail suitable sampling, e.g. using 10 bit A/D and D/A converters with a sampling rate of 20 MHz. Possible embodiments include an SAR converter or a flash converter.