Fabrication method of packaging substrate

Abstract

A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

Claims

1. A method for fabricating a packaging substrate, comprising the steps of: providing a carrier having a first circuit layer formed thereon, wherein the carrier has a conductive layer that allows the first circuit layer to be formed thereon, and the first circuit layer has a plurality of first conductive pads; forming a dielectric layer on the carrier and the first circuit layer, wherein the dielectric layer has a first surface in contact with and attached to the carrier and a second surface opposite to the first surface; removing the carrier so as to expose a surface of the conductive layer formed on the first circuit layer from the first surface of the dielectric layer; forming a resist layer on the conductive layer and forming a plurality of openings in the resist layer corresponding in position to the first conductive pads; forming a metal layer in the openings of the resist layer; and removing the resist layer so as for the metal layer to form on the first conductive pads a plurality of conductive bumps protruding above the first surface of the dielectric layer.

2. The method of claim 1, wherein the surface of the first circuit layer is flush with or lower than the first surface of the dielectric layer.

3. The method of claim 1, further comprising forming an insulating layer on the first surface of the dielectric layer and the surface of the first circuit layer and forming a plurality of openings in the insulating layer for exposing the conductive bumps.

4. The method of claim 1, further comprising forming a second circuit layer on the second surface of the dielectric layer.

5. The method of claim 4, further comprising forming a plurality of conductive vias in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer.

6. The method of claim 4, further comprising forming an insulating layer on the second surface of the dielectric layer and the second circuit layer and forming a plurality of openings in the insulating layer for exposing portions of the second circuit layer.

7. A method for fabricating a packaging substrate, comprising the steps of: providing a carrier having a first circuit layer formed thereon, wherein the carrier has a metal layer, and the first circuit layer has a plurality of first conductive pads; forming a dielectric layer on the carrier and the first circuit layer, wherein the dielectric layer has a first surface in contact with and attached to the carrier and a second surface opposite to the first surface; removing the carrier so as to expose a surface of the first circuit layer from the first surface of the dielectric layer; and after the carrier is removed, portions of the metal layer are removed so as for the remaining portions of the metal layer to form on the first conductive pads a plurality of conductive bumps protruding above the first surface of the dielectric layer.

8. The method of claim 7, wherein the surface of the first circuit layer is flush with or lower than the first surface of the dielectric layer.

9. The method of claim 7, further comprising forming an insulating layer on the first surface of the dielectric layer and the surface of the first circuit layer and forming a plurality of openings in the insulating layer for exposing the conductive bumps.

10. The method of claim 7, further comprising forming a second circuit layer on the second surface of the dielectric layer.

11. The method of claim 10, further comprising forming a plurality of conductive vias in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer.

12. The method of claim 10, further comprising forming an insulating layer on the second surface of the dielectric layer and the second circuit layer and forming a plurality of openings in the insulating layer for exposing portions of the second circuit layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIGS. 1A to 1F are schematic cross-sectional views showing a method for fabricating a packaging substrate according to the prior art;

(2) FIG. 1G is a schematic cross-sectional view showing a subsequent process of the conventional packaging substrate;

(3) FIGS. 2A to 2G are schematic cross-sectional views showing a method for fabricating a packaging substrate according to the present invention, wherein FIGS. 2F and 2F show other embodiments of the FIG. 2F, and FIG. 2G shows another embodiment of FIG. 2G;

(4) FIG. 2H is a schematic cross-sectional view showing a subsequent process of the packaging substrate of the present invention;

(5) FIGS. 3A and 3B are schematic cross-sectional views showing a method for forming the conductive bumps of FIG. 2F;

(6) FIGS. 4A to 4C are schematic cross-sectional views showing another method for forming the conductive bumps of FIG. 2F; and

(7) FIGS. 5A and 5B are schematic cross-sectional views showing a further method for forming the conductive bumps of FIG. 2F.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(8) The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.

(9) It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as upper, lower, first, second, a etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.

(10) FIGS. 2A to 2G are schematic cross-sectional views showing a method for fabricating a packaging substrate 2 according to the present invention.

(11) Referring to FIGS. 2A and 2B, a carrier 20 is provided and a first circuit layer 21 is formed on upper and lower surfaces of the carrier 20.

(12) The carrier 20 can be an insulating plate, a ceramic plate, a copper clad laminate or a glass plate. In the present embodiment, a metal layer 200 is formed on the upper and lower surfaces of the carrier 20 to serve as a conductive layer, i.e., a seed layer. If the carrier 20 is a copper clad laminate, the copper foil of the copper clad laminate can serve as the conductive layer.

(13) Referring to FIG. 2B, a first circuit layer 21 is formed on the conductive layer 200 by electroplating. The first circuit layer 21 has a plurality of first conductive pads 210.

(14) Referring to FIG. 2C, a dielectric layer 22 is formed on the carrier 20 and the first circuit layer 21. The dielectric layer 22 has a first surface 22a in contact with and attached to the carrier 20 and a second surface 22b opposite to the first surface 22a.

(15) In the present embodiment, the dielectric layer 22 is made of prepreg.

(16) Referring to FIG. 2D, a second circuit layer 23 is formed on the second surface 22b of the dielectric layer 22. The second circuit layer 23 has a plurality of second conductive pads 230. Further, a plurality of conductive vias 24 are formed in the dielectric layer 22 for electrically connecting the first circuit layer 21 and the second circuit layer 23.

(17) Referring to FIG. 2E, the carrier 20 is removed to expose the conductive layer 200.

(18) Referring to FIG. 2F, a plurality of conductive bumps 27 made of such as copper are formed on the conductive layer 200 corresponding in position to the first conductive pads 210. The conductive bumps 27 protrude to a height h of 5 um above the first surface 22a of the dielectric layer 22. Then, portions of the conductive layer 200 exposed from the conductive bumps 27 are removed while maintaining portions 200 of the conductive layer 200 under the conductive bumps 27.

(19) In the present embodiment, the width D of the conductive bumps 27 is equal to the width R of the first conductive pads 210.

(20) In another embodiment, referring to FIG. 2F, the width D of the conductive bumps 27 is greater than the width R of the first conductive pads 210. In a further embodiment, referring to FIG. 2F, the width D of the conductive bumps 27 is less than the width R of the first conductive pads 210.

(21) Referring to FIG. 2G, a first insulating layer 25 is formed on the first surface 22a of the dielectric layer 22 and the first circuit layer 21 and a plurality of first openings 250 are formed in the first insulating layer 25 so as to expose the conductive bumps 27 and portions of the first surface 22a of the dielectric layer 22 around peripheries of the conductive bumps 27. Further, a second insulating layer 26 is formed on the second surface 22b of the dielectric layer 22 and the second circuit layer 23 and a plurality of second openings 260 are formed in the second insulating layer 26 to expose the second conductive pads 230.

(22) In another embodiment, referring to FIG. 2G, when the conductive layer 200 is removed, the first conductive pads 210 are also partially removed so as to be recessed into the first surface 22a of the dielectric layer 22.

(23) Subsequently, referring to FIG. 2H, an electronic element 9 is disposed on the first conductive pads 210 through a plurality of conductive elements 28 made of such as a solder material. Since the conductive bumps 27 protrude above the first surface 22a of the dielectric layer 22, the conductive elements 28 can come into contact with both top surfaces 27a and side surfaces 27c of the conductive bumps 27 so as to increase the contact area between the conductive elements 28 and the first conductive pads 210, thereby strengthening the bonding between the conductive elements 28 and the first conductive pads 210 and preventing delamination of the conductive elements 28 from the first conductive pads 210. Therefore, the product reliability is improved.

(24) Further, even if the surface of the first circuit layer 21 is lower than the first surface 22a of the dielectric layer 22, the conductive bumps 27 protruding above the first surface 22a of the dielectric layer 22 ensure sufficient wetting of the conductive elements 28 so as to prevent the conductive elements 28 from being stuck on the first surface 22a of the dielectric layer 22. Therefore, the conductive elements 28 can be in effective contact with the conductive bumps 27 so as to be electrically connected to the first conductive pads 210.

(25) The conductive bumps 27 can be formed through the following methods.

(26) FIGS. 3A and 3B are schematic cross-sectional views showing a method for forming the conductive bumps 27 according to a first embodiment.

(27) Referring to FIG. 3A, a metal layer 40 is formed on the conductive layer 200 by attaching or electroplating.

(28) In the present embodiment, the conductive layer 200 is a copper foil.

(29) Referring to FIG. 3B, a patterning process is performed to remove portions of the metal layer 40 and the conductive layer 200 under the metal layer 40. As such, the remaining portions 40 of the metal layer 40 and the remaining portions 200 of the conductive layer 200 form the conductive bumps 27.

(30) FIGS. 4A to 4C are schematic cross-sectional views showing a method for forming the conductive bumps 27 according to a second embodiment.

(31) Referring to FIG. 4A, a resist layer 52 is formed on the conductive layer 200 and a plurality of third openings 520 are formed in the resist layer 52 to expose portions of the conductive layer 200 corresponding in position to the first conductive pads 210.

(32) In the present embodiment, the conductive layer 200 is a copper foil.

(33) Referring to FIG. 4B, a metal layer 50 is formed on the exposed portions of the conductive layer 200 in the third openings 520 of the resist layer 52 by electroplating.

(34) Referring to FIG. 4C, the resist layer 52 and the portions of the conductive layer 200 under the resist layer 52 are removed. As such, the metal layer 50 and the portions 200 of the conductive layer 200 under the metal layer 50 form the conductive bumps 27.

(35) FIGS. 5A and 5B are schematic cross-sectional views showing a method for forming the conductive bumps 27 according to a third embodiment.

(36) Referring to FIG. 5A, the conductive layer 200 is removed and a metal layer 30 is formed on the first surface 22a of the dielectric layer 22 and the first circuit layer 21.

(37) In the present embodiment, a copper foil can be laminated on the first surface 22a of the dielectric layer 22 and the first circuit layer 21 to serve as the metal layer 30. Alternatively, the metal layer 30 can be formed by electroplating.

(38) In other embodiments, after the conductive layer 200 is removed, the first circuit layer 21 has a surface slightly lower than the first surface 22a of the dielectric layer 22 so as to be recessed into the first surface 22a of the dielectric layer 22.

(39) In another embodiment, no conductive layer 200 is formed on the upper and lower surfaces of the carrier 20. Instead, referring to FIG. 5A, the metal layer 30 is directly formed on the upper and lower surfaces of the carrier 20. Therefore, after the carrier 20 is removed, the metal layer 30 is exposed.

(40) Referring to FIG. 5B, a patterning process is performed to remove portions of the metal layer 30. As such, the remaining portions 30 of the metal layer 30 form the conductive bumps 27.

(41) The present invention further provides a packaging substrate 2, which has: a dielectric layer 22 having opposite first and second surfaces 22a, 22b; a first circuit layer 21 embedded in the first surface 22a of the dielectric layer 22 and having a surface exposed from the first surface 22a of the dielectric layer 22, wherein the first circuit layer 21 has a plurality of first conductive pads 210; and a plurality of conductive bumps 27, 27, 27 formed on the first conductive pads 210 and protruding above the first surface 22a of the dielectric layer 22.

(42) The surface of the first circuit layer 21 can be flush with the first surface 22a of the dielectric layer 22.

(43) The conductive bumps 27, 27, 27 can be less, equal to or greater in width than the first conductive pads 210. The conductive bumps 27, 27, 27 can be made of copper.

(44) The packaging substrate 2 can further have a first insulating layer 25 formed on the first surface 22a of the dielectric layer 22 and the surface of the first circuit layer 21 and having a plurality of openings 250 for exposing the conductive bumps 27, 27, 27 and portions of the first surface 22a around peripheries of the conductive bumps 27, 27, 27.

(45) The packaging substrate 2 can further have a second circuit layer 23 formed on the second surface 22b of the dielectric layer 22 and having a plurality of second conductive pads 230. Further, a plurality of conductive vias 24 are formed in the dielectric layer 22 for electrically connecting the first circuit layer 21 and the second circuit layer 23. Furthermore, the packaging substrate 2 can have a second insulating layer 26 formed on the second surface 22b of the dielectric layer 22 and the second circuit layer 23 and having a plurality of second openings 260 for exposing the second conductive pads 230.

(46) According to the present invention, since the first conductive pads have the conductive bumps formed thereon and protruding above the first surface of the dielectric layer, when an electronic element is disposed on the first conductive pads through a plurality of conductive elements made of such as a solder material, the conductive elements can come into contact with a plurality of surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the first conductive pads, thereby strengthening the bonding between the conductive elements and the first conductive pads and preventing delamination of the conductive elements from the first conductive pads. Therefore, the product reliability is improved.

(47) Further, even if the surface of the first circuit layer is lower than the first surface of the dielectric layer, the conductive bumps protruding above the first surface of the dielectric layer ensure sufficient wetting of the conductive elements so as to cause the conductive elements to be in effective contact with the conductive bumps so as to be electrically connected to the first conductive pads, thereby improving the product reliability.

(48) The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.