SEMICONDUCTOR SWITCHING STRING

Abstract

A semiconductor switching string including a series-connected switching assemblies. Each assembly has a main switching element including first and second connection terminals which current flows between when the main switching element is on. The main element has an auxiliary element between the connection terminals. The string includes a local control unit connected with each auxiliary element which are programmed to switch an auxiliary element to create an alternative current path between the connection terminals that diverts current through to reduce the voltage across the corresponding main switching element. The local unit is programmed to control switching an auxiliary element to a fully-on mode in which the auxiliary element is at maximum rated base current, a pulsed mode which turns the auxiliary element on and off and/or an active mode operating the auxiliary element with a continuously variable base current. The string includes a higher level control unit programmed to implement the modes.

Claims

1. A semiconductor switching string, for use in a power converter, comprising: a plurality of series-connected semiconductor switching assemblies, each semiconductor switching assembly having a main semiconductor switching element including first and second connection terminals between which current flows from the first terminal to the second terminal when the main semiconductor switching element is switched on, the main semiconductor switching element having an auxiliary semiconductor switching element electrically connected between the first and second connection terminals thereof; a local control unit operatively connected with each auxiliary semiconductor switching element, the or each local control unit being programmed to control switching of a respective auxiliary semiconductor switching element to selectively create an alternative current path between the first and second connection terminals associated therewith whereby current is diverted to flow through the alternative current path to reduce the voltage across the corresponding main semiconductor switching element, the or each local control unit being so programmed to selectively control switching of a respective auxiliary semiconductor switching element in a fully-on mode in which the auxiliary semiconductor switching element is operated with its maximum rated base current or gate voltage, and one or both of a pulsed switched mode in which the auxiliary semiconductor switching element is turned on and off and an active mode in which the auxiliary semiconductor switching element is operated with a continuously variable base current or gate voltage; and a higher level control unit arranged in communication with the or each local control unit and programmed to selectively implement: (i) a first model based control methodology to collectively operate via the or each local control unit each auxiliary semiconductor switching element in the fully-on mode; and (ii) a second active control based control methodology to selectively and collectively operate via the or each local control unit each auxiliary semiconductor switching element in one or both of the pulsed switched mode and the active mode.

2. The semiconductor switching string according to claim 1 wherein the higher level control unit is programmed to selectively implement a first model based control methodology includes having the higher level control unit programmed to establish when each main semiconductor switching element turns off and upon turn off of a respective main semiconductor switching element thereafter operate the corresponding auxiliary semiconductor switching element in its fully-on mode for a first time period.

3. The semiconductor switching string according to claim 2 wherein the higher level control unit is programmed to establish when each main semiconductor switching element turns off includes detecting when a given main semiconductor switching element turns off by comparing the voltage thereacross with the voltage across an adjacent main semiconductor switching element.

4. The semiconductor switching string according to claim 3 wherein comparing the voltage across a given main semiconductor switching element with the voltage across an adjacent main semiconductor switching element includes measuring the difference between the voltages and initiating operation of the auxiliary semiconductor switching element corresponding to the given main semiconductor switching element in its fully-on mode when the difference between the voltages exceeds a voltage threshold.

5. The semiconductor switching string according to claim 2 wherein the higher level control unit is programmed to establish when each main semiconductor switching element turns off includes estimating when a given main semiconductor switching element turns off according to the time elapsed since it was turned on.

6. The semiconductor switching string according to claim 5 wherein estimating when a given main semiconductor switching element turns off includes initiating operation in its fully-on mode of the corresponding auxiliary semiconductor switching element at the estimated turn off time.

7. The semiconductor switching string according to claim 2 wherein the higher level control unit is programmed to operate a corresponding auxiliary semiconductor switching element in its fully-on mode for a first time period includes pre-calculating the length of the first time period.

8. The semiconductor switching string according to claim 7 wherein pre-calculating the length of the first time period includes establishing a transfer function representative of the voltage transfer characteristics of the semiconductor switching string when operating in a blocking mode within in a limb portion of a converter limb in a power converter, with all main semiconductor switching elements in the semiconductor switching string turned off.

9. The semiconductor switching string according to claim 8 wherein establishing a transfer function includes considering the time response of the transfer function and the associated time constant with a dominant effect on a voltage overshoot of the semiconductor switching string.

10. The semiconductor switching string according to claim 1 wherein the higher level control unit is programmed to selectively implement a second active control based control methodology includes having the higher level control unit programmed to minimise the deviation of a measured characteristic associated with each main semiconductor switching element from a desired parameter.

11. The semiconductor switching string according to claim 10 wherein the higher level control unit is programmed to minimise the deviation of a measured characteristic associated with each main semiconductor switching element from a desired parameter includes, for each main semiconductor switching element, generating an error signal representative of the deviation, regulating the error signal to compensate for the deviation and thereby produce a control signal, and generating a switching signal from the control signal to operate the corresponding auxiliary semiconductor switching element in one or both of the pulsed mode and the active mode.

12. The semiconductor switching string according to claim 11 wherein generating an error signal includes comparing the voltage across each main semiconductor switching element against a desired value.

13. The semiconductor switching string according to claim 12 wherein the desired value is one of: an average of the voltage across a given main semiconductor switching element and the voltage across an adjacent main semiconductor switching element; an average of the voltage across all main semiconductor switching elements in the semiconductor switching string; and an estimated voltage.

14. The semiconductor switching string according to claim 11 wherein regulating the error signal includes amplifying the error signal in a proportional manner.

15. The semiconductor switching string according to claim 11 wherein generating a switching signal from the control signal includes one of: utilising pulse-width modulation of constant or varying switching frequency; and scaling the control signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] There now follows a brief description of embodiments of the invention, by way of non-limiting example, with reference being made to the following drawings in which:

[0039] FIG. 1 shows semiconductor switching string;

[0040] FIG. 2 shows a semiconductor switching assembly of the semiconductor switching string shown in FIG. 1;

[0041] FIG. 3 illustrates a switching operation of an auxiliary semiconductor switching element of the semiconductor switching assembly shown in FIG. 2;

[0042] FIG. 4 illustrates schematically a first model based control methodology implemented by a higher level controller of the semiconductor switching string shown in FIG. 1;

[0043] FIG. 5 shows a simplified equivalent circuit which can be used to establish a voltage transfer function for the semiconductor switching string shown in FIG. 1;

[0044] FIG. 6 illustrates schematically a second active control based control methodology implemented by the higher level controller of the semiconductor switching string shown in FIG. 1;

[0045] FIG. 7A illustrates schematically the generation of a first switching signal by the higher level controller shown in FIG. 1; and

[0046] FIG. 7B illustrates schematically the generation of a second switching signal by the higher level controller shown in FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

[0047] A semiconductor switching string according to embodiments of the invention is designated generally by reference numeral 10, as shown in FIG. 1.

[0048] The semiconductor switching string 10 includes a plurality of series-connected semiconductor switching assemblies 12. Three such semiconductor switching assemblies 12A, 12B, 12C are shown in FIG. 1, by way of illustration, whereas in practice the semiconductor switching string 10 is likely to include many tens or hundreds of semiconductor switching assemblies 12.

[0049] As shown in FIG. 2, each semiconductor switching assembly 12 has a main semiconductor switching element 14 that includes first and second connection terminals 16, 18. In the embodiment shown the main semiconductor switching element 14 is a main thyristor 20, although in other embodiments of the invention a different semiconductor switching element may be used such as a diode, Light-Triggered Thyristor (LTT), Gate Turn-Off thyristor (GTO), Gate Commutated Thyristor (GCT) or Integrated Gate Commutated Thyristor (IGCT). In an embodiment, the main semiconductor switching element 14 is optimised for lowest conduction (on-state) losses at the expense of other parameters such as turn-on and turn-off characteristics and off-state dv/dt capability.

[0050] The main thyristor 20 shown includes an anode 22 which defines the first connection terminal 16, a cathode 24 which defines the second connection terminal 18, and a gate 26 that defines a control terminal 28 via which the main thyristor 14 may be switched on, e.g. by a corresponding gate control unit 30.

[0051] When the main thyristor 14 is so switched on, i.e. turned-on fully, current flows through the main thyristor 14 from the first connection terminal 16 to the second connection terminal 18, i.e. from the anode 22 to the cathode 24.

[0052] The main thyristor 14 includes an auxiliary semiconductor switching element 32 which is electrically connected between the first and second connection terminals 16, 18 of the main thyristor 14, and the auxiliary semiconductor switching element 32 has a local control unit 34 that is operatively connected therewith. In the embodiment shown, each auxiliary semiconductor switching element 32 has a corresponding local control unit 34 operatively connected therewith whereas in other embodiments of the invention two or more auxiliary semiconductor switching elements 32 may share a local control unit 34.

[0053] Returning to the embodiment shown, each local control unit 34 is programmed to control switching of the corresponding auxiliary semiconductor switching element 32 to selectively create an alternative current path 36 between the first and second connection terminals 16, 18.

[0054] In the embodiment shown the auxiliary semiconductor switching element 32 is connected in inverse-parallel with the main thyristor 14 (although this need not necessarily be the case) such that when the auxiliary semiconductor switching element 32 is switched on the resulting alternative current path 36 is configured to allow current to flow from the second connection terminal 18 to the first connection terminal 16.

[0055] More particularly, the auxiliary semiconductor switching element 32 includes a transistor 38 which has a source that is connected to the first connection terminal 16 of the main thyristor 14, a drain that is connected to the second connection terminal 18 of the main thyristor 14, and a gate that is connected to the local control unit 34.

[0056] The transistor 38 shown schematically in FIG. 2 is a metal-oxide-semiconductor field effect transistor (MOSFET), although many other transistors may also be used such as, for example, a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), or a junction gate field-effect transistor (JFET). A transistor assembly, such as a MOSFET-JFET cascode circuit incorporating a super-cascode arrangement of 50V MOSFETs and a series string of 1200V SiC JFETs, or a direct series connection of low voltage MOSFETs or IGBTs, may also be used.

[0057] It will be appreciated that, depending on the type of transistor, one or more of the terms source, drain and gate may be respectively replaced by the terms emitter, collector and base. By way of example, whilst a MOSFET and a JFET each has a source, drain and gate combination, an IGBT has an emitter, collector and gate combination while a BJT has an emitter, collector and base combination.

[0058] The auxiliary semiconductor switching element 32 shown in FIG. 2 also includes an optional current limiting element, in the form of a resistor 39, which is connected in series with the transistor 38.

[0059] As well as having the auxiliary semiconductor switching element 32 connected in inverse-parallel therewith, the main thyristor 20 also has a passive damping circuit 40, which includes a damping capacitor 42 and a damping resistor 44, connected in parallel between the first and second connection terminals 16, 18. Other embodiments of the invention may, however, omit the passive damping circuit 40.

[0060] In use an ideal thyristor would cease to conduct exactly at the instant when the current flowing through the thyristor falls to zero. However a real thyristor, such as each of the main thyristors 20A, 20B, 20C shown in FIG. 1, continues to conduct current in a reverse direction (even when the main thyristor 20 is in a so-called reverse-biased condition) for some hundreds of microseconds after the current falls to zero. The time integral of this reverse current is the reverse recovered charge (Q.sub.rr), i.e. stored charge, of the main thyristor 20A, 20B, 20C.

[0061] In the embodiment shown, a first main thyristor 20A has a lower Q.sub.rr than, e.g. a second main thyristor 20B in an otherwise identical second semiconductor switching assembly 12B which is connected in series with the first semiconductor switching assembly 12A that includes the first main thyristor 20A.

[0062] The aforementioned difference in Q.sub.rr between the first and second main thyristors 20A, 20B arises due to manufacturing tolerances/imperfections e.g. while introducing dopants into the first main thyristor 20A and the second main thyristor 20B. As a result the first main thyristor 20A will establish peak reverse current and start supporting reverse blocking voltage sooner than in the second main thyristor 20B.

[0063] When the first and second main thyristors 20A, 20B are connected in the series arrangement shown in FIG. 1 the current flowing through the first semiconductor switching assembly 12A must be the same as the current flowing through the second semiconductor switching assembly 12B and thus the difference in reverse current flows through the passive damping circuit 40 of the first main thyristor. Also, since the first main thyristor 20A establishes reverse blocking voltage sooner this causes the voltage V.sub.A across the first main thyristor 20A to reach a larger reverse peak voltage, than the second main thyristor 20B with a higher Q.sub.rr.

[0064] Such operation, if left un-checked, gives rise to a voltage offset V between the voltage V.sub.A across the first main thyristor 20A and the voltage V.sub.B across the second main thyristor 20B, where the voltage offset V is given by:

V=Q.sub.rr/C.sub.d

[0065] Where Q.sub.rr is the difference in charge stored by the second main thyristor 20B and the first main thyristor 20A, and C.sub.d is the value of the damping capacitor 42.

[0066] Such a voltage offset can persist for a long time such that it does not decay significantly before the first main thyristor 20A is turned on again approximately 120 electrical degrees later after blocking. Such a voltage offset can also significantly affect the timing point at which the voltage across a given main thyristor 20 crosses zero. This impacts on the accuracy of an extinction angle that must be established, e.g. when the main thyristors 20A, 20B, 20C form part of a HVDC power converter which is operating as an inverter and requires that the extinction angle includes a margin to accommodate such variations in stored charge.

[0067] However, in the semiconductor switching string 10 shown, each local control unit 34 is programmed to switch on the corresponding auxiliary semiconductor switching element 32, i.e. the corresponding transistor 38, while the corresponding main thyristor 20A, 20B, 20C is in the aforementioned reverse-biased condition and while a reverse current is flowing through the said main thyristor 20A, 20B, 20C, to create the corresponding alternative current path 36 and thereby divert the reverse current through the corresponding alternative current path 34. Such diversion of the reverse current through the corresponding alternative current path 36 prevents this current flowing into the associated damping circuit 40 (and so is equivalent to reducing the effective off-state impedance of the corresponding main thyristor 20A, 20B, 20C) such that the resulting voltage across the corresponding main thyristor 20A, 20B, 20C is reduced.

[0068] More particularly, each local control unit 34 is programmed to control the amount of current directed to flow through the corresponding alternative current path 36 by switching the corresponding transistor 38 within a switching operation in which the transistor 34 operates in a fully-on mode followed by a pulsed switched mode followed by an active mode during a given operating cycle of the semiconductor switching string 10, i.e. while each main semiconductor switching element 14, i.e. the main thyristors 20A, 20B, 20C, is in the reverse-biased condition.

[0069] Further details of the switching operation of the transistor 34 is described as follows, with reference to FIG. 3.

[0070] During the commutation overshoot transient 46 of the corresponding main thyristor 20A, 20B, 20C (i.e. when the highest amount of reverse current 48 is required to flow in the alternative current path 36), the transistor 38 is operated in the fully-on mode in which the transistor 34 is operated with its maximum rated gate voltage.

[0071] Following the operation of the transistor 38 in the fully-on mode and at intermediate values of the reverse current 48 required to flow in the alternative current path 36, the transistor 38 is operated in the pulsed switched mode in which the transistor 38 is turned on and off a plurality of times. This helps to ensure that the level of reverse current 48 flowing through the alternative current path 36, and hence the level of reverse current 48 flowing through the transistor 38, remains at a level required to compensate for the aforementioned variation in turn-off performance characteristics of the corresponding first main thyristor 20A, e.g. to compensate for a variation in Q.sub.rr between the main thyristors 20A, 20B, 20C.

[0072] During the pulsed switched mode, the transistor 38 is intermittently operated in the active mode in which the transistor 38 is operated with a continuously variable gate voltage. More specifically, while the transistor 38 is turned on and off during the pulsed switched mode the transistor 38 is operated in the active mode during each transition period between turned-on and turned-off states of the auxiliary semiconductor switching element, whereby the reverse current 48 flowing in the alternative current path 36 ramps up or down during each transition period. Combining the pulsed switch and active modes in this manner results in a more gradual ramp 50 of the reverse current 48 in each transition period, and thereby eliminates the problems normally associated with voltage step changes being imposed across the corresponding main thyristor 20A, 20B, 20C whilst continuing to provide the desired control over the level of reverse current 48 flowing through the alternative current path 36.

[0073] Following the pulsed switched mode, the transistor 38 is then operated in the active mode at low values of the reverse current 48 required to flow in the alternative current path 36. This provides fine control of the voltage across the corresponding main thyristor 20A, 20B, 20C, e.g. to compensate for residual voltage imbalance between the main thyristors 20A, 20B, 20C which may be caused by one or more other sources.

[0074] It will be appreciated that operation of the transistor 38 in the active mode may include operation of the transistor 38 in its linear region and/or saturation region.

[0075] In addition to the foregoing, the semiconductor switching string includes a higher level control unit 52 that is arranged in communication with each local control unit 34, and additionally with each gate control unit 30.

[0076] The higher level control unit 52 illustrated in FIG. 1 is shown as being discrete from each of the local control units 34 and gate control units 30. In other embodiments of the invention, however, the or each local control unit 34 and the or each gate control unit 30 and the higher level control unit 52 may be integrally formed within a single control module (not shown). In still further embodiments of the invention the higher level control unit 52 may be implemented as a control module within a local control unit 34 or gate control unit 30.

[0077] In any event, the higher level control unit 52 is programmed to implement: (i) a first model based control methodology to collectively operate, via each local control unit 34, each auxiliary semiconductor switching element 32 in the fully-on mode; and (ii) a second active control based control methodology to selectively and collectively operate, again via each local control unit 34, each auxiliary semiconductor switching element 32 in both the pulsed switched mode and the active mode.

[0078] The manner in which the higher level control unit 52 is programmed to implement each of the aforementioned control methodologies is described in more detail below.

[0079] In the first instance the higher level control unit 52 may be programmed to implement a first model based control methodology such as a transfer function or state-space relationship based control methodology.

[0080] In any event, having the higher level control unit 52 programmed to selectively implement a first model based control methodology includes having the higher level control unit 52 programmed to establish when each main semiconductor switching element turns off 14, i.e. each main thyristor 20A, 20B, 20C turns off.

[0081] In addition it includes having the higher level control unit 52 programmed, upon turn off of a respective main thyristor 20A, 20B, 20C, to thereafter operate the corresponding auxiliary semiconductor switching element 32 in its fully-on mode for a first time period t.sub.ON.

[0082] More particularly, establishing when each main thyristor 20A, 20B, 20C element turns off includes detecting when a given main thyristor 20A, 20B, 20C turns off by comparing the voltage V.sub.A, V.sub.B, V.sub.C thereacross with the voltage V.sub.A, V.sub.B, V.sub.C across an adjacent main thyristor 20A, 20B, 20C, i.e. another main thyristor 10A, 20B, 20C lying next to the aforesaid given main thyristor 20A, 20B, 20C in the semiconductor switching string 10.

[0083] More particularly still, comparing the voltage V.sub.A, V.sub.B, V.sub.C across a given main thyristor 20A, 20B, 20C with the voltage V.sub.A, V.sub.B, V.sub.C across an adjacent main thyristor 20A, 20B, 20C includes measuring the difference d.sub.A, d.sub.B, d.sub.C between the voltages V.sub.A, V.sub.B, V.sub.C and initiating operation of the auxiliary semiconductor switching element 32 (that corresponds to the given main thyristor 20A, 20B, 20C) in its fully-on mode when the difference d.sub.A, d.sub.B, d.sub.C between the voltages V.sub.A, V.sub.B, V.sub.C exceeds a voltage threshold 54.

[0084] In the embodiment shown, the voltage V.sub.A, V.sub.B, V.sub.C across each individual main thyristor 20A, 20B, 20C is measured by the corresponding gate control unit 30 and is then passed to the local control unit 34 of the corresponding auxiliary semiconductor switching element 32, which then establishes the difference d.sub.A, d.sub.B, d.sub.C between the voltages V.sub.A, V.sub.B, V.sub.C.

[0085] In this manner the higher level control unit 52 is programmed to delegate the step of establishing when each main thyristor 20A, 20B, 20C turns off and the step of operating the corresponding auxiliary semiconductor switching element 32 in its fully-on mode for a first time period t.sub.ON to each corresponding local control unit 34, i.e. as shown schematically in FIG. 4.

[0086] In other embodiments of the invention the individual voltages may be obtained in a different manner and operation of each auxiliary semiconductor switching element may be done in a different way, e.g. principally by the higher level control unit 52.

[0087] In still further embodiments of the invention (not shown) having the higher level control unit 52 programmed to establish when each main thyristor 20A, 20B, 20C turns off may include estimating when a given main thyristor 20A, 20B, 20C turns off according to the time elapsed since it was turned on. In such other embodiments of the invention operation of the corresponding auxiliary semiconductor switching element 32 in its fully-on mode is initiated at the estimated turn off time.

[0088] Meanwhile, operating a corresponding auxiliary semiconductor switching element 32 in its fully-on mode for a first time period t.sub.ON includes pre-calculating the length of the first time period t.sub.ON.

[0089] In the embodiment shown the higher level controller 52 is programmed to implement a first model based control methodology in the form of a transfer function control methodology, and so pre-calculating the length of the first time period t.sub.ON includes establishing a transfer function that is representative of the voltage transfer characteristics of the semiconductor switching string 10 when it is operating in a blocking mode within in a limb portion of a converter limb in a power converter, i.e. when the semiconductor switching string 10 lies in a said limb portion and all of the main thyristors 20A, 20B, 20C in the semiconductor switching string 10 are turned off.

[0090] In other embodiments of the invention, pre-calculating the length of the first time period t.sub.ON may instead include establishing a state-space representation of the voltage transfer characteristics of the semiconductor switching string 10 when it is operating in a blocking mode within in a limb portion of a converter limb in a power converter.

[0091] Returning to the embodiment shown, and by way of example, FIG. 5 shows a simplified equivalent circuit 56 which can be used to model the voltage transfer characteristics of a fourth equivalent switch 58D that is defined by the semiconductor switching string 10 described hereinabove.

[0092] The fourth switch 58D is one of six essentially identical equivalent switches 58A, 58B, 58C, 58D, 58E, 58F, each of which lies within a corresponding limb portion 60A, 60B, 60C, 60D, 60E, 60F of a corresponding converter limb 62, 64, 66. The converter limbs 62, 64, 66 are arranged together in a six-pulse bridge to define a three-phase power converter 68, which extends between first and second DC terminals 70, 72 of a DC network 74 and respective AC terminals 76, 78, 80 of a three phase AC network 82. Each of the main thyristors 20A, 20B, 20C in the fourth switch 58D are turned off such that the corresponding limb portion 60D is said to be blocking.

[0093] In this way the equivalent circuit 56 is able to describe to a desired extent the interaction between the damping circuit 40 within the semiconductor switching string 10 and other elements within the power converter 68.

[0094] More particularly, such interaction can be described by:

[00001]$Z_{\mathrm{TX}}=R_{\mathrm{TX}}+{\mathrm{sL}}_{\mathrm{TX}}$$Z_D+{\mathrm{sL}}_{\mathrm{STRAY}}=\left(R_D+{\mathrm{sL}}_D+\frac{1}{{\mathrm{sC}}_D}\right).Math.n_{\mathrm{LEVELS}}+{\mathrm{sL}}_{\mathrm{STRAY}}$

with an associated transfer function in the complex domain being given by:

[00002]$\frac{V_4}{V_{S.Math..Math.3}}=\frac{Z_D+{\mathrm{sL}}_{\mathrm{STRAY}}}{Z_{\mathrm{TX}}+Z_D+{\mathrm{sL}}_{\mathrm{STRAY}}}=\frac{\left(R_d+{\mathrm{sL}}_d+\frac{1}{{\mathrm{sC}}_d}\right).Math.n_{\mathrm{LEVELS}}+{\mathrm{sL}}_{\mathrm{STRAY}}}{R_{\mathrm{TX}}+{\mathrm{sL}}_{\mathrm{TX}}+\left(R_d+{\mathrm{sL}}_d+\frac{1}{{\mathrm{sC}}_d}\right).Math.n_{\mathrm{LEVELS}}+{\mathrm{sL}}_{\mathrm{STRAY}}}$

where V.sub.4 is the voltage across the fourth equivalent switch 58D, i.e. the blocking voltage supported by the semiconductor switching string 10; V.sub.S3 is the AC voltage at the corresponding AC terminal 76; Z.sub.TX is a simplified AC network 82 and associated transformer impedance which can be represented by a series resistance R.sub.TX and a series inductance L.sub.TX; L.sub.STRAY is a lumped parameter representing the inductance within the corresponding limb portion 60D (which may be made up of a residual inductance of saturated reactors (not shown) within the limb portion 60D as well as any stray bus-bar inductance within the limb portion 60D); Z.sub.D is the equivalent combined impedance made up of individual contributions from the damping circuit 40 associated with each main thyristor 20A, 20B, 20C in the semiconductor switching string (with each damping circuit 40 having an individual resistance R.sub.d, i.e. the damping resistor 44, an individual capacitance Ca, i.e. the damping capacitor 42, and an individual inductance L.sub.d); and n.sub.LEVELS is the number of main thyristors 20A, 20B, 20C in the semiconductor switching string 10 (i.e. the number of damping circuits 40 in the semiconductor switching string 10).

[0095] Multiplying the numerator and denominator by s/s to eliminate the 1/s term of Ca gives

[00003]$\frac{s.R_d.n_{\mathrm{LEVELS}}+s^2.L_d,n_{\mathrm{LEVELS}}+\frac{n_{\mathrm{LEVELS}}}{C_d}+s^2.L_{\mathrm{STRAY}}}{\begin{array}{c}s.R_{\mathrm{TX}}+s^2.L_{\mathrm{TX}}+s.R_d.n_{\mathrm{LEVELS}}+\\ s^2.L_d.n_{\mathrm{LEVELS}}+\frac{n_{\mathrm{LEVELS}}}{C_d}+s^2.L_{\mathrm{STRAY}}\end{array}}$

and then collecting the terms in the numerator and denominator gives

[00004]$\frac{\left(L_d.Math.n_{\mathrm{LEVELS}}+L_{\mathrm{STRAY}}\right).Math.s^2+\left(R_d.Math.n_{\mathrm{LEVELS}}\right).Math.s+\left(\frac{n_{\mathrm{LEVELS}}}{C_d}\right)}{\begin{array}{c}\left(L_{\mathrm{TX}}+L_d.Math.n_{\mathrm{LEVELS}}+L_{\mathrm{STRAY}}\right).Math.s^2+\\ \left(R_{\mathrm{TX}}+R_d.n_{\mathrm{LEVELS}}\right).Math.s+\left(\frac{n_{\mathrm{LEVELS}}}{C_d}\right)\end{array}}$

[0096] Dividing and rearranging to get unity co-efficient for s2, and using

R.sub.D=R.sub.d.Math.n.sub.LEVELS;

L.sub.D=L.sub.d.Math.n.sub.LEVELS; and

C.sub.D=C.sub.d/n.sub.LEVELS

gives a final transfer function of the form:

[00005]$\frac{\left(\frac{L_D+L_{\mathrm{STRAY}}}{L_{\mathrm{TX}}+L_D+L_{\mathrm{STRAY}}}\right).Math.\left(s^2+s.Math.\frac{R_D}{L_D+L_{\mathrm{STRAY}}}+\frac{1}{C_D\left(L_D+L_{\mathrm{STRAY}}\right)}\right)}{s^2+s\left(\frac{R_{\mathrm{TX}}+R_D}{L_{\mathrm{TX}}+L_D+L_{\mathrm{STRAY}}}\right)+\left(\frac{1}{\left(L_{\mathrm{TX}}+L_D+L_{\mathrm{STRAY}}\right).Math.C_D}\right)}$

[0097] Thereafter the higher level control unit 52 considers the time response of the above-derived transfer function and the associated time constant with a dominant effect on a voltage overshoot of the semiconductor switching string 10.

[0098] More particularly, the higher level control unit 52 is programmed to compare the above-derived transfer function with a standard transfer function of the form

[00006]$\frac{K_b\left(1+T_1.Math.s\right).Math.\left(1+T_2.Math.s\right).Math.\mathrm{.Math.}.Math..Math.\left(1+T_n.Math.s\right)}{\left(1+T_a.Math.s\right).Math.\left(1+T_b.Math.s\right).Math.\mathrm{.Math.}\left(1+T_m.Math.s\right)}$

in order to focus on the gain K.sub.b and time constants T.sub.1, T.sub.2, . . . T.sub.n of the transfer function describing the behaviour of the semiconductor switching string 10 of embodiments of the invention.

[0099] As an alternative, in other embodiments of the invention, the above-derived transfer function may instead be compared with a standard transfer function of the form

[00007]$\frac{{}_n^2}{s^2+2.Math..Math..Math.{}_n.Math.s+{}_n^2}$

where: .sub.n describes the undamped natural frequency of the semiconductor switching string 10; and is a damping factor (i.e. a measure of how damped the response of the semiconductor switching string 10 is).

[0100] Returning to the comparison first mentioned above, the gain K.sub.b is given by

[00008]$K_b=\left(\frac{L_D+L_{\mathrm{STRAY}}}{L_{\mathrm{TX}}+L_D+L_{\mathrm{STRAY}}}\right)$

while the time constants T.sub.1, T.sub.2, . . . T.sub.n are obtained as follows:

[00009]$f\left(s\right)=s^2+s.Math.\frac{R_D}{L_D+L_{\mathrm{STRAY}}}+\frac{1}{C_D\left(L_D+L_{\mathrm{STRAY}}\right)}$

with the assumption that

f(s)=(s+a)(s+b) . . . (s+c)

where, a, b, c are the roots of the expression for f(s) that indicate zeros for the derived transfer function, such that

[00010]$T_1=\frac{1}{a};T_2=\frac{1}{b};T_n=\frac{1}{c}$

[0101] The time response (t) of a transfer function may be expressed by considering the zeros of the transfer function, such that

[00011]$f\left(t\right)=K_b\left(e^{-\frac{t}{T_1}}+e^{-\frac{t}{T_2}}+\mathrm{.Math.}.Math..Math.e^{-\frac{t}{T_n}}\right)$

[0102] It follows that the zero with a dominant effect on the voltage overshoot of the semiconductor switching string 10 as a whole, indeed with the most dominant effect on the said voltage overshoot, is the zero with the smallest time constant T.sub.1, T.sub.2, . . . T.sub.n.

[0103] In the embodiment described the smallest time constant is taken as T.sub.1 such that the calculated duration of the first time period torr, i.e. the period of time for which each auxiliary switching element 32 is operated in its fully-on mode, is given by

t.sub.ON=1/T.sub.1

[0104] In the second instance, having the higher level control unit 52 programmed to selectively implement a second active control based control methodology includes having the higher level control unit 52 programmed to minimise the deviation of a measured characteristic associated with each main semiconductor switching element, i.e. each main thyristor 20A, 20B, 20C, from a desired parameter.

[0105] In this manner the higher level control unit 52 is programmed to implement a second active control based control methodology in the form of a servo control based control methodology, and more particularly a proportional servo control based control methodology.

[0106] Other active control based control methodologies, such as differential control and integral control, may also be used however.

[0107] In the embodiment shown, the higher level control unit 52 is programmed to eliminate the deviation of the measured characteristic associated with each main thyristor 20A, 20B, 20C from the desired parameter, and more particularly is programmed, for each main thyristor 20A, 20B, 20C, to: generate an error signal e.sub.A, e.sub.B, e.sub.C representative of the deviation; regulate the error signal e.sub.A, e.sub.B, e.sub.C to compensate for the deviation and thereby produce a control signal m.sub.refA, m.sub.refB, m.sub.refC; and generate a switching signal V.sub.GS, i.e. a gate voltage for the gate of the corresponding auxiliary switching element 32, from the control signal mref.sub.A, mref.sub.B, Mref.sub.C to operate the corresponding auxiliary semiconductor switching element 32 in each of the pulsed mode and the active mode.

[0108] More particularly still, the higher level controller 52 is programmed to delegate the aforementioned steps to each corresponding local control unit 34, as illustrated schematically in FIG. 6. In other embodiments of the invention, however, this need not necessarily be the case.

[0109] In the embodiment shown, each local control unit 34 generates an error signal e.sub.A, e.sub.B, e.sub.C by comparing the voltage V.sub.A, V.sub.B, V.sub.C across each main thyristor 20A, 20B, 20C against a desired value in the form of an average of the voltage across a given main thyristor 20A, 20B, 20C and the voltage across an adjacent main thyristor 20A, 20B, 20C.

[0110] In other embodiments of the invention the desired value may be an average of the voltage across all main thyristors 20A, 20B, 20C in the semiconductor switching string 10, or an estimated voltage such as might be obtained by mathematical estimation or calculation.

[0111] In further embodiments of the invention (not shown), each local control unit 34 (or the higher level control unit 52) may generate an error signal by comparing the damping current, i.e. the current flowing through the passive damping circuit 40, with a desired reference current, or by comparing the impedance of the auxiliary semiconductor switching element 32 with a desired reference impedance.

[0112] In the meantime, returning to the embodiment shown, each local control unit 34 regulates the error signal e.sub.A, e.sub.B, e.sub.C by amplifying the error signal e.sub.A, e.sub.B, e.sub.C in a proportional manner.

[0113] Each local control unit 34 achieves this by applying a proportional gain k.sub.P to the error signal e.sub.A, e.sub.B, e.sub.C.

[0114] Such a proportional gain k.sub.P may be selected by using trial and error with the gain value k.sub.P chosen and adjusted until the semiconductor switching string 10 exhibits desired behaviour.

[0115] The proportional gain k.sub.P may also be selected by considering a mathematical model of the semiconductor switching string 10, e.g. as defined by a transfer function.

[0116] For example, since the behaviour of the fourth equivalent switch 58D, i.e. the semiconductor switching string 10 including a passive damping circuit 40 is known, this can be used as basis for selecting the proportional gain k.sub.P, such that:

[00012]$k_P=\frac{1}{R_d.Math.I_{D.Math..Math.\_.Math..Math.\mathrm{BASE}}}$

where R.sub.d is the damping resistance, i.e. the damping resistor 44; and/D BASE is the peak current that flows in the passive damping circuit 40.

[0117] In addition to the foregoing, each local control unit 34 generates a switching signal V.sub.GS from the control signal m.sub.refA, m.sub.refB, m.sub.refC, when operating the corresponding auxiliary semiconductor switching element 32 in its pulsed switched mode, by using pulse-width modulation, as shown in FIG. 7(a).

[0118] More particularly, each local control unit 34 compares the control signal m.sub.refA, m.sub.refB, m.sub.refC against a carrier-type waveform 84, such as a triangular or sawtooth waveform so as to provide a switching signal V.sub.GS with switching pulses of a constant period T given by

T=t.sub.ON+t.sub.OFF

where the duty cycle, i.e.

t.sub.ON/T

is varied in proportion with the control signal mref.sub.A, mref.sub.B, Mref.sub.C to achieve compensation, i.e. to diminish the error.

[0119] Accordingly, for a period when the voltage V.sub.A of the first thyristor 20A is greater than the voltage V.sub.B of the second thyristor 20B, the error signal e.sub.A is given by

[00013]$e_A=\frac{V_A-V_B}{2}$

and the control signal m.sub.refA is given by

[00014]$m_{\mathrm{refA}}=\frac{V_A-V_B}{R_d.Math.I_{D.Math..Math.\_.Math..Math.\mathrm{BASE}}}$

[0120] The resulting control action is such that as the error e.sub.A between the compared thyristor voltages V.sub.A, V.sub.B increases, the control signal m.sub.refA increases. This switches the auxiliary semiconductor switching element 32 on for longer when switching signal V.sub.GS generation is carried out, i.e. the auxiliary semiconductor switching element 32 and associated impedance, i.e. as provided by the current limiting resistor 39 therein, is left in circuit for longer with the consequence of reducing the voltage difference until the error e.sub.A is eliminated.

[0121] In another embodiment of the invention (not shown), each local control unit 34 (or the higher level control unit 52) may additionally vary the switching frequency of the corresponding auxiliary semiconductor switching element 32. Such a step might be carried out in order to optimize any losses in the said corresponding auxiliary semiconductor switching element 32. For instance the switching frequency may be reduced when the voltage V.sub.A, V.sub.B, V.sub.C across the corresponding main thyristor 20A, 20B, 20C is high and increased when the voltage V.sub.A, V.sub.B, V.sub.C is low.

[0122] Meanwhile, when operating the corresponding auxiliary semiconductor switching element 32 in its active mode, each local control unit 34 generates a switching signal V.sub.GS by scaling the control signal m.sub.refA, m.sub.refB, m.sub.refC, as shown in FIG. 7(b). Such a configuration means that a high control signal mref.sub.A, mref.sub.B, Mref.sub.C results in a low switching signal V.sub.GS, and thus a high impedance in the alternative current path 36, i.e. as provided by the corresponding auxiliary semiconductor switching element 32, and more particularly the impedance included therewithin by way of the resistor 39, being switched into circuit.

[0123] This written description uses examples to disclose the invention, including the preferred embodiments, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.