RADIOFREQUENCY AMPLIFIER

Abstract

According to one aspect, an integrated circuit having a radio frequency amplifier includes at least two amplifier stages and an impedance matching device between two amplifier stages of the radio frequency amplifier. The matching device includes two lines which are coupled by electromagnetic induction. The first line is connected to an output of the first amplifier stage and the second line is connected to an input of the second amplifier stage.

Claims

1-12. (canceled)

13. An integrated circuit, comprising: a radio frequency amplifier, comprising: a first amplifier stage; a second amplifier stage; and an impedance matching circuit comprising a first inductive line and a second inductive line coupled to each other through electromagnetic induction, the first inductive line coupled to an output of the first amplifier stage, and the second inductive line coupled to an input of the second amplifier stage.

14. The integrated circuit of claim 13, wherein the second inductive line is dimensioned such that the second inductive line compensates for an input capacitive component of the second amplifier stage.

15. The integrated circuit of claim 13, wherein the first inductive line is dimensioned such that the first inductive line allows meeting a real portion of a required load at the output of the first amplifier stage.

16. The integrated circuit of claim 13, wherein the first inductive line and the second inductive line are disposed to maximize a coupling factor between the first inductive line and the second inductive line.

17. The integrated circuit of claim 13, wherein the first inductive line comprises: a first terminal coupled to the first amplifier stage; and a second terminal coupled to a decoupling capacitive element.

18. The integrated circuit of claim 17, wherein the first terminal is coupled to the first amplifier stage via an inductive element.

19. The integrated circuit of claim 13, wherein the first amplifier stage and the second amplifier stage are configured to obtain a ratio of less than 5 between a resistance at the input of the second amplifier stage and a resistance of a load desired at the output of the first amplifier stage.

20. The integrated circuit of claim 13, wherein the first inductive line and the second inductive line are wound around each other.

21. The integrated circuit of claim 20, wherein the first inductive line and the second inductive line are wound around a decoupling capacitive element coupled to the first inductive line or the second inductive line.

22. The integrated circuit of claim 13, wherein the radio frequency amplifier is a complementary metal-oxide semiconductor (CMOS) type radio frequency amplifier.

23. The integrated circuit of claim 13, wherein the first amplifier stage is a driver stage, and wherein the second amplifier stage is a power stage.

24. A device, comprising: a radio antenna; an integrated circuit, comprising: a radio frequency amplifier coupled to the radio antenna and configured to deliver an amplified radio frequency signal to the radio antenna from a radio frequency signal received at an input of the radio frequency amplifier, the radio frequency amplifier comprising: a first amplifier stage; a second amplifier stage; and an impedance matching circuit comprising a first inductive line and a second inductive line coupled to each other through electromagnetic induction, the first inductive line coupled to an output of the first amplifier stage, and the second inductive line coupled to an input of the second amplifier stage.

25. The device of claim 24, wherein the second inductive line is dimensioned such that the second inductive line compensates for an input capacitive component of the second amplifier stage, and wherein the first inductive line is dimensioned such that the first inductive line allows meeting a real portion of a required load at the output of the first amplifier stage.

26. The device of claim 24, wherein the first inductive line and the second inductive line are disposed to maximize a coupling factor between the first inductive line and the second inductive line.

27. The device of claim 24, wherein the first inductive line comprises: a first terminal coupled to the first amplifier stage, the first terminal coupled to the first amplifier stage via an inductive element; and a second terminal coupled to a decoupling capacitive element.

28. The device of claim 24, wherein the first amplifier stage and the second amplifier stage are configured to obtain a ratio of less than 5 between a resistance at the input of the second amplifier stage and a resistance of a load desired at the output of the first amplifier stage.

29. The device of claim 24, wherein the first inductive line and the second inductive line are wound around a decoupling capacitive element coupled to the first inductive line or the second inductive line.

30. An integrated circuit, comprising: a radio frequency amplifier of a complementary metal-oxide semiconductor (CMOS) type, the radio frequency amplifier comprising: a driver stage; a power stage; and an impedance matching circuit comprising a first inductive line and a second inductive line coupled to each other through electromagnetic induction, the first inductive line coupled to an output of the driver stage, and the second inductive line coupled to an input of the power stage.

31. The integrated circuit of claim 30, wherein the second inductive line is dimensioned such that the second inductive line compensates for an input capacitive component of the power stage, and wherein the first inductive line is dimensioned such that the first inductive line allows meeting a real portion of a required load at the output of the driver stage.

32. The integrated circuit of claim 30, wherein the driver stage and the power stage are configured to obtain a ratio of less than 5 between a resistance at the input of the power stage and a resistance of a load desired at the output of the driver stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Other advantages and features of the invention will appear on examination of the detailed description of implementations and embodiments, which are in no way limiting, and of the appended drawings in which:

[0058] FIG. 1 is a block diagram of an impedance matching device;

[0059] FIG. 2 is a block diagram of an impedance matching device;

[0060] FIG. 3 is a block diagram of an impedance matching device;

[0061] FIG. 4 is a block diagram of an impedance matching device;

[0062] FIG. 5 is a block diagram of an impedance matching device;

[0063] FIG. 6 is a block diagram of an impedance matching device;

[0064] FIG. 7 is a block diagram of an embodiment integrated circuit;

[0065] FIG. 8 is a block diagram of an embodiment integrated circuit;

[0066] FIG. 9 is a top view of embodiment inductors L1 and L2 and other components; and

[0067] FIG. 10 is a block diagram of an embodiment integrated circuit.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0068] FIG. 7 represents an integrated circuit IC according to one embodiment of the invention.

[0069] The integrated circuit comprises a radio frequency amplifier AMP. The radio frequency amplifier AMP is configured to amplify the power of a radio frequency signal RFIN.

[0070] The radio frequency amplifier AMP is configured to be able to be connected to a radio antenna (not represented) so as to be able to deliver an amplified radio frequency signal RFOUT to this radio antenna.

[0071] Such a radio frequency amplifier can in particular be integrated into an object comprising a radio antenna, in particular so as to be able to be used within the framework of the Internet of Things.

[0072] The radio frequency amplifier comprises two amplifier stages DS, PS. Nevertheless, it is possible to provide a radio frequency amplifier comprising more than two amplifier stages. The radio frequency amplifier can, for example, comprise three amplifier stages.

[0073] In the embodiment represented in FIG. 1, the amplifier stage DS located most upstream is a driver stage and the subsequent amplifier stage PS is a power stage. Alternatively, the most upstream amplifier stage may be a pre-driver stage and the subsequent amplifier stage is a driver stage.

[0074] Each amplifier stage DS, PS is a CMOS amplifier.

[0075] Advantageously, the first amplifier stage DS (the driver stage) has an output impedance close to an input impedance of the second amplifier stage PS (the power stage).

[0076] In particular, the first amplifier stage DS and the second amplifier stage PS are configured so as to obtain a ratio between a resistance (Rp_psin in FIG. 1) seen at the input of the second stage and a resistance of the load (Rp_load_ds in FIG. 3) desired at the output of the first stage of less than 5.

[0077] The radio frequency amplifier AMP comprises an impedance matching device IMD between the two amplifier stages DS, PS.

[0078] The impedance matching device IMD is configured to provide a desired load at the output of the first amplifier stage DS (the driver stage) from the impedance at the input of the second amplifier stage PS (the power stage).

[0079] More particularly, the first amplifier stage DS, that is to say, the driver stage, has an input DSIN configured to receive the radio frequency signal RFIN. This first amplifier stage DS also has an output DSOUT connected to a main input I1 of the impedance matching device IMD.

[0080] The second amplifier stage PS, that is to say the power stage, has an input PSIN connected to a main output Gi of the impedance matching device IMD. This second amplifier stage PS also has an output PSOUT connected to the radio antenna, in particular via switching circuits and filters (not represented).

[0081] The impedance matching device IMD comprises two lines L1, L2 which are coupled by electromagnetic induction.

[0082] A first line L1 has a first terminal connected to the main input I1 of the impedance matching device IMD. As previously seen, this main input I1 of the impedance matching device is connected to the output DSOUT of the first amplifier stage DS.

[0083] The first line L1 also has a second terminal connected to an output O2 of the impedance matching device. This output O2 is connected to a decoupling capacitive element CD4. The decoupling capacitive element CD4 therefore has a first terminal connected to the second terminal of the first line L1 and a second terminal connected to ground GND.

[0084] A second line L2 has a first terminal connected to the main output O1 of the impedance matching device. As previously seen, this main output O1 of the impedance matching device IMD is connected to the input PSIN of the second amplifier stage PS. More particularly, the main output O1 of the impedance matching device IMD is connected to the input PSIN of the second amplifier stage PS via a capacitive element CAP4.

[0085] The capacitive element CAP4 prevents a bias VGPS of the first stage from leaking through the second coupled line L2.

[0086] The second line L2 also has a second terminal connected to an output O3 of the impedance matching device IMD. This output O3 is connected to ground GND.

[0087] The first line L1 and the second line L2 are disposed so as to be as close as possible so as to maximise a coupling factor between these two lines L1, L2.

[0088] The second line L2, which is connected to the second amplifier stage, is configured to compensate for the capacitance Cp_psin of the input impedance of the second stage DS (see FIG. 1). The width of the second line is selected so as to be large enough to comply with a current constraint (electromigration).

[0089] In particular, the inductance of the second line L2 is selected such that it is equal to L2=1/(Cp_psin ω.sup.2, where Cp_psin is the parallel capacitance seen at the input of the second stage PS and ω is the pulsation relative to a central operating frequency.

[0090] The first line L1, which is connected to the first amplifier stage DS, is configured to meet the resistance Rp_load_ds of the load required by the first amplifier stage DS.

[0091] In particular, when the coupling factor between the first line L1 and the second line L2 is close to 1, the inductance of the first line L1 is selected such that it is equal to L1=(L2×Rp_load_ds)/Rp_psin.

[0092] When the integrated circuit comprises several metal layers, the coupled lines L1, L2 are made with the thickest metal layer. Generally, the lines L1, L2 have a thickness of between 2 μm and 4 μm.

[0093] It may be preferred to make the coupled lines from two metal layers disposed at different heights in order to obtain two coupled lines one above the other. This allows increasing the coupling factor between the two lines.

[0094] The first line L1 which is connected to the first amplifier stage DS can also be configured to be used as a bias line for this first amplifier stage DS. In particular, a bias voltage VBAT_DS can be applied to the second terminal of the first line L1.

[0095] It is possible to do the same for the second amplifier stage PS. In this case, as represented in FIG. 8, the second terminal of the second line L2 is connected to ground via a capacitive decoupling element CD5.

[0096] A bias voltage VGPS is then applied to the second terminal of the second line L2. Furthermore, the first terminal of the second line L2 is directly connected to the second amplifier stage PS. The integrated circuit therefore does not comprise a capacitive element between the first terminal of the second line and the second stage.

[0097] As represented in FIG. 9, the second line L2 is wound around the first line L1 such that the two coupled lines are as close as possible to each other.

[0098] Furthermore, in order to optimise the space occupied by the coupled lines L1, L2, it is advantageous to wind the coupled lines around the decoupling capacitive element CD4.

[0099] The decoupling capacitive element CD4 then occupies a space in the centre of the two wound lines L1, L2. This space is required and is left unoccupied when the decoupling capacitor CD4 is placed next to the coupled lines. Alternatively, it is possible to wind the coupled lines around the decoupling capacitive element CD5.

[0100] Moreover, placing the decoupling capacitive element CD4 at the centre of the two wound lines L1, L2 allows reducing the power losses. In particular, by placing the decoupling capacitive element CD4 in the centre, the second terminal of the first line L1 can be directly connected to the decoupling capacitive element CD4 in the centre.

[0101] More particularly, when the decoupling capacitive element CD4 is not placed in the centre but next to the wound lines L1, L2, the first line passes again under the wound lines to be able to connect the second terminal thereof to the decoupling capacitive element. This can lead to power losses.

[0102] FIG. 10 illustrates a variant of the integrated circuit of FIG. 8. Herein, the integrated circuit differs from that of FIG. 8 in that it comprises an impedance matching device having a main input I1 connected to the output of the first DS amplifier stage via an inductive element Lmatch.

[0103] The inductive element Lmatch is used to make the matching device IMD resonate with the capacitor of the output impedance of the first stage.

[0104] Such an inductive element Lmatch can be used when the capacitance Cp_dsout seen at the output of the first stage can have a significant impact on the performances, in particular on the gain of the amplifier and on the power added efficiency. In particular, the greater the capacitance Cp_dsout or the greater the pulsation a), the greater the leakage of the signal at the output of the first stage towards ground.

[0105] In particular, the value of the inductance of the inductive element Lmatch can be determined according to the formula:

[00001]$\mathrm{Lmatch}=\frac{\mathrm{Rp\_load}{\mathrm{\_ds}}^2*\mathrm{Cp\_dsout}*\omega }{\left(1+{\left(\mathrm{Rp\_load}\mathrm{\_ds}*\mathrm{Cp\_dsout}*\omega \right)}^2\right)}$

where Rp_load_ds is the desired load of the first amplifier stage DS, Cp_dsout is the capacitance of the output impedance of the first amplifier stage DS, and ω is the pulsation relative to the operating frequency.

[0106] Furthermore, in this case the value of the inductance of the first line L1 is selected as being equal to L1=(L2×Rmatch)/Rp_psin,

[0107] R_psin being the resistance of the input impedance of the second stage, Rmatch

[00002]$\mathrm{Rmatch}=\frac{\mathrm{Rp\_load}\mathrm{\_ds}}{\left(1+{\left(\mathrm{Rp\_load}\mathrm{\_ds}*\mathrm{Cp\_dsout}*\omega \right)}^2\right)},$

being equal to where Rp_load_ds is the desired load of the first amplifier stage DS, Cp_dsout is the capacitance of the output impedance of the first stage, and ω is the pulsation relative to the operating frequency.

[0108] A bias voltage VBAT_DS can be applied to the second terminal of the first line L1 then acts as a choke.

[0109] The described impedance matching devices can be used between two single ended or differential type amplifier stages, or between a single ended type amplifier stage and a differential type amplifier stage.