Power factor correction circuit

Abstract

The present invention discloses a power factor correction circuit. The power factor correction circuit includes: a first bridge arm having a first switch and a second switch; a second bridge arm having a third switch and a fourth switch; a first inductor and a second inductor; a first capacitor and/or a second capacitor connected with a common point between the second inductor and the first inductor; and a third capacitor and/or a fourth capacitor, the third capacitor connected in parallel to the third switch based on an arrangement of the second capacitor and having a capacitance value same as that of the second capacitor, the fourth capacitor connected in parallel to the fourth switch based on an arrangement of the first capacitor and having a capacitance value same as that of the first capacitor.

Claims

1. A power factor correction circuit, comprising: a first AC terminal and a second AC terminal for receiving an AC voltage; a first DC terminal and a second DC terminal for providing a DC voltage; a first inductor; a first bridge arm comprising a first switch and a second switch connected in series, a first node between the first switch and the second switch electrically coupled to the first AC terminal through the first inductor; a second bridge arm comprising a third switch and a fourth switch connected in series, a second node between the third switch and the fourth switch electrically coupled to the second AC terminal, wherein the first bridge arm and the second bridge arm are connected in parallel between the first DC terminal and the second DC terminal; a second inductor having one terminal connected to the first AC terminal, and another terminal connected to the first inductor; a first capacitor and/or a second capacitor, the first capacitor having one end connected to a third node between the second inductor and the first inductor and another end connected to the first DC terminal, the second capacitor having one end connected to the third node between the second inductor and the first inductor and another end connected to the second DC terminal; and a third capacitor and/or a fourth capacitor, the third capacitor connected in parallel to the third switch based on an arrangement of the second capacitor and having a capacitance value same as that of the second capacitor, the fourth capacitor connected in parallel to the fourth switch based on an arrangement of the first capacitor and having a capacitance value same as that of the first capacitor.

2. The power factor correction circuit of claim 1, further comprising a first surge diode and a second surge diode connected in series, a cathode of the first surge diode connected to the first DC terminal, an anode of the second surge diode connected to the second DC terminal, and an anode of the first surge diode and a cathode of the second surge diode connected to the first AC terminal.

3. The power factor correction circuit of claim 1, further comprising a bus capacitor electrically connected between the first DC terminal and the second DC terminal.

4. The power factor correction circuit of claim 1, wherein each of the third switch and the fourth switch is a diode.

5. The power factor correction circuit of claim 1, wherein each of the first switch, the second switch, the third switch and the fourth switch is a semiconductor switching device including a MOSFET, a GaN device, or a SiC device.

6. A power factor correction circuit, comprising: a first AC terminal and a second AC terminal for receiving an AC voltage; a first DC terminal and a second DC terminal for providing a DC voltage; a first inductor; a first bridge arm comprising a first switch and a second switch connected in series, a first node between the first switch and the second switch electrically coupled to the first AC terminal through the first inductor; a second bridge arm comprising a third switch and a fourth switch connected in series, a second node between the third switch and the fourth switch electrically coupled to the second AC terminal, wherein the first bridge arm and the second bridge arm are connected in parallel between the first DC terminal and the second DC terminal; a second inductor having one terminal connected to the first AC terminal and another terminal connected to the first inductor; a first switching unit and a first capacitor connected in series, and electrically connected between the first DC terminal and a third node between the second inductor and the first inductor; and/or a second switching unit and a second capacitor connected in series, and electrically connected between the second DC terminal and the third node between the second inductor and the first inductor, wherein the first switching unit and/or the second switching unit are turned off under light-load or no-load.

7. The power factor correction circuit of claim 6, further comprising a bus capacitor electrically connected between the first DC terminal and the second DC terminal.

8. The power factor correction circuit of claim 6, further comprising a first surge diode and a second surge diode connected in series, a cathode of the first surge diode connected to the first DC terminal, an anode of the second surge diode connected to the second DC terminal, and an anode of the first surge diode and a cathode of the second surge diode connected to the first AC terminal.

9. The power factor correction circuit of claim 6, wherein each of the third switch and the fourth switch is a diode.

10. The power factor correction circuit of claim 6, wherein each of the first switch, the second switch, the third switch and the fourth switch is a semiconductor switching device including a MOSFET, a GaN device, or a SiC device.

11. A power factor correction circuit, comprising: a first AC terminal and a second AC terminal for receiving an AC voltage; a first DC terminal and a second DC terminal for supplying a DC voltage; a first inductor; a first bridge arm comprising a first switch and a second switch connected in series, a first node between the first switch and the second switch electrically coupled to the first AC terminal through the first inductor; a second bridge arm comprising a third switch and a fourth switch connected in series, a second node between the third switch and the fourth switch electrically coupled to the second AC terminal, wherein the first bridge arm and the second bridge arm are connected in parallel between the first DC terminal and the second DC terminal; a second inductor having a first terminal connected to a first terminal of the first inductor and connected to the first node between the first switch and the second switch, wherein the first inductor and the second inductor are coupled inductors, and the first terminal of the second inductor and the first terminal of the first inductor are terminals of same magnetic polarity; a first capacitor and/or a second capacitor, the first capacitor having one end connected to a second terminal of the second inductor and another end connected to the first DC terminal, the second capacitor having one end connected to the second terminal of the second inductor and another end connected to the second DC terminal; and a third capacitor and/or a fourth capacitor, the third capacitor connected in parallel to the third switch based on an arrangement of the second capacitor and having a capacitance value same as that of the second capacitor, the fourth capacitor connected in parallel to the fourth switch based on an arrangement of the first capacitor and having a capacitance value same as that of the first capacitor.

12. The power factor correction circuit of claim 11, further comprising a bus capacitor electrically connected between the first DC terminal and the second DC terminal.

13. The power factor correction circuit of claim 11, further comprising a first surge diode and a second surge diode connected in series, a cathode of the first surge diode connected to the first DC terminal, an anode of the second surge diode connected to the second DC terminal, and an anode of the first surge diode and a cathode of the second surge diode connected to the first AC terminal.

14. The power factor correction circuit of claim 11, wherein each of the third switch and the fourth switch is a diode.

15. The power factor correction circuit of claim 11, wherein each of the first switch, the second switch, the third switch and the fourth switch is a semiconductor switching device including a MOSFET, a GaN device, or a SiC device.

16. A power factor correction circuit, comprising: a first AC terminal and a second AC terminal for receiving an AC voltage; a first DC terminal and a second DC terminal for providing a DC voltage; a first inductor; a first bridge arm comprising a first switch and a second switch connected in series, a first node between the first switch and the second switch electrically coupled to the first AC terminal through the first inductor; a second bridge arm comprising a third switch and a fourth switch connected in series, a second node between the third switch and the fourth switch electrically coupled to the second AC terminal, wherein the first bridge arm and the second bridge arm are connected in parallel between the first DC terminal and the second DC terminal; a second inductor having a first terminal connected to a first terminal of the first inductor and connected to the first node between the first switch and the second switch, wherein the first inductor and the second inductor are coupled inductors, and the first terminal of the second inductor and the first terminal of the first inductor are terminals of same magnetic polarity; a first switching unit and a first capacitor connected in series, and electrically connected between a second terminal of the second inductor and the first DC terminal; and/or a second switching unit and a second capacitor connected in series, and electrically connected between the second terminal of the second inductor and the second DC terminal, wherein the first switching unit and/or the second switching unit are turned off under light-load or no-load.

17. The power factor correction circuit of claim 16, further comprising a bus capacitor electrically connected between the first DC terminal and the second DC terminal.

18. The power factor correction circuit of claim 16, further comprising a first surge diode and a second surge diode connected in series, a cathode of the first surge diode connected to the first DC terminal, an anode of the second surge diode connected to the second DC terminal, and an anode of the first surge diode and a cathode of the second surge diode connected to the first AC terminal.

19. The power factor correction circuit of claim 16, wherein each of the third switch and the fourth switch is a diode.

20. The power factor correction circuit of claim 16, wherein each of the first switch, the second switch, the third switch and the fourth switch is a semiconductor switching device including a MOSFET, a GaN device, or a SiC device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The exemplary embodiments will be described in detail with reference to the accompanying drawings, through which the above and other features and advantages of the present invention will become more apparent.

(2) FIG. 1 is a schematic diagram of a circuit structure of a power factor correction circuit according to a first embodiment of the present invention.

(3) FIG. 2 is a schematic diagram of a circuit structure of a power factor correction circuit according to a second embodiment of the present invention.

(4) FIG. 3 is a schematic diagram of a circuit structure of a power factor correction circuit according to a third embodiment of the present invention.

(5) FIG. 4 is a schematic diagram of a circuit structure of a power factor correction circuit according to a fourth embodiment of the present invention.

(6) FIG. 5 is a schematic diagram of a circuit structure of a power factor correction circuit according to a fifth embodiment of the present invention.

(7) FIG. 6 is a schematic diagram of a circuit structure of a power factor correction circuit according to a sixth embodiment of the present invention.

(8) FIG. 7 is a schematic diagram of a circuit structure of a power factor correction circuit according to a seventh embodiment of the present invention.

(9) FIG. 8 is a schematic diagram of a circuit structure of a power factor correction circuit according to an eighth embodiment of the present invention.

(10) FIG. 9 is a schematic diagram of a circuit structure of a power factor correction circuit according to a ninth embodiment of the present invention.

(11) FIG. 10 is a schematic diagram of a circuit structure of a power factor correction circuit according to a tenth embodiment of the present invention.

(12) FIG. 11 is a schematic diagram of a circuit structure of a power factor correction circuit according to an eleventh embodiment of the present invention.

(13) FIG. 12 is a schematic diagram of a circuit structure of a power factor correction circuit according to a twelfth embodiment of the present invention.

(14) FIG. 13A is a schematic diagram of a voltage waveform of a bus capacitor of a power factor correction circuit according to the prior art.

(15) FIG. 13B is a schematic diagram of a voltage waveform of a bus capacitor of a power factor correction circuit according to the present invention.

DETAILED EMBODIMENTS OF THE INVENTION

(16) The exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and shall not be understood as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the invention will be thorough and complete, and the conception of exemplary embodiments will be fully conveyed to those skilled in the art. In the drawings, the same reference sign denotes the same or similar structure, so the detailed explanation will be omitted.

(17) When element/component/and the like described and/or illustrated here are introduced, the phrases “one”, “a(an)”, “the”, “said” and “at least one” refer to one or more elements/components/and the like. The terms “include”, “comprise” and “have” refer to an open meaning without excluding additional element/component/and the like except for the listed element s/components/and the like. The relative phrases, such as, “upper” or “lower” used here may describe a relative relation of one component with respect to another component. It shall be understood that if the device illustrated in the drawing reverses to turn upside down, the component on an “upper” side will become a component on a “lower” side. In addition, the terms “first”, “second” and the like in the claims are not numeral limitations to object.

(18) FIG. 1 illustrates a circuit structure of a power factor correction circuit according to a first embodiment of the present invention. The power factor correction circuit includes a first AC terminal AC.sub.1 and a second AC terminal AC.sub.2 for receiving an AC voltage, and a first DC terminal DC.sub.1 and a second DC terminal DC.sub.2 for providing a DC voltage. The power factor correction circuit further includes a first bridge arm, a second bridge arm, a first inductor L.sub.1 and a second inductor L.sub.2. The first bridge arm includes a first switch S.sub.1 and a second switch S.sub.2 connected in series. A first node N.sub.1 between the first switch S.sub.1 and the second switch S.sub.2 is electrically coupled to the first AC terminal AC.sub.1 through the first inductor L.sub.1 and the second inductor L.sub.2. The second bridge arm includes a third switch S.sub.3 and a fourth switch S.sub.4 connected in series. A second node N.sub.2 between the third switch S.sub.3 and the fourth switch S.sub.4 is electrically coupled to the second AC terminal AC.sub.2. The first bridge arm and the second bridge arm are connected in parallel between the first DC terminal DC.sub.1 and the second DC terminal DC.sub.2. The second inductor L.sub.2 has two terminals, one terminal connected to the first AC terminal AC.sub.1 and another terminal connected to the first inductor L.sub.1.

(19) The power factor correction circuit further includes a first capacitor C.sub.1 and a second capacitor C.sub.2. The first capacitor C.sub.1 has one end connected to a third node N.sub.3 between the second inductor L.sub.2 and the first inductor L.sub.1, and another end connected to the first DC terminal DC.sub.1. The second capacitor C.sub.2 has one end connected to the third node N.sub.3 between the second inductor L.sub.2 and the first inductor L.sub.1, and another end connected to the second DC terminal DC.sub.2.

(20) The power factor correction circuit further includes a third capacitor C.sub.3 and a fourth capacitor C.sub.4. The third capacitor C.sub.3 is connected in parallel to the third switch S.sub.3 based on an arrangement of the second capacitor C.sub.2, and has a capacitance value same as that of the second capacitor C.sub.2. The fourth capacitor C.sub.4 is connected in parallel to the fourth switch S.sub.4 based on an arrangement of the first capacitor C.sub.1, and has a capacitance value same as that of the first capacitor C.sub.1.

(21) In the present invention, the power factor correction circuit may further include a first surge diode D.sub.1 and a second surge diode D.sub.2 connected in series. A cathode of the first surge diode D.sub.1 is connected to the first DC terminal DC.sub.1, an anode of the second surge diode D.sub.2 is connected to the second DC terminal DC.sub.2, and an anode of the first surge diode D.sub.1 and a cathode of the second surge diode D.sub.2 are connected to the first AC terminal AC.sub.1.

(22) In the present invention, the power factor correction circuit may further include a bus capacitor C.sub.bus electrically connected between the first DC terminal DC.sub.1 and the second DC terminal DC.sub.2.

(23) In the embodiment of FIG. 1, the third switch S.sub.3 and the fourth switch S.sub.4, may be, for example, diodes. In other embodiment, the first switch S.sub.1, the second switch S.sub.z, the third switch S.sub.3 and the fourth switch S.sub.4 may be semiconductor switching devices, for example, including but not limited to MOSFETs, GaN devices, or SiC devices.

(24) FIG. 2 illustrates a circuit structure of a power factor correction circuit according to a second embodiment of the present invention, which differs from the embodiment of FIG. 1 in that the power factor correction circuit only includes the second capacitor C.sub.2 and the third capacitor C.sub.3 corresponding to the second capacitor C.sub.2. The second capacitor C.sub.2 has one end connected to the third node N.sub.3 between the second inductor L.sub.2 and the first inductor L.sub.1, and another end connected to the second DC terminal DC.sub.2. The third capacitor C.sub.3 is connected in parallel to the third switch S.sub.3 based on the arrangement of the second capacitor C.sub.2, and has a capacitance value same as that of the second capacitor C.sub.2.

(25) FIG. 3 illustrates a circuit structure of a power factor correction circuit according to a third embodiment of the present invention, which differs from the embodiment of FIG. 1 in that the power factor correction circuit only includes the first capacitor C.sub.1 and the fourth capacitor C.sub.4 corresponding to the first capacitor C.sub.1. The first capacitor C.sub.1 has one end connected to the third node N.sub.3 between the second inductor L.sub.2 and the first inductor L.sub.1, and another end connected to the first DC terminal DC.sub.1. The fourth capacitor C.sub.4 is connected in parallel to the fourth switch S.sub.4 based on the arrangement of the first capacitor C.sub.1, and has a capacitance value same as that the first capacitor C.sub.1.

(26) FIG. 4 illustrates a circuit structure of a power factor correction circuit according to a fourth embodiment of the present invention, which differs from the embodiment of FIG. 1 in that the third capacitor C.sub.3 and the fourth capacitor C.sub.4 are omitted while the switching units connected in series to the first and second capacitors and turned off under no-load or light-load are provided. More specifically, the power factor correction circuit includes a first switching unit SW.sub.1 and a first capacitor C.sub.1 connected in series, and a second switching unit SW.sub.2 and a second capacitor C.sub.2 connected in series. The first switching unit SW.sub.1 and the first capacitor C.sub.1 are electrically connected between the first DC terminal DC.sub.1 and the third node N.sub.3 between the second inductor L.sub.2 and the first inductor L.sub.1. The second switching unit SW.sub.2 and the second capacitor C.sub.2 are electrically connected between the second DC terminal DC.sub.2 and the third node N.sub.3 between the second inductor L.sub.2 and the first inductor L.sub.1. The first switching unit SW.sub.1 and the second switching unit SW.sub.2 are turned off under light-load or no-load.

(27) FIG. 5 illustrates a circuit structure of a power factor correction circuit according to a fifth embodiment of the present invention, which differs from the embodiment of FIG. 4 in that the power factor correction circuit only includes the second switching unit SW.sub.2 and the second capacitor C.sub.2 connected in series. The second switching unit SW.sub.2 and the second capacitor C.sub.2 are electrically connected between the second DC terminal DC.sub.2 and the third node N.sub.3 between the second inductor L.sub.2 and the first inductor L.sub.1. The second switching unit SW.sub.2 is turned off under light-load or no-load.

(28) FIG. 6 illustrates a circuit structure of a power factor correction circuit according to a sixth embodiment of the present invention, which differs from the embodiment of FIG. 4 in that the power factor correction circuit only includes the first switching unit SW.sub.1 and the first capacitor C.sub.1 connected in series. The first switching unit SW.sub.1 and the first capacitor C.sub.1 are electrically connected between the first DC terminal DC.sub.1 and the third node N.sub.3 between the second inductor L.sub.2 and the first inductor L.sub.1. The first switching unit SW.sub.1 is turned off under light-load or no-load.

(29) In some embodiments, the first switching unit and the second switching unit may include one or more switches.

(30) In some embodiments, a load less than 50% of a rated load may be considered as the light-load, but the present application is not limited thereto. In some embodiments, light-load may refer to a load less than 30%, 20% or 5% of the rated load.

(31) FIG. 7 illustrates a circuit structure of a power factor correction circuit according to a seventh embodiment of the present invention, which differs from the embodiment of FIG. 1 in that the first node N.sub.1 between the first switch S.sub.1 and the second switch S.sub.2 of the first bridge arm of the power factor correction circuit is electrically connected to the first AC terminal AC.sub.1 through the first inductor L.sub.1, i.e., the first inductor L.sub.1 has a first terminal connected to the first node N.sub.1 and a second terminal connected to the first AC terminal AC.sub.1; a first terminal of the second inductor L.sub.2 is connected to the first terminal of the first inductor L.sub.1, and connected to the first node N.sub.1 between the first switch S.sub.1 and the second switch S.sub.2; the first capacitor C.sub.1 has one end connected to a second terminal N.sub.4 of the second inductor L.sub.2 and another end connected to the first DC terminal DC.sub.1; and the second capacitor C.sub.2 has one end connected to the second terminal N.sub.4 of the second inductor L.sub.2 and another end connected to the second DC terminal DC.sub.2. In the embodiment of FIG. 7, the power factor correction circuit further includes a third capacitor C.sub.3 and a fourth capacitor C.sub.4. The third capacitor C.sub.3 is connected in parallel to the third switch S.sub.3 based on an arrangement of the second capacitor C.sub.2, and has a capacitance value same as that of the second capacitor C.sub.2. The fourth capacitor C.sub.4 is connected in parallel to the fourth switch S.sub.4 based on an arrangement of the first capacitor C.sub.1, and has a capacitance value same as that of the first capacitor C.sub.1. The first inductor L.sub.1 and the second inductor L.sub.2 are coupled inductors, and the first terminal of the first inductor L.sub.1 and the first terminal of the second inductor L.sub.2 are terminals of same magnetic polarity.

(32) FIG. 8 illustrates a circuit structure of a power factor correction circuit according to an eighth embodiment of the present invention, which differs from the embodiment of FIG. 7 in that the power factor correction circuit only includes the second capacitor C.sub.2 and the third capacitor C.sub.3 corresponding to the second capacitor C.sub.2. The second capacitor C.sub.2 has one end connected to the second terminal N.sub.4 of the second inductor L.sub.2, and another end connected to the second DC terminal DC.sub.2. The third capacitor C.sub.3 is connected in parallel to the third switch S.sub.3 based on the arrangement of the second capacitor C.sub.2, and has a capacitance value same as that of the second capacitor C.sub.2.

(33) FIG. 9 illustrates a circuit structure of a power factor correction circuit according to a ninth embodiment of the present invention, which differs from the embodiment of FIG. 7 in that the power factor correction circuit only includes the first capacitor C.sub.1 and the fourth capacitor C.sub.4 corresponding to the first capacitor C.sub.1. The first capacitor C.sub.1 has one end connected to the second terminal N.sub.4 of the second inductor L.sub.2, and another end connected to the first DC terminal DC.sub.1. The fourth capacitor C.sub.4 is connected in parallel to the fourth switch S.sub.4 based on the arrangement of the first capacitor C.sub.1, and has a capacitance value same as that of the first capacitor C.sub.1.

(34) FIG. 10 illustrates a circuit structure of a power factor correction circuit according to a tenth embodiment of the present invention, which differs from the embodiment of FIG. 7 in that the third capacitor C.sub.3 and the fourth capacitor C.sub.4 are omitted while the switching units connected in series to the first and second capacitors and turned off under no-load or light-load are provided. More specifically, the power factor correction circuit includes a first switching unit SW.sub.1 and a first capacitor C.sub.1 connected in series, and a second switching unit SW.sub.2 and a second capacitor C.sub.2 connected in series. The first switching unit SW.sub.1 and the first capacitor C.sub.1 are electrically connected between the second terminal N.sub.4 of the second inductor L.sub.2 and the first DC terminal DC.sub.1. The second switching unit SW.sub.2 and the second capacitor C.sub.2 are electrically connected between the second terminal N.sub.4 of the second inductor L.sub.2 and the second DC terminal DC.sub.2. The first switching unit SW.sub.1 and the second switching unit SW.sub.2 are turned off under light-load or no-load.

(35) FIG. 11 illustrates a circuit structure of a power factor correction circuit according to an eleventh embodiment of the present invention, which differs from the embodiment of FIG. 10 in that the power factor correction circuit only includes the second switching unit SW.sub.2 and the second capacitor C.sub.2 connected in series. The second switching unit SW.sub.2 and the second capacitor C.sub.2 are electrically connected between the second terminal N.sub.4 of the second inductor L.sub.2 and the second DC terminal DC.sub.2. The second switching unit SW.sub.2 is turned off under light-load or no-load.

(36) FIG. 12 illustrates a circuit structure of a power factor correction circuit according to a twelfth embodiment of the present invention, which differs from the embodiment of FIG. 10 in that the power factor correction circuit only includes the first switching unit SW.sub.1 and the first capacitor C.sub.1 connected in series. The first switching unit SW.sub.1 and the first capacitor C.sub.1 are electrically connected between the second terminal N.sub.4 of the second inductor L.sub.2 and the first DC terminal DC.sub.1. The first switching unit SW.sub.1 is turned off under light-load or no-load.

(37) In some embodiments, the first switching unit and the second switching unit may include one or more switches.

(38) Similarly, a load less than 50% of a rated load may be considered as the light-load, but the present application is not limited thereto. In some embodiments, the light-load may refer to a load less than 30%, 20% or 5% of the rated load. In the above embodiments, the third switch S.sub.3 and the fourth switch S.sub.4 may be, for example, diodes. In other embodiment, the first switch S.sub.1, the second switch S.sub.2, the third switch S.sub.3 and the fourth switch S.sub.4 may be semiconductor switching devices, for example, including but not limited to MOSFETs, GaN devices, or SiC devices.

(39) FIG. 13A is a schematic diagram of a voltage waveform of bus capacitor of a power factor correction circuit according to the prior art, and FIG. 13B is a schematic diagram of a voltage waveform of bus capacitor of a power factor correction circuit according to the present invention. As shown in FIGS. 13A and 13B, when the circuit is under no-load or light-load, a voltage V.sub.bus of the bus capacitor C.sub.bus of the prior art increases, but a voltage V.sub.bus of the bus capacitor C.sub.bus of the present invention does not increase, such that the bus capacitor can be effectively protected. The power factor correction circuit of the present invention can effectively prevent the voltage of the bus capacitor from increasing abnormally when the circuit is under no-load or light-load by keeping the capacitors of the diagonal position of the rectifier bridge to have the same capacitance value, or by connecting the switching unit in series to the capacitor and turning off the switching unit under no-load or light-load.

(40) The present invention is applicable to the Totem-Pole PFC circuit, and facilitates to reduce a volume of the filter circuit while preventing a sharp increase of the output voltage of the bus capacitor under no-load or light-load.

(41) Exemplary embodiments of the present invention have been shown and described above. It shall be understood that the present invention is not limited to the disclosed embodiments. Instead, the present invention intends to cover various modifications and equivalents included in the spirit and scope of the appended claims.