SOLID STATE CIRCUIT BREAKER AND MOTOR DRIVING SYSTEM

Abstract

A solid state circuit breaker, including a solid state switch, an inductor connected with the solid state switch in series and a fault detection circuit. The solid state switch has a gate electrode, a source electrode and a drain electrode. The fault detection circuit is used for detecting health status of the solid state switch and identifying fault type of the solid state switch in a condition that a fault occurs on the solid state switch based on one or more of a measured voltage between the source electrode and the drain electrode of the solid state switch, a measured voltage of two terminals of the inductor, a reference voltage and a switching control signal provided to the gate electrode of the solid state switch. A motor driving system having the solid state circuit breaker is further disclosed.

Claims

1. A solid state circuit breaker comprising: a solid state switch having a gate electrode, a source electrode and a drain electrode; an inductor connected with the solid state switch in series; and a fault detection circuit for detecting health status of the solid state switch and identifying fault type of the solid state switch in a condition that a fault occurs on the solid state switch based on one or more of a measured voltage between the source electrode and the drain electrode of the solid state switch, a measured voltage of two terminals of the inductor, a reference voltage and a switching control signal provided to the gate electrode of the solid state switch.

2. The solid state circuit breaker of claim 1, wherein the fault detection circuit comprises a field programmable gate array for outputting a string of codes, and the fault detection circuit detects health status and fault type of the solid state switch according to the string of codes.

3. The solid state circuit breaker of claim 1, wherein the fault detection circuit detects whether over-heat occurs on the solid state switch based on the measured voltage between the source electrode and the drain electrode of the solid state switch, the switching control signal and a curve of a resistance between the source electrode and the drain electrode of the solid state switch versus a temperature of the solid state switch.

4. The solid state circuit breaker of claim 3, wherein the fault detection circuit detects that over-heat occurs on the solid state switch when the measured voltage between the source electrode and the drain electrode of the solid state switch is greater than a predetermined voltage threshold in a condition that the switching control signal is a high level.

5. The solid state circuit breaker of claim 1, wherein the fault detection circuit detects whether short circuit occurs on the solid state switch based on the measured voltage between the source electrode and the drain electrode of the solid state switch and the switching control signal.

6. The solid state circuit breaker of claim 5, wherein the fault detection circuit detects that short circuit occurs on the solid state switch when the measured voltage between the source electrode and the drain electrode of the solid state switch is zero in a condition that the switching control signal is a low level.

7. The solid state circuit breaker of claim 1, wherein the fault detection circuit detects whether open circuit occurs on the solid state switch based on the measured voltage of two terminals of the inductor, the reference voltage and the switching control signal.

8. The solid state circuit breaker of claim 7, wherein the fault detection circuit comprises: a comparator for comparing the measured voltage of two terminals of the inductor with the reference voltage to output a comparison result, and the fault detection circuit detects occurrence of open circuit on the solid state switch based on the comparison result and the switching control signal.

9. The solid state circuit breaker of claim 8, wherein the fault detection circuit comprises: a logic gate circuit; a first RS trigger connected with the comparator via the logic gate circuit; and a second RS trigger connected with the switching control signal via the logic gate circuit.

10. The solid state circuit breaker of claim 9, wherein a reset terminal of the first RS trigger is connected with the logic gate circuit and a set terminal thereof is connected with the switching control signal; a reset terminal of the second RS trigger is connected with the logic gate circuit and a set terminal thereof is connected with a reverse signal of the switching control signal; the fault detection circuit detects whether open circuit occurs on the solid state switch according to logic levels of an output terminal of the first RS trigger and an output terminal of the second RS trigger.

11. The solid state circuit breaker of claim 10, wherein the logic gate circuit comprises: a first NOT gate having an input terminal connected with the switching control signal; a first NAND gate having a first input terminal connected with an output terminal of the comparator and a second input terminal connected with the switching control signal; a second NAND gate having a first input terminal connected with the output terminal of the comparator and a second input terminal connected with an output terminal of the first NOT gate; a second NOT gate having an input terminal connected with the output terminal of the second RS trigger; a third NOT gate having an input terminal connected with the output terminal of the first RS trigger; a first OR gate having a first input terminal connected with an output terminal of the first NAND gate, a second input terminal connected with an output terminal of the second NOT gate, and an output terminal connected with the reset terminal of the first RS trigger; and a second OR gate having a first input terminal connected with an output terminal of the third NOT gate, a second input terminal connected with an output terminal of the second NAND gate, and an output terminal connected with the reset terminal of the second RS trigger.

12. The solid state circuit breaker of claim 7, wherein the fault detection circuit further comprises: a delay circuit for delaying the switching control signal to obtain a delayed switching control signal, wherein the fault detection circuit detects the solid state switch based on the measured voltage of two terminals of the inductor, the reference voltage and the delayed switching control signal.

13. The solid state circuit breaker of claim 12, wherein the delay circuit comprises: a first branch and a second branch connected in parallel, wherein the first branch comprises a first diode and a first resistor connected in series, the second branch comprises a second diode and a second resistor connected reversely and in series; and a capacitor connected with the first and the second branches.

14. A motor driving system comprising: an electrical motor; a power source for providing a DC voltage; a DC bus capacitor connected with the power source in parallel; a DC/AC converter for converting the DC voltage to an AC voltage and providing the AC voltage to the electrical motor; and a solid state circuit breaker comprising: a solid state switch having a gate electrode, a source electrode and a drain electrode; an inductor connected with the solid state switch in series; and a fault detection circuit for detecting health status of the solid state switch and identifying fault type of the solid state switch in a condition that a fault occurs on the solid state switch based on one or more of a measured voltage between the source electrode and the drain electrode of the solid state switch, a measured voltage of two terminals of the inductor, a reference voltage and a switching control signal provided to the gate electrode of the solid state switch.

15. The motor driving system of claim 14, wherein the fault detection circuit comprises a field programmable gate array for outputting a string of codes, and the fault detection circuit detects whether over-heat, short circuit or open circuit occurs on the solid state switch according to the string of codes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present invention can be understood better in light of the following detailed description with reference to the accompanying drawings, in which the same reference signs represent the same components in the whole drawings, in which:

[0009] FIG. 1 is a schematic diagram of a motor driving system having a solid state circuit breaker with a function of fault self-diagnosing according to an embodiment of the present invention;

[0010] FIG. 2 is a schematic diagram of a fault detection circuit in the solid state circuit breaker as shown in FIG. 1;

[0011] FIG. 3 is a graph showing a curve of a resistance between a source electrode and a drain electrode of a solid state switch versus a temperature of the solid state switch in the solid state circuit breaker as shown in FIG. 1;

[0012] FIG. 4 is a schematic diagram of a fault detection circuit for detecting a fault of open circuit of an embodiment of the present invention;

[0013] FIG. 5 is a waveform graph of the fault detection circuit as shown in FIG. 4 in a condition that the solid state circuit breaker is normal; and

[0014] FIG. 6 is a waveform graph of the fault detection circuit as shown in FIG. 4 in a condition that open circuit occurs on the solid state circuit breaker.

DETAILED DESCRIPTION OF THE INVENTION

[0015] In order to help the person skilled in the art to exactly understand the subject matters claimed by embodiments of the present invention, detailed description for embodiments of the present invention will be given with reference to the accompanying drawings in the following. In the following detailed description for those embodiments, some known functions or structures will not be described in details by the Description, to avoid disclosure of the present invention to be affected by unnecessary details.

[0016] Unless defined otherwise, the technical or scientific terms used in the Claims and the Description should have meanings as commonly understood by one of ordinary skilled in the art to which the present disclosure belongs. The terms first, second and the like in the present Description and Claims do not mean any sequential order, quantity or importance, but are only used for distinguishing different components. The terms a, an and the like do not denote a limitation of quantity, but denote the existence of at least one. The terms comprises, comprising, includes, including or has, have, having and the like mean that the element or object in front of the comprises, comprising, includes, including, has, have and having covers the elements or objects and their equivalents illustrated following the comprises, comprising, includes, including, has, have and having, without excluding other elements or objects. The terms coupled, connected and the like are not limited to being connected physically or mechanically, but may comprise electric connection, no matter directly or indirectly.

[0017] FIG. 1 shows a schematic diagram of a schematic motor driving system 200 according to an embodiment of the present invention. As shown in FIG. 1, the schematic motor driving system 200 comprises an electrical motor 102, a power source 104 for providing a DC voltage, a DC bus capacitor C connected with the power source 104 in parallel, a DC/AC converter 106 connected between the DC bus capacitor C and the electrical motor 102, and a solid state circuit breaker 100 connected between the power source 104 and the DC/AC converter 106. The DC/AC converter 106 may convert a DC voltage to an AC voltage, and provides the AC voltage to the electrical motor 102.

[0018] In embodiments of the present invention the solid state circuit breaker 100 has a function of fault self-diagnosing, and comprises a solid state switch SW, an inductor L connected with the solid state switch SW in series, a fly-wheel diode D.sub.i and a fault detection circuit 1. The solid state switch SW may, for example, comprise a metal-oxide-semiconductor field effect transistor (MOSFET). The solid state switch SW may also comprise an insulated gate bipolar transistor (IGBT) or an integrated gate commutated thyristor (IGCT). The solid state switch SW has a gate electrode g, a source electrode s and a drain electrode d.

[0019] The solid state circuit breaker 100 may also include a gate driving circuit 2, a first voltage measurement device 31 and a second voltage measurement device 32. The gate driving circuit 2 is used to supply a switching control signal S.sub.g to the gate electrode g of the solid state switch SW. The first voltage measurement device 31 is used to measure a voltage V.sub.1 between the source electrode s and the drain electrode d of the solid state switch SW. The second voltage measurement device 32 is used to measure a voltage V.sub.m of two terminals of the inductor L.

[0020] As shown in FIG. 2, the fault detection circuit 1 may receive a reference voltage V.sub.r that may be a little greater than a threshold voltage between the source electrode s and the drain electrode d of the solid state switch SW. The fault detection circuit 1 may detect health status of the solid state switch SW and identify fault type of the solid state switch SW in the condition that a fault occurs on the solid state switch SW based on one or more of the measured voltage V1 between the source electrode s and the drain electrode d of the solid state switch SW, the measured voltage V.sub.m of two terminals of the inductor, the reference voltage V.sub.r and the switching control signal S.sub.g provided to the gate electrode g of the solid state switch SW. In embodiments of the present invention the fault detection circuit 1 may be implemented in software, hardware or combination thereof.

[0021] Continuing to refer to FIG. 2, as an example, the fault detection circuit 1 may comprise a field programmable gate array (FPGA) 10 for outputting a string of codes CH. The fault detection circuit 1 may detect health status and fault type of the solid state switch SW according to the string of codes CH. In embodiments of the present invention, the fault detection circuit 1 may detect whether a fault such as over-heat, short circuit or open circuit occurs on the solid state switch SW according to the string of codes CH. For example, the string of codes CH may be an eight-bit code. In one embodiment, the first bit of the code CH may be used to represent health status of the solid state switch SW, and the last four bits, i.e., fifth to eighth bits, of the code CH may be used to present fault type of the solid state switch SW. And the middle second to fourth bits of the code CH are spare bits, which may be used to indicate other features of the solid state switch SW and may be defined according to the user's need. For instance, when the first bit of the code CH is 0, it indicates that the solid state switch SW is in a normal status; and when the first bit is 1, it indicates that a fault occurs on the solid state switch SW. The fifth bit of the code CH may represent whether a fault of over-heat occurs on the solid state switch SW. For example, when the fifth bit is 0, it indicates that no fault of over-heat occurs on the solid state switch SW; and when the fifth bit is 1, it indicates that a fault of over-heat occurs on the solid state switch SW. The sixth bit of the code CH may represent whether a fault of short circuit occurs on the solid state switch SW. For example, when the sixth bit is 0, it indicates that no fault of short circuit occurs on the solid state switch SW; and when the sixth bit is 1, it indicates that a fault of short circuit occurs on the solid state switch SW. The seventh and eighth bits of the code CH may represent whether a fault of open circuit occurs on the solid state switch SW. For example, when the seventh and eighth bits are both 1, it indicates that no fault of open circuit occurs on the solid state switch SW; and when the seventh bit is 0 and the eighth bit is 1, it indicates that a fault of open circuit occurs on the solid state switch SW. The bit numbers of the code CH and their representing meanings, and the meanings of the high and low logic levels of the respective bit as mentioned above are set merely for explaining the code of embodiments of the present invention, rather than restricting embodiments of the present invention, which may be defined according to requirements of different users.

[0022] In embodiments of the present invention, the solid state circuit breaker 100 may detect whether a fault of over-heat occurs on the solid state switch SW. Hereinafter, with combined reference to FIG. 1 and FIG. 3, it will be described in details how the solid state circuit breaker 100 detects whether a fault of over-heat occurs thereon by the fault detection circuit 1. FIG. 3 shows a graph of a curve of a resistance R.sub.ds between the source electrode s and the drain electrode d of the solid state switch SW versus a temperature T of the solid state switch SW (referred to as R.sub.ds-T curve). It can be seen from FIG. 3 that the resistance R.sub.ds between the source electrode s and the drain electrode d of the solid state switch SW will increase as the temperature T of the solid state switch SW increases. And it is known that in the condition that the solid state switch SW is closed, the relationship between the voltage V.sub.1 between the source electrode s and the drain electrode d of the solid state switch SW and the resistance R.sub.ds between the source electrode s and the drain electrode d of the solid state switch SW is as follows:

V.sub.1=R.sub.dsI.sub.1(1)

[0023] wherein I.sub.1 represents the current flowing through the source electrode s and the drain electrode d of the solid state switch SW. In the condition that the driving current required by the electrical motor 102 is constant, I.sub.1 is constant.

[0024] Therefore, from the R.sub.ds-T curve of FIG. 3 and the above Equation (1), it can be concluded that the voltage V.sub.1 between the source electrode s and the drain electrode d of the solid state switch SW is in positive proportion to the temperature T of the solid state switch SW.

[0025] In embodiments of the present invention the fault detection circuit 1 may detect whether over-heat occurs on the solid state switch SW based on the measured voltage V.sub.1 between the source electrode s and the drain electrode d of the solid state switch SW, the switching control signal S.sub.g and the curve of the resistance R.sub.ds between the source electrode s and the drain electrode d of the solid state switch SW versus the temperature T of the solid state switch SW. In the condition that the switching control signal S.sub.g provided to the gate electrode g of the solid state switch SW is a high level, when the measured voltage V.sub.1 between the source electrode s and the drain electrode d of the solid state switch SW is greater than a predetermined voltage threshold, the first bit of the code CH is output as 1, and the fifth bit of the code CH is also output as 1. Therefore, at this moment, the fault detection circuit 1 may detect that a fault of over-heat occurs on the solid state switch SW.

[0026] In embodiments of the present invention, the solid state circuit breaker 100 may detect whether a fault of short circuit occurs on the solid state switch SW. The fault detection circuit 1 may detect whether short circuit occurs on the solid state switch SW based on the measured voltage V.sub.1 between the source electrode s and the drain electrode d of the solid state switch SW and the switching control signal S.sub.g. In the condition that the switching control signal S.sub.g is a low level, when the measured voltage V.sub.1 between the source electrode s and the drain electrode d of the solid state switch SW is zero, the first bit of the code CH is output as 1, and the sixth bit of the code CH is also output as 1. Therefore, at this moment, the fault detection circuit 1 may detect that a fault of short circuit occurs on the solid state switch SW.

[0027] In embodiments of the present invention, the solid state circuit breaker 100 may detect whether a fault of open circuit occurs on the solid state switch SW. Hereinafter, with reference to FIG. 1 in combination with FIG. 4 to FIG. 6, it will be described in details how the solid state circuit breaker 100 detects whether a fault of open circuit occurs thereon by the fault detection circuit 1. The fault detection circuit 1 detects whether open circuit occurs on the solid state switch SW based on the measured voltage V.sub.m of two terminals of the inductor L, the reference voltage V.sub.r and the switching control signal S.sub.g. FIG. 4 shows a schematic diagram of the fault detection circuit 1 according to embodiments of the present invention. As shown in FIG. 4, the fault detection circuit 1 may comprise a comparator 4, whose positive terminal (+) receives the measured voltage V.sub.m of two terminals of the inductor L, and whose negative terminal () receives the reference voltage V.sub.r. The comparator 4 may compare the measured voltage V.sub.m of two terminals of the inductor L with the reference voltage V.sub.r to output a comparison result S.sub.m. The fault detection circuit 1 detects occurrence of open circuit on the solid state switch SW based on the comparison result S.sub.m output by the comparator 4 and the switching control signal S.sub.g.

[0028] The fault detection circuit 1 may further comprise a logic gate circuit 5, a first RS trigger 61 and a second RS trigger 62. The first RS trigger 61 may be connected with the comparator 4 via the logic gate circuit 5, and the second RS trigger 62 may be connected with the switching control signal S.sub.g via the logic gate circuit 5. A reset terminal R of the first RS trigger 61 is connected with the logic gate circuit 5 and a set terminal S thereof is connected with the switching control signal S.sub.g, and a reset terminal R of the second RS trigger 62 is connected with the logic gate circuit 5 and a set terminal S thereof is connected with a reverse switching control signal S.sub.g. The fault detection circuit 1 may detect whether open circuit occurs on the solid state switch SW according to logic levels of a result FS.sub.1 output by the output terminal Q of the first RS trigger 61 and a result FS.sub.2 output by the output terminal Q of the second RS trigger 62.

[0029] In one example, the logic gate circuit 5 may comprise a first NOT gate 51, a second NOT gate 52, a third NOT gate 53, a first NAND gate 54, a second NAND gate 55, a first OR gate 56 and a second OR gate 57.

[0030] In embodiments of the present invention, the fault detection circuit 1 may further comprise a delay circuit 7 for delaying the switching control signal S.sub.g to obtain a delayed switching control signal S.sub.gr. The fault detection circuit 1 detects the solid state switch SW based on the measured voltage V.sub.m of two terminals of the inductor L, the reference voltage V.sub.r and the delayed switching control signal S.sub.gr.

[0031] The delay circuit 7 comprises a first branch (not indicated) and a second branch (not indicated) which are connected in parallel, and a capacitor C.sub.1 connected with the first and the second branches. The first branch comprises a first diode D.sub.1 and a first resistor R.sub.1 which are connected in series, the second branch comprises a second diode D.sub.2 and a second resistor R.sub.2 which are connected reversely and in series. The resistance of the first resistor R.sub.1, the resistance of the second resistor R.sub.2 and the capacitance of the capacitor C.sub.1 are relevant with delay of the solid state switch SW's switching on and off.

[0032] Continuing to refer to FIG. 4, the first NOT gate 51 has an input terminal connected with the switching control signal S.sub.g. In this embodiment, the input terminal of the first NOT gate 51 is connected with the delayed switching control signal S.sub.gr. The delayed switching control signal S.sub.gr outputs S.sub.gr through the first NOT gate 51.

[0033] The first NAND gate 54 has a first input terminal connected with the output terminal of the comparator 4, and a second input terminal connected with the switching control signal S.sub.g (the delayed switching control signal S.sub.gr in this embodiment). The comparison result S.sub.m output by the comparator 4 and the delayed switching control signal S.sub.gr are output as F.sub.1 through the first NAND gate 54.

[0034] The second NAND gate 55 has a first input terminal connected with the output terminal of the comparator 4, and a second input terminal connected with an output terminal of the first NOT gate 51. The comparison result S.sub.m output by the comparator 4 and the result S.sub.gr output by the first NOT gate 51 are output as F.sub.2 through the second NAND gate 55.

[0035] The second NOT gate 52 has an input terminal connected with the output terminal Q of the second RS trigger 62. The result FS.sub.2 output by the output terminal Q of the second RS trigger 62 is output as FS.sub.2 through the second NOT gate 52.

[0036] The third NOT gate 53 has an input terminal connected with the output terminal Q of the first RS trigger 61. The result FS.sub.1 output by the output terminal Q of the first RS trigger 61 is output as FS.sub.1 through the third NOT gate 53.

[0037] The first OR gate 56 has a first input terminal connected with an output terminal of the first NAND gate 54, a second input terminal connected with an output terminal of the second NOT gate 52, and an output terminal connected with the reset terminal R of the first RS trigger. The result F.sub.1 output by the first NAND gate 54 and the result FS.sub.2 output by the second NOT gate 52 are output as F.sub.1r through the first OR gate 56.

[0038] The second OR gate 57 has a first input terminal connected with an output terminal of the third NOT gate 53, a second input terminal connected with an output terminal of the second NAND gate 55, and an output terminal connected with the reset terminal R of the second RS trigger 62. The result FS.sub.1 output by the third NOT gate 53 and the result F.sub.2 output by the second NAND gate 55 are output as F.sub.2r through the second OR gate 57.

[0039] FIG. 5 and FIG. 6 show waveform graphs of the fault detection circuit 1 in the condition that the solid state circuit breaker 100 is normal and in the condition that open circuit occurs on the solid state circuit breaker 100 respectively. The following Table 1 is a truth table of the first RS trigger 61 and the second RS trigger 62. Hereinafter, with reference to FIG. 4 in combination with FIGS. 5, 6 and Table 1, it will be described in details how the fault detection circuit 1 achieves fault detection.

TABLE-US-00001 TABLE 1 Truth Table of the first and second RS triggers 61, 62 S R Q Q.sub.n 1 0 0 1 0 1 1 0 0 0 1 1 1 1 Kept Kept

[0040] With reference to FIG. 4 and FIG. 5, in the condition that the solid state circuit breaker 100 is normal, when the switching control signal S.sub.g is a high level of 1, the value of the voltage V.sub.m of the two terminals of the inductor L is less than the reference voltage V.sub.r. At this moment, the result S.sub.m output by the comparator 4 is a low level of 0. In the condition that the switching control signal S.sub.g is a high level of 1, the delayed switching control signal S.sub.gr is also a high level of 1, therefore, the result F.sub.1 output through the first NAND gate 54 is a high level of 1. The result FS.sub.2 output by the output terminal Q of the second RS trigger 62 initially is set to be a high level of 1, therefore, the result FS.sub.2 output through the second NOT gate 52 is a low level of 0. Then, the result F.sub.1r output through the first OR gate 56 is a high level of 1, and F.sub.1r is connected to the reset terminal R of the first RS trigger 61, the set terminal S of the first RS trigger 61 is connected to the switching control signal S.sub.g, therefore, in the condition that the set terminal S of the first RS trigger 61 is a high level of 1 and the reset terminal R of the first RS trigger 61 is a high level of 1, it can be concluded according to Table 1 that the result FS.sub.1 output by the output terminal Q of the first RS trigger 61 is kept to be a high level of 1. The result S.sub.gr output through the first NOT gate 51 by the delayed switching control signal S.sub.gr having a high level of 1 is a low level of 0, therefore, the result F.sub.2 output through the second NAND gate 55 is a high level of 1. The result FS.sub.1 output by the output terminal Q of the first RS trigger 61 initially is set to be a high level of 1, therefore, the result FS.sub.1 output through the third NOT gate 53 is a low level of 0. Then, the result F.sub.2r output through the second OR gate 57 is a high level of 1, and F.sub.2r is connected to the reset terminal R of the second RS trigger 62, the set terminal S of the second RS trigger 62 is connected to the reverse switching control signal S.sub.g, therefore, in the condition that the set terminal S of the second RS trigger 62 is a low level of 0 and the reset terminal R of the second RS trigger 62 is a high level of 1, it can be concluded according to Table 1 that the result FS.sub.2 output by the output terminal Q of the second RS trigger 62 is a high level of 1.

[0041] With reference to the duration of t.sub.1-t.sub.2 in FIG. 4 and FIG. 6, in the condition that a fault of open circuit occurs on the solid state circuit breaker 100, when the switching control signal S.sub.g is a high level of 1, the value of the voltage V.sub.m of the two terminals of the inductor L is higher than the reference voltage V.sub.r. At this moment, the result S.sub.m output by the comparator 4 is a high level of 1. In the condition that the switching control signal S.sub.g is a high level of 1, the delayed switching control signal S.sub.gr is also a high level of 1, therefore, the result F.sub.1 output through the first NAND gate 54 is a low level of 0. The result FS.sub.2 output by the output terminal Q of the second RS trigger 62 before the fault of open circuit occurs is a high level of 1, therefore, the result FS.sub.2 output through the second NOT gate 52 is a low level of 0. Then, the result F.sub.1r output through the first OR gate 56 is a low level of 0, and F.sub.1r is connected to the reset terminal R of the first RS trigger 61, the set terminal S of the first RS trigger 61 is connected to the switching control signal S.sub.g, therefore, in the condition that the set terminal S of the first RS trigger 61 is a high level of 1 and the reset terminal R of the first RS trigger 61 is a low level of 0, it can be concluded according to Table 1 that the result FS.sub.1 output by the output terminal Q of the first RS trigger 61 is a low level of 0. The result S.sub.gr output through the first NOT gate 51 by the delayed switching control signal S.sub.gr having a high level of 1 is a low level of 0, therefore, the result F.sub.2 output through the second NAND gate 55 is a high level of 1. The result FS.sub.1 output by the output terminal Q of the first RS trigger 61 before the fault of open circuit occurs is a high level of 1, therefore, the result FS.sub.1 output through the third NOT gate 53 is a low level of 0. Then, the result F.sub.2r output through the second OR gate 57 is a high level of 1, and F.sub.2r is connected to the reset terminal R of the second RS trigger 62, the set terminal S of the second RS trigger 62 is connected to the reverse switching control signal S.sub.g, therefore, in the condition that the set terminal S of the second RS trigger 62 is a low level of 0 and the reset terminal R of the second RS trigger 62 is a high level of 1, it can be concluded according to Table 1 that the result FS.sub.2 output by the output terminal Q of the second RS trigger 62 is a high level of 1.

[0042] Therefore, summing up, a logic diagnosis result for the fault detection circuit 1 as shown in Table 2 below may be obtained.

TABLE-US-00002 TABLE 2 Health Status S.sub.g S.sub.m FS.sub.1 FS.sub.2 Normal 1 0 1 1 Open Circuit 1 1 0 1

[0043] Based on the comparison result S.sub.m output by the comparator 4 and the switching control signal S.sub.g, the result FS.sub.1 output by the output terminal Q of the first RS trigger 61 and the result FS.sub.2 output by the output terminal Q of the second RS trigger 62 may be obtained, and consequently it may be determined whether a fault of open circuit occurs on the solid state circuit breaker 100 based on the FS.sub.1 and FS.sub.2. In the embodiment, the result FS.sub.1 output by the output terminal Q of the first RS trigger 61 and the result FS.sub.2 output by the output terminal Q of the second RS trigger 62 may be used as the 7.sup.th bit and the 8.sup.th bit of the code CH.

[0044] It shall be noted that the comparator 4 and the various kinds of gate circuits herein only represent modules for achieving corresponding functions thereby, which are not limited to hardware manners, but may be implemented by software, hardware or combinations of the two.

[0045] In embodiments of the present invention the solid state circuit breaker 100 can diagnose health status of itself and determine fault type in a condition that a fault occurs.

[0046] Similarly, the motor driving system 200 of embodiments of the present invention can diagnose health status of the solid state circuit breaker 100 itself and determine fault type in a condition that a fault occurs on the solid state circuit breaker 100, thus preventing the electrical motor 102 from being damaged.

[0047] This written description uses examples to disclose the invention, including the preferred embodiments, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.