METHODS OF MAKING PRINTED STRUCTURES
20230091571 · 2023-03-23
Inventors
- Christopher Andrew Bower (Raleigh, NC, US)
- Matthew Alexander Meitl (Durham, NC, US)
- Brook Raymond (Cary, NC, US)
- Salvatore Bonafede (Chapel Hill, NC, US)
Cpc classification
H01L2224/1319
ELECTRICITY
H01L2224/0401
ELECTRICITY
B32B37/1292
PERFORMING OPERATIONS; TRANSPORTING
H01L21/4853
ELECTRICITY
B32B37/10
PERFORMING OPERATIONS; TRANSPORTING
H01L2224/1403
ELECTRICITY
H01L2224/131
ELECTRICITY
H01L2224/13023
ELECTRICITY
H01L2933/0066
ELECTRICITY
H01L2224/95
ELECTRICITY
H01L2224/24226
ELECTRICITY
H01L2224/131
ELECTRICITY
H01L2221/68363
ELECTRICITY
H01L2224/13007
ELECTRICITY
H01L2224/82
ELECTRICITY
B32B2457/206
PERFORMING OPERATIONS; TRANSPORTING
H01L2224/82
ELECTRICITY
H01L2224/16227
ELECTRICITY
H01L2224/75745
ELECTRICITY
H01L2224/1411
ELECTRICITY
H01L2224/16237
ELECTRICITY
H01L2224/136
ELECTRICITY
H01L2224/05638
ELECTRICITY
H01L24/95
ELECTRICITY
H01L2224/81395
ELECTRICITY
H01L33/62
ELECTRICITY
H01L2924/00014
ELECTRICITY
H05K3/3436
ELECTRICITY
H01L2221/68381
ELECTRICITY
H01L2224/81191
ELECTRICITY
H05K2201/10803
ELECTRICITY
H01L24/82
ELECTRICITY
H01L2924/00014
ELECTRICITY
H01L24/25
ELECTRICITY
H01L2224/136
ELECTRICITY
H01L2224/13186
ELECTRICITY
B32B37/16
PERFORMING OPERATIONS; TRANSPORTING
H01L2224/95
ELECTRICITY
H01L2224/81986
ELECTRICITY
H01L2224/05638
ELECTRICITY
B32B37/26
PERFORMING OPERATIONS; TRANSPORTING
B32B7/14
PERFORMING OPERATIONS; TRANSPORTING
H01L2224/04105
ELECTRICITY
H01L2221/68345
ELECTRICITY
H01L23/49811
ELECTRICITY
H01L2224/13186
ELECTRICITY
H01L2224/1319
ELECTRICITY
H01L2224/95136
ELECTRICITY
International classification
H05K3/32
ELECTRICITY
B32B37/10
PERFORMING OPERATIONS; TRANSPORTING
B32B37/12
PERFORMING OPERATIONS; TRANSPORTING
B32B37/16
PERFORMING OPERATIONS; TRANSPORTING
B32B37/26
PERFORMING OPERATIONS; TRANSPORTING
B32B7/14
PERFORMING OPERATIONS; TRANSPORTING
H05K1/11
ELECTRICITY
Abstract
An example of a method of making a printed structure comprises providing a destination substrate, contact pads disposed on the destination substrate, and a layer of adhesive disposed on the destination substrate. A stamp with a component adhered to the stamp is provided. The component comprises a stamp side in contact with the stamp and a post side opposite the stamp side, a circuit, and connection posts extending from the post side. Each of the connection posts is electrically connected to the circuit. The component is pressed into contact with the adhesive layer to adhere the component to the destination substrate and to form a printed structure having a volume defined between the component and the destination substrate. The stamp is removed and the printed structure is processed to fill or reduce the volume.
Claims
1-35. (canceled)
36. An electrical interconnection structure, comprising: a destination substrate, contact pads disposed on or in the destination substrate, and a patterned layer of adhesive disposed on the destination substrate; a component having a post side and comprising connection posts extending from the post side, each of the connection posts electrically connected to one of the contact pads, and at least a portion of the post side in contact with the patterned layer of adhesive, wherein the patterned layer of adhesive occupies a portion of a volume between the component and the destination substrate and the patterned layer of adhesive presses the connection posts to the contact pads.
37. The electrical interconnection structure of claim 36, wherein the patterned layer of adhesive does not contact the connection posts.
38. The electrical interconnection structure of claim 36, wherein the adhesive is not crosslinked.
39. The electrical interconnection structure of claim 36, wherein the adhesive is crosslinked.
40. The electrical interconnection structure of claim 36, wherein the layer of adhesive is disposed such that at least a portion of the contact pads are uncovered.
41. The electrical interconnection structure of claim 36, wherein the layer of adhesive is disposed such that no adhesive is between the connection posts and the contact pads.
42. The electrical interconnection structure of claim 36, wherein the layer of adhesive has a thickness over the destination substrate that is less than a distance between the post side and the destination substrate.
43. The electrical interconnection structure of claim 36, wherein the adhesive is cured.
44. The electrical interconnection structure of claim 36, wherein the adhesive pattern is defined by spacing of components over the destination substrate.
45. The electrical interconnection structure of claim 36, wherein the adhesive is one or more of polybenzoxazole (PBO), an epoxy, a polyimide, a photoresist, and an acrylic.
46. The electrical interconnection structure of claim 36, wherein an amount of volumetric contraction is greater than an amount of thermal expansion of the adhesive at an upper working temperature of the adhesive.
47. The electrical interconnection structure of claim 36, wherein the volume is partially unfilled.
48. The electrical interconnection structure of claim 36, wherein the adhesive is wicked over or on one or more surfaces of one or more of the component, the contact pads, and the destination substrate into the volume.
49. The electrical interconnection structure of claim 36, wherein each of the connection posts is electrically conductive and comprises a sharp point.
50. The electrical interconnection structure of claim 36, wherein each of the connection posts is electrically conductive and has a height that is greater than a base width, and a base area that is greater than a peak area.
51. The electrical interconnection structure of claim 36, wherein each of the connection posts comprises a conductive metal.
52. The electrical interconnection structure of claim 36, wherein the component comprises an active circuit.
53. The electrical interconnection structure of claim 36, wherein the component comprises an integrated circuit, a transistor, or an LED.
54. The electrical interconnection structure of claim 36, wherein the component has at least one dimension between 1 micron and 200 microns.
55. The electrical interconnection structure of claim 36, wherein the component comprises more than two connection posts extending from the post side, each of the more than two connection posts electrically connected to the circuit and each of the more than two connection posts connected to one of the contact pads.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0112] The foregoing and other objects, aspects, features, and advantages of the present disclosure will become more apparent and better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:
[0113]
[0114]
[0115]
[0116]
[0117]
[0118]
[0119]
[0120]
[0121]
[0122]
[0123]
[0124]
[0125]
[0126]
[0127]
[0128]
[0129] The features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The figures are not drawn to scale since the variation in size of various elements in the Figures is too great to permit depiction to scale.
DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS
[0130] The present disclosure provides, inter alia, structures and methods for electrically connecting relatively small electrical components such as integrated circuit chiplets (or components including integrated circuit chiplets), for example, to a relatively large destination substrate. Using embodiments of structures and methods disclosed herein, electrical connection can be made in an efficient and cost-effective way. Referring to the cross section of
[0131] The component 10 can be an active component, for example including one or more active elements such as electronic transistors or diodes or light-emitting diodes and photodiodes that produce an electrical current in response to ambient light. Alternatively, the component 10 can be a passive component, for example including one or more passive elements such as resistors, capacitors, or conductors. In some embodiments, the component 10 is a compound component 10 that includes both active and passive elements. The component 10 can be a semiconductor device having one or more semiconductor layers 11, such as an integrated circuit. The component 10 can be an unpackaged die. In some embodiments, the component 10 is a compound element having a plurality of active or passive elements, such as multiple semiconductor devices with separate substrates, each with one or more active elements or passive elements, or both. In certain embodiments, the plurality of elements is disposed and interconnected on a compound element substrate separate from the substrates of any semiconductor devices or a different substrate. The compound element can be micro transfer printed itself after the elements have been arranged thereon. The components 10 can be electronic processors, controllers, drivers, light-emitting diodes, photodiodes, light-control devices, or light-management devices.
[0132] The components 10 made by methods according to certain embodiments can include or be a variety of chiplets having semiconductor structures, including a diode, a light-emitting diode (LED), a transistor, or a laser. Chiplets are small integrated circuits and can be unpackaged dies released from a source wafer and can be micro transfer printed. Components 10 (or chiplets 70, for example, included in a component 10) can have at least one of a width, a length, and a height from 2 to 50 .Math.m (e.g., 2 to 5 .Math.m, 5 to 10 .Math.m, 10 to 20 .Math.m, or 20 to 50 .Math.m). Chiplets 70 can have a doped or undoped semiconductor substrate thickness of 2 to 50 .Math.m (e.g., 2 to 5 .Math.m, 5 to 10 .Math.m, 10 to 20 .Math.m, or 20 to 50 .Math.m). The chiplets 70 or components 10 can be micro-light-emitting diodes with a length greater than width, for example having an aspect ratio greater than or equal to 2, 4, 8, 10, 20, or 50 and component contact pads 12 that are adjacent to the ends of the printable semiconductor components 10 along the length of the printable semiconductor components 10. This structure enables low-precision manufacturing processes to electrically connect wires to the f component contact pads 12 without creating registration problems and possible unwanted electrical shorts or opens.
[0133] The components 10 can include active elements such as electronic circuits 14 formed using lithographic processes and can include passive elements such as electrical connections, e.g., wires, to the component contact pads 12 and connection posts 16. In certain embodiments, the component contact pads 12 are planar electrical connections formed on the process side 40 of the component 10 and source wafer. Such component contact pads 12 are typically formed from metals such as aluminum or polysilicon using masking and deposition processes used in the art. In certain embodiments, the component contact pads 12 are electrically connected to the circuit 14 with wires 13. In some embodiments the component contact pads 12 are directly electrically connected to the circuit 14 without intervening wires. In some embodiments, component contact pads 12 and the circuit 14, together with other functional structures formed in the active layer on the source wafer make up the component 10, or chiplet.
[0134] In some embodiments, the contact pads 12 are omitted and the connection posts are electrically connected to the circuit 14 with the wires 13. In some embodiments, each contact pad 12 and its respective connection post 16 are a single component (e.g., formed together as contact terminal).
[0135] In some embodiments, the components 10 are small integrated circuits, for example chiplets, having a thin substrate with a thickness of only a few microns, for example less than or equal to 25 microns, less than or equal to 15 microns, or less than or equal to 10 microns, and a width or length of 5-10 microns, 10-50 microns, 50-100 microns, or 100-1000 microns. Such chiplet components 10 can be made in a source semiconductor wafer (e.g., a silicon or GaN wafer) having a process side 40 and a back side 42 used to handle and transport the wafer. Components 10 are formed using lithographic processes in an active layer on or in the process side 40 of the source wafer. An empty release layer space is formed beneath the components 10 with tethers connecting the components 10 to the source wafer in such a way that pressure applied against the components 10 breaks the tethers to release the components 10 from the source wafer. Methods of forming such structures are described, for example, in the paper “AMOLED Displays using Transfer-Printed Integrated Circuits” and U.S. Pat. 8,889,485 referenced above. Lithographic processes for forming components 10 in a source wafer, for example transistors, wires, and capacitors, can be used in the integrated circuit art.
[0136] According to some embodiments, the native source wafer can be provided with the components 10, release layer, tethers, and connection posts 16 already formed, or they can be constructed as part of a method in accordance with some embodiments.
[0137] Connection posts 16 are electrical connections formed on the process side 40 of the component 10 that extend generally perpendicular to the surface of the process side 40. Such connection posts 16 can be formed from metals such as aluminum, titanium, tungsten, copper, silver, gold, or other conductive metals. The connection posts 16 can be formed by repeated masking and deposition processes that build up three-dimensional structures. In some embodiments, the connection posts 16 are made of one or more high elastic modulus metals, such as tungsten. As used herein, a high elastic modulus is an elastic modulus sufficient to maintain the function and structure of the connection post 16 when pressed into a backplane contact pads 22, as described further below with respect to
[0138] In certain embodiments, the electrical connections 15 include patterned metal layers forming component contact pads 12. The contact pads 12 can be made using integrated circuit photolithographic methods. Likewise, the connection posts 16 can be made by etching one or more layers of metal evaporated or sputtered on the process side 40 of the component 10. Such structures can also be made by forming a layer above the component 10 surface, etching a well into the surface, filling it with a conductive material such as metal, and then removing the layer. In some embodiments, the connection posts 16 are electrically connected to the circuit 14 and the connection posts 16 and the circuit 14, together with other functional active or passive structures formed in the active layer on the source wafer, make up the component 10.
[0139] The connection posts 16 can have a variety of aspect ratios and typically have a peak area smaller than a base area. The connection posts 16 can have a sharp point for embedding in or piercing backplane contact pads 22 (described further below). Components 10 with protruding connection posts 16 generally are discussed in U.S. Pat. 8,889,485 whose contents are incorporated by reference herein in their entirety.
[0140] As shown in the Figures, the connection posts 16 can have a base width W representing a planar dimension of the connection post 16 on the process side 40 and a height H representing the extent of the connection post 16 from the process side 40 to the peak of the connection post 16. The peak of the connection post 16 can have a width W2 less than W that, in some embodiments, approaches zero so the connection post 16 has a sharp point. The base of the connection post 16 can have a base area in contact with the process side 40 and a peak area smaller than the base area. The connection post 16 can also have a height H greater than a base dimension.
[0141] Referring to
[0142] The multi-layer connection post 16 can be made using photolithographic methods, for example coating and then pattern-wise curing materials such as resins or metals that can be etched. The connection post 16 or post material 18 can be a semiconductor materiel, such as silicon or GaN, formed by etching material from around the connection post 16. Coatings, such as the conductive material 19 can be evaporated or sputtered over the post material 18 structure and then pattern-wise etched to form the multi-layer connection post 16 of
[0143] Referring next to
[0144] Referring next to
[0145] The backplane contact pads 22 can be made of a relatively soft metal, such as tin, solder, or tin-based solder, to assist in forming good electrical contact with the connection posts 16 and adhesion with the components 10. As used herein, a soft metal may refer to a metal into which a connection post 16 can be pressed to form an electrical connection between the connection post 16 and the backplane contact pad 22. In this arrangement, the backplane contact pad 22 can plastically deform and flow under mechanical pressure to provide a good electrical connection between the connection post 16 and the backplane contact pad 22.
[0146] In some embodiments, the connection posts 16 can include a soft metal and the backplane contact pads 22 include a high elastic modulus metal. In this arrangement, the connection posts 16 can plastically deform and flow under mechanical pressure to provide a good electrical connection between the connection post 16 and the backplane contact pads 22.
[0147] If an optional adhesive layer is formed on the destination substrate 20, the connection posts 16 can be driven through the adhesive layer to form an electrical connection with the backplane contact pads 22 beneath the adhesive layer. The adhesive layer can be cured to more firmly adhere the components 10 to the destination substrate 20 and maintain a robust electrical connection between the connection posts 16 and backplane contact pads 22 in the presence of mechanical stress. The adhesive layer can undergo some shrinkage during the curing process that can further strengthen the electrical connectivity and adhesion between the connection post 16 and the backplane contact pads 22.
[0148] As shown in
[0149] In some embodiments, the connection posts 16 of the components 10 are in contact with, are embedded in, or pierce the backplane contact pads 22 of the destination substrate 20.
[0150] As noted above with reference to
[0151] In some embodiments, the backplane contact pads are coated with an optional polymer layer that can extend over the destination substrate (for example as shown in
[0152] As shown in
[0153] Referring next to
[0154] The pillars 32 of the stamp are pressed against corresponding components 10 into the release layer to adhere the components 10 to the pillars 32 to transfer the pressed components 10 from the source wafer to the stamp pillars 32 in step 110. By pressing the stamp against the components 10, the tethers are broken and the components 10 are adhered to the pillars 32, for example by van der Waal’s forces. The stamp is removed from the source wafer, leaving the components 10 adhered to the pillars 32. In some embodiments, the pillars 32 have a planar dimension, for example a width, smaller than the distance D2 between the connection posts 10 on the components 10. Thus, the pillars 32 of the stamp fit between the connection posts 16 to make intimate contact with the surface of the components 10 to enhance the adhesive effect of the van der Waal’s forces and improve adhesion between the components 10 and the pillars 32. If the pillars 32 were located over the connection posts 16, the connection posts 16 would form a standoff between the process side 40 of the components 10 and the pillars 32, greatly decreasing the attractive force of the van der Waal’s force between the components 10 and the pillars 32.
[0155] Referring again to step 104 of
[0156] In step 120, the components 10 adhered to the pillars 32 of the stamp are brought into contact with the pillars 32 of the transfer stamp 30. Because the area of the pillars 32 of the transfer stamp 30 is larger than the area of the pillars 32 of the stamp, the van der Waal’s forces between the components 10 and the pillars 32 of the transfer stamp 30 is greater than the van der Waal’s forces between the components 10 and the pillars 32 of the stamp. Therefore, the components 10 will transfer to the pillars 32 of the transfer stamp 30 when the stamp is removed leaving the components 10 adhered to the pillars 32 of the transfer stamp 30. If the pillars 32 of the stamp and transfer stamp 30 are made of different material, the pillars 32 of the transfer stamp 30 should have a surface area sufficient to transfer the components 10 to the pillars 32 of the transfer stamp 30 from the pillars 32 of the stamp. If the pillars 32 of the transfer stamp 30 form a vacuum collet, the vacuum collet must be small enough to contact single components 10 and the vacuum must be strong enough to remove the contacted single component 10 from the pillars 32 of the stamp and transfer it to the pillars 32 of the transfer stamp 30.
[0157] The stamp can have more pillars 32 than the transfer stamp 30 has. Thus, not all of the components 10 on the pillars 32 of the stamp will transfer to the pillars 32 of the transfer stamp 30. The transfer stamp 30 can be laterally translated with respect to the stamp to sequentially transfer subsets of the components 10 from the pillars 32 of the stamp to the pillars 32 of the transfer stamp 30. Since the pillars 32 of the stamp are spatially aligned to the components 10 on the source wafer, to enable a sparser distribution of components 10 on the transfer stamp 30, the transfer stamp 30 can have fewer pillars 32 than the stamp so as to spatially distribute the components 10 farther apart.
[0158] The transfer stamp 30 can include pillars 32 that form vacuum collets. By applying a vacuum (or partial vacuum) to the vacuum collets, the components 10 can be transferred to the transfer stamp 30. The transfer stamp 30 is aligned with the stamp, vacuum is applied to the vacuum collets, and the transfer stamp 30 is removed from the stamp, leaving the components 10 adhered to the pillars 32 of the transfer stamp 30.
[0159] The spatial distribution of the components 10 is a matter of design choice for the end product desired. In one embodiment, all of the components 10 in a source wafer array are transferred to the stamp. In some embodiments, a subset of the components 10 in the source wafer array is transferred. Similarly, in some embodiments, all of the components 10 on the pillars 32 of the stamp array are transferred to the pillars 32 of the transfer stamp 30. In some embodiments, a subset of the components 10 on the pillars 32 of the stamp are transferred to the pillars 32 of the transfer stamp 30. By varying the number and arrangement of pillars 32 on the stamp and transfer stamps 30, the distribution of components 10 on the pillars 32 of the transfer stamp 30 can be likewise varied, as can the distribution of the components 10 on the destination substrate 20.
[0160] In a further embodiment, referring to step 106 of
[0161] The adhesion between the components 10 and the receiving side of the destination substrate 20 should be greater than the adhesion between the components 10 and the pillars 32 of the transfer stamp 30. As such, when the transfer stamp 30 is removed from the receiving side of the destination substrate 20, the components 10 adhere more strongly to the destination substrate 20 than to the transfer stamp 30, thereby transferring the components 10 from the transfer stamp 30 to the receiving side of the destination substrate 20.
[0162] The transfer stamp 30 is then removed leaving the components 10 adhered to the destination substrate 20. An optional heat treatment in step 150 can solder or weld the connection posts 16 of the components 10 to the backplane contact pads 22 of the destination substrate 20. Thus, in a further method, the backplane contact pads 22 (or connection posts 16) are heated, causing the backplane contact pad metal to reflow and improve adhesion between the components 10 and the destination substrate 20 and improve the electrical connection to the connection posts 16.
[0163] Thus, referring next to
[0164] A stamp having a plurality of pillars 32 formed thereon is spatially aligned to the components 10. Each pillar 32 of the stamp has a first area. The pillars 32 of the stamp are pressed against corresponding components 10 to adhere the components 10 to the pillars 32 of the stamp. A transfer stamp 30 having a plurality of pillars 32 is spatially aligned to the pillars 32 of the stamp. Each pillar 32 of the transfer stamp 30 has a second area greater than the first area. The pillars 32 of the transfer stamp 30 are pressed against corresponding components 10 on the pillars 32 of the stamp to adhere the components 10 to the pillars 32 of the transfer stamp 30. The components 10 are aligned with and then pressed against the destination substrate 20 to adhere the components 10 to the destination substrate 20.
[0165] In an additional embodiment, referring to
[0166] In some embodiments, an electronically active substrate includes a destination substrate 20 having a plurality of backplane contact pads 22. The backplane contact pads 22 have a surface. A plurality of components 10 are distributed over the destination substrate 20. Each component 10 includes a component substrate, for example a semiconductor substrate, different from the destination substrate 20, for example a printed circuit board resin or epoxy substrate. Each component 10 has a circuit 14 and connection posts 16 formed on a process side 40 of the component substrate. The connection posts 16 have a base width and a height that is greater than the base width. The connection posts 16 are in electrical contact with the circuit 14 and the backplane contact pads 22. The connection posts 16 are in contact with, embedded in, or driven through the surface of the backplane contact pads 22 into the backplane contact pads 22 to electrically connect the connection posts 16 to the backplane contact pads 22.
[0167] In some embodiments, an adhesive layer 18 is formed over the destination substrate 20 between the active components 10 and the destination substrate 20 (see also
[0168] Referring next to
[0169] A material layer, for example an insulating layer such as a first dielectric layer 64, for example an inorganic dielectric such as silicon dioxide or silicon nitride, or an organic insulator such as a polymer or a curable polymer, resin or epoxy is coated over the patterned layer of conductive material (including the connection posts 16) and the forming substrate 62 (
[0170] The printable component is then defined, for example by etching the first dielectric layer 64 (for example using an anisotropic etch, an aqueous base etchant, KOH, or TMAH) to form a release layer and anchors in the forming substrate 60 connected by tethers to the printable component. In one embodiment, second or third dielectric layers are provided to facilitate the definition of the printable component, the anchors, and the tethers. Referring to
[0171] In a further embodiment, a stamp 80 is used to release the printable component from the forming substrate 60 as part of a micro transfer print process, as shown in
[0172]
[0173] In a further embodiment, the component is a light-emitting component that emits light. In one arrangement, the light is emitted in a direction opposite to the connection posts 16. In a further embodiment, the chiplet 70 is covered with a second dielectric layer (e.g., second dielectric layer 66). The second dielectric layer 66 can be transparent to visible light or to the frequencies of light emitted by the light emitter and the light can be emitted through the second dielectric layer 66.
[0174] Referring next to
[0175] Referring also to
[0176] As shown in
[0177] As shown in
[0178] According to some embodiments, referring to
[0179] The adhesive layer 29 can be disposed as a patterned or an unpatterned adhesive layer 29. The adhesive layer 29 can be patterned without crosslinking, thereby facilitating adhesion between the adhesive layer 29 and the component 10. The adhesive layer 29 can be patterned and provided uncrosslinked, thereby facilitating adhesion between the adhesive layer 29 and the component 10. The adhesive 29 can be crosslinked after the component 10 is pressed into the adhesive layer 29 (e.g., during processing). The adhesive layer 29 can be disposed as a pattern that leaves at least a portion of the contact pads 22 uncovered or disposed as a pattern such that no adhesive 29 is between the connection posts 16 and contact pads 22, or both. The step of processing the printed structure 50 can comprise changing the pattern of the adhesive 29 from a first shape with an area parallel to the destination substrate 20 and a height perpendicular to the destination substrate 20 to a second shape having a smaller height and a larger area.
[0180] In some embodiments, pressing connection posts 16 into an adhesive layer 29 contacts each of the connection posts 16 to a contact pad 22 (e.g., of a plurality of contact pads 22). In some embodiments, the step of pressing the connection posts 16 into the adhesive layer 29 does not contact each connection post 16 to a contact pad 22. In some embodiments, the adhesive layer 29 is disposed such that at least a portion of the contact pads 22 is uncovered. In some embodiments, the adhesive layer 29 is disposed such that no adhesive 29 is between the connection posts 16 and the contact pads 22.
[0181] The adhesive layer 29 can be provided with a thickness over the destination substrate 20 that is less than a distance between the post side 40 and the destination substrate 20 after the step of pressing the connection posts 16 into the adhesive layer 29 or that is greater than or equal to a distance between the post side 40 and the destination substrate 20 after the step of pressing the connection posts 16 into the adhesive layer 29. In some embodiments, the adhesive layer 29 is provided with a thickness over the destination substrate 20 that is less a height of one or more connection posts 16. In some embodiments, the adhesive layer 29 is provided with a thickness that is greater than a height of one or more connection posts 16.
[0182] In some embodiments, adhesive 29 is cured (e.g., during processing). The adhesive 29 can be cured in a pattern defined by the components 10 over the destination substrate 20. The adhesive 29 can be a positive resist. In some embodiments, a method comprises removing adhesive 29 from the area over the destination substrate 20 that is not between the component 10 and the destination substrate 20. The adhesive 29 can be or comprise, for example, one or more of polybenzoxazole (PBO), an epoxy, a polyimide, a photoresist, and an acrylic.
[0183] According to some embodiments, the amount of volumetric contraction is greater than the thermal expansion of the adhesive 29 over the working temperature of the adhesive 29 or printed structure 50. For example, an amount of volumetric contraction of an adhesive 29 is greater than an amount of thermal expansion of the adhesive 29 at an upper working (e.g., service) temperature of the adhesive 29. A volume 76 can be partially unfilled either before or after processing. A volume 76 can be filled with adhesive 29 and processing a printed structure 50 can comprise reducing the volume 76 of the adhesive 29 between a component 10 and a destination substrate 20. Processing a printed structure 50 can comprise infiltrating the adhesive from around a component 10 into a respective volume 76. Processing a printed structure 50 can comprise moving a component 10 toward a destination substrate 20. Processing a printed structure 50 can comprise wicking adhesive 29 over or on one or more surfaces of one or more of a component 10, contact pads 22, and a destination substrate 20 into a volume 76. Processing a printed structure 50 can comprise changing the viscosity or temperature of an adhesive 29, or both the viscosity and temperature of the adhesive 29. Adhesive 29 can comprise a solvent and processing a printed structure 50 can comprise changing a concentration of the solvent in the adhesive 29. According to some embodiments, processing a printed structure 50 comprises elevating the temperature of the printed structure 50 to increase the density of the adhesive 29, thereby reducing the volume 76.
[0184] Adhesive 29 can comprise one or more compounds and processing a printed structure 50 can comprise elevating the temperature of the printed structure 50 to volatilize the one or more compounds, thereby reducing a volume 76 between a component 10 and a destination substrate 20. Processing a printed structure 50 can comprise gradient heating the printed structure 50.
[0185] According to some embodiments, each connection post 16 is electrically conductive and comprises a sharp point (for example as shown in
[0186] A component 10 can be or comprise an active component 10. The component 10 can be or comprise an integrated circuit, a transistor, or an LED. The component 10 can have at least one dimension between 1 micron and 200 microns.
[0187] Methods according to certain embodiments can comprise providing more than two contact pads 22, a plurality of components 10, or both. A plurality of components 10 can be transferred using a single stamp 30 (e.g., comprising a plurality of posts). According to some embodiments, the component 10 comprises more than two connection posts 16 extending from the post side 40, each connection post 16 electrically connected to the circuit 14.
[0188] According to some embodiments, an electrical interconnection structure (e.g., a printed structure 50) comprises a destination substrate 20, contact pads 22 disposed on the destination substrate 20, and a patterned layer of adhesive 29 disposed on the destination substrate 20. A component 10 comprises a post side 40 and connection posts 16 extending from the post side 40, each connection post 16 electrically connected to one of the contact pads 22, and at least a portion of the post side 40 in contact with the patterned layer of adhesive 29. The patterned layer of adhesive 29 can occupy a portion of a volume 76 between the component 10 and the destination substrate 20 and the patterned layer of adhesive 29 can press the connection posts 16 to the contact pads 22. According to some embodiments, the patterned layer of adhesive 29 does not contact the connection posts 16.
[0189] A printed structure 50 according to some embodiments has been constructed by micro-transfer printing LEDs (components 10) to a destination substrate 20 and is shown in
[0190] According to one embodiment, the source wafer can be provided with components 10 and component contact pads 12 and connection posts 16 already formed on the process side 40 of the source wafer. Alternatively, an unprocessed source wafer can be provided and the components 10 formed on the process side 40 of the source wafer. An unprocessed source wafer is a substrate that does not yet include components 10. The unprocessed source wafer can have other processing steps completed, for example, cleaning, deposition of material layers, or heat or chemical treatments, as are used in the photo-lithographic arts. Components 10 are formed, for example using photo-lithographic processes including forming masks over the source wafer, etching materials, removing masks, and depositing materials. Such processes are used in the photo-lithographic arts. Using such processes, components 10 are formed on or in the process side 40 of the source wafer.
[0191] Components 10 can be small electronic integrated circuits, for example, having a size of about 5 microns to about 5000 microns in at least one dimension. The electronic circuits can include semiconductor materials (for example inorganic materials such as silicon or gallium arsenide, or inorganic materials) having various structures, including crystalline, microcrystalline, polycrystalline, or amorphous structures. In some embodiments, the components 10 are passive, for example including a conductor that, when used in a printed structure 50 serves to electrically connect one conductor (e.g., a backplane contact pad 22) to another, forming a jumper. The components 10 can also include insulating layers and structures such as silicon dioxide, nitride, and passivation layers and conductive layers or structures including wires 13 made of aluminum, titanium, silver, or gold that foam an electronic circuit. Connection posts 16 or component contact pads 12 can be formed of metals such as aluminum or polysilicon semiconductors and can be located on the process side 40 of the components 10. Methods and materials for making component 10 electronic circuits are used in the integrated circuit arts. Large numbers of such small integrated circuits are formed on a single source wafer. The components 10 are typically packed as closely as possible to use the surface area of the source wafer as efficiently as possible.
[0192] In some embodiments, the components 10 are small integrated circuits formed in a semiconductor wafer, for example gallium arsenide or silicon, which can have a crystalline structure. Processing technologies for these materials typically employ high heat and reactive chemicals. However, by employing transfer technologies that do not stress the component 10 or substrate materials, more benign environmental conditions can be used compared to thin-film manufacturing processes. Thus, structures and methods according to certain embodiments of the present disclosure have an advantage in that flexible substrates, such as polymeric substrates, that are intolerant of extreme processing conditions (e.g. heat, chemical, or mechanical processes) can be employed for the destination substrates 20. Furthermore, it has been demonstrated that crystalline silicon substrates have strong mechanical properties and, in small sizes, can be relatively flexible and tolerant of mechanical stress. This is particularly true for substrates having 5 \-micron, 10 \-micron, 20 \-micron, 50 \-micron, or even 100 \-micron thicknesses. Alternatively, the components 10 can be formed in a microcrystalline, polycrystalline, or amorphous semiconductor layer.
[0193] The components 10 can be constructed using foundry fabrication processes used in the art. Layers of materials can be used, including materials such as metals, oxides, nitrides and other materials used in the integrated-circuit art. Each component 10 can be a complete semiconductor integrated circuit and can include, for example, transistors. The components 10 can have different sizes, for example, 1000 square microns or 10,000 square microns, 100,000 square microns, or 1 square mm, or larger, and can have variable aspect ratios, for example 1:1, 2:1, 5:1, or 10:1. The components 10 can be rectangular or can have other shapes.
[0194] Certain embodiments provide advantages over other printing methods described in the prior art. By employing connection posts 16 on components 10 and a printing method that provides components 10 on a destination substrate 20 with the process side 40 and connection posts 16 adjacent to the destination substrate 20, a low-cost method for printing chiplets in large quantities over a destination substrate 20 is provided. Furthermore, additional process steps for electrically connecting the components 10 to the destination substrate 20 are obviated.
[0195] The source wafer and components 10, stamp, transfer stamp 30, and destination substrate 20 can be made separately and at different times or in different temporal orders or locations and provided in various process states.
[0196] Transferring components 10 can be iteratively applied to a single or multiple destination substrates 20. By repeatedly transferring sub-arrays of components 10 from a transfer stamp 30 to a destination substrate 20 and relatively moving the transfer stamp 30 and destination substrates 20 between stamping operations by a distance equal to the spacing of the selected components 10 in the transferred sub-array between each transfer of components 10, an array of components 10 formed at a high density on a source wafer can be transferred to a destination substrate 20 at a much lower density. In practice, the source wafer is likely to be expensive, and forming components 10 with a high density on the source wafer will reduce the cost of the components 10, especially as compared to forming components on the destination substrate 20. Transferring the components 10 to a lower-density destination substrate 20 can be used, for example, if the components 10 manage elements distributed over the destination substrate 20, for example in a display, digital radiographic plate, or photovoltaic system.
[0197] In particular, in the case wherein the active component 10 is an integrated circuit formed in a crystalline semiconductor material, the integrated circuit substrate provides sufficient cohesion, strength, and flexibility that it can adhere to the destination substrate 20 without breaking as the transfer stamp 30 is removed.
[0198] In comparison to thin-film manufacturing methods, using densely populated source substrates wafers and transferring components 10 to a destination substrate 20 that requires only a sparse array of components 10 located thereon does not waste or require active layer material on a destination substrate 20. Transferring components 10 made with crystalline semiconductor materials that have higher performance than thin-film active components can also be performed in certain methods. Furthermore, the flatness, smoothness, chemical stability, and heat stability requirements for a destination substrate 20 used in some embodiments may be reduced because the adhesion and transfer process is not substantially limited by the material properties of the destination substrate 20. Manufacturing and material costs may be reduced because of high utilization rates of more expensive materials (e.g., the source substrate) and reduced material and processing requirements for the destination substrate 20.
[0199] As is understood by those skilled in the art, the terms “over” and “under” are relative terms and can be interchanged in reference to different orientations of the layers, elements, and substrates included in the present disclosure. For example, a first layer on a second layer, in some implementations means a first layer directly on and in contact with a second layer. In other implementations a first layer on a second layer includes a first layer and a second layer with another layer therebetween.
[0200] It should be understood that the order of steps or order for performing certain action is immaterial so long as the disclosed technology remains operable. Moreover, two or more steps or actions in some circumstances can be conducted simultaneously.
[0201] In this application, unless otherwise clear from context or otherwise explicitly stated, (i) the term "a" may be understood to mean "at least one"; (ii) the term "or" may be understood to mean "and/or"; (iii) the terms "comprising" and "including" may be understood to encompass itemized components or steps whether presented by themselves or together with one or more additional components or steps; (iv) the terms "about" and "approximately" may be understood to permit standard variation as would be understood by those of ordinary skill in the relevant art; and (v) where ranges are provided, endpoints are included.
[0202] Throughout the description, where apparatus and systems are described as having, including, or comprising specific components, or where processes and methods are described as having, including, or comprising specific steps, it is contemplated that, additionally, there are apparatus, and systems of the disclosed technology that consist essentially of, or consist of, the recited components, and that there are processes and methods according to the disclosed technology that consist essentially of, or consist of, the recited processing steps.
[0203] Having described certain embodiments, it will now become apparent to one of skill in the art that other implementations incorporating the concepts of the disclosure may be used. Therefore, the disclosure should not be limited to certain implementations, but rather should be limited only by the spirit and scope of the following claims.
TABLE-US-00001 PARTS LIST D1 distance D2 distance H height W base width W2 peak width 10, 10A, 10B, 10C, 10D component 11 semiconductor layer 12 component contact pad 13 wire 14 circuit 15 electrical connection 16 connection post 16A short connection post 16B deformed / crumpled connection post 17 group of connection posts 18 post material 19 conductive material / solder 20 destination substrate 22 contact pad / backplane contact pad /destination substrate contact pad 22A deformed / crumpled backplane contact pad 22B non-planar contact pad 23 perimeter portion 24 conductive material / solder 25 perimeter portion 26 layer 28 layer 29 shrinkable material / adhesive / adhesive layer 30 stamp / transfer stamp 32 pillars 40 process side / post side 42 back side / stamp side 50 printed structure / electrical interconnection structure 60 forming substrate 62 form 64 first dielectric layer 66 second dielectric layer 68 anchor 69 space 70 chiplet 72 chiplet contact pad 74 conductor 76 volume 80 stamp 100 provide source wafer step 102 provide stamp step 104 provide transfer stamp step 106 provide destination substrate step 110 contact components with stamp step 120 contact components with transfer stamp step 130 align components to destination substrate step 140 micro transfer print components to destination substrate step 150 optional heat structure step 200 provide source wafer step 210 form component structure in wafer step 220 form component contact pads on component structure step 230 coat resin and pattern-wise cure step 240 coat metal and pattern-wise etch step 300 remove component from destination substrate step 310 replace component on destination substrate step