Protection circuit for electronic system

Abstract

Damages to the rectifying MOSFET in the secondary side of voltage converters are reduced or eliminated by inserting intermediary steps between detecting a dropping in the converter output voltage V.sub.CC and activating the under voltage lock out (UVLO) circuitry. During the intermediary steps, the timing for switching off the MOSFET is advanced to prevent the current flow in the MOSFET from reversing its direction.

Claims

1. A voltage converter, comprising: a power MOSFET coupled to a secondary-side controller; the secondary-side controller, operable to sustain a V.sub.CC voltage at a V.sub.CC terminal; the secondary-side controller configured to trigger a first bias voltage when the V.sub.CC voltage is above a first preset value and to trigger a second bias voltage different from the first bias voltage when the V.sub.CC voltage is below the first preset voltage; and an under-voltage-lock-out (UVLO) circuitry, which is triggered when the V.sub.CC voltage is below a second preset voltage, which is below the first preset voltage.

2. The voltage converter of claim 1, in which the first bias voltage corresponds to a first switching-off threshold voltage of the power MOSFET.

3. The voltage converter of claim 2, in which the second bias voltage corresponds to a second switching-off threshold voltage of the power MOSFET, different from the first switching-off threshold voltage.

4. The voltage converter of claim 1, in which the secondary controller and the power MOSFET are integrated in one chip.

5. A voltage converter having a primary side controller and a secondary-side controller, comprising; a primary-side UVLO circuitry and a secondary-side UVLO circuitry; and a primary-side UVLO triggering voltage and a secondary-side UVLO triggering voltage lower than the primary-side UVLO triggering voltage; the secondary-slide controller is operable to sustain a V.sub.CC voltage at a V.sub.CC terminal; the primary-side UVLO triggering voltage and the secondary-side UVLO triggering voltage being related to V.sub.CC, and the secondary-side controller is coupled to a power MOSFET, which is configured to turn off at a second turn-off voltage different from a first turn-off voltage.

6. The voltage converter of claim 5, in which the secondary controller and the power MOSFET are integrated in one chip.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) FIG. 1 depicts a block diagram of a partial circuit of a voltage converter according to the invention.

(2) FIG. 2 depicts a block diagram of another partial circuit of voltage converter according to the invention.

DETAILED DESCRIPTION

(3) FIG. 1 depicts a portion of a voltage converter, specifically a sub-circuit 100 in the secondary side of a voltage converter. The function of the sub-circuit 100 is to interrogate the V.sub.CC voltage and to determine its relative value with respect to it to a reference voltage that is set at preset amount below the expected normal V.sub.CC. When V.sub.CC drops from its expected normal value by a preset amount, the sub-circuit triggers to change the turn-off voltage threshold of the MOSFET.

(4) The sub-circuit 100 comprises a comparator 3 with two input terminals 1, and 2, Terminal 1 is configured to receive V.sub.CC and terminal 2 is configured to receive a reference voltage. In this example, the reference voltage is set at 4.2 V, which is about 16% lower than the normal V.sub.CC of 5V. Other value for the reference voltage may be appropriate and may be used. When V.sub.CC is above 4.2 V, the system is deemed to be operating normally and the comparator outputs a 1 at its output terminal. When V.sub.CC drops below 4.2 V, the output of the comparator switches from a 1 to a 0.

(5) The output of the comparator is coupled to a multiplexor 4, Two input terminals 5 and 6 of the multiplexor 4 are configured to receive two turn-off threshold voltages V.sub.THOFF1 and V.sub.THOFF2. In this example, V.sub.THOFF1 is set at 5 mV and V.sub.THOFF2 is set at 20 mV. Other values for the turn-off threshold may be appropriate and may be used When the terminal 7 of the multiplexor 4 receives a 1 signal, indicating a normal functioning condition, it selects V.sub.THOFF1 (5 mV) at terminal 6 and passes it to the output terminal 8. When the multiplexor 4 receives a 0 signal from the comparator 3, indicating V.sub.CC as below the threshold of 4.2 V, the multiplexor 4 selects V.sub.THOFF2 (20 mV) at terminal 5 and passes it to the output terminal 8.

(6) The output of the multiplexor 4 is added as a bias voltage to a second comparator 9. The comparator 9 compares the voltage V.sub.S at one terminal 10 to V.sub.D in conjunction with the bias voltage V.sub.THOFF1 or V.sub.THOFF2 at the other input terminal 8. When the biased V.sub.D is less than V.sub.S, the comparator 9 switches and sends a signal to turn off the MOSFET.

(7) With this sub-circuit as an example, the two turn-off threshold voltages can be successfully incorporated in the converter so the MOSFET can be switched off under different timing schemes depending on whether the converter V.sub.CC is above or below the preset threshold.

(8) FIG. 2 depicts the schematic diagram of a circuit 200, which is a portion of a voltage converter, and a MOSFET 300 that is driven by the circuit 200 The circuit 208 comprises a sub-circuit 400, which is similar to the sub-circuit 100 in drawing figure

(9) The MOSFET 300 in this example is external to the circuit 200, which is built in one integrated circuit chip. In other examples, the MOSFET may be a portion of the same integrated circuit chip.

(10) The MOSFET is driven by a driver element 13, which in turn is driven by a AND gate 14. When the output of the AND gate 14 is in a high state, the driver element 13 applies a voltage near V.sub.CC on the gate terminal of the MOSFET and turn it on When the output of the AND gate 14 is in a low state, the driver element 13 applies a voltage near GND on the gate terminal of the MOSFET and turns it off.

(11) The sub-circuit 400 is coupled to a SR flip-flop 15 at its RESET terminal. The output Q of the flip-flop 15 is coupled to the AND gate 14. As illustrated in FIG. 1, when V.sub.CC drops below a threshold voltage, the sub-circuit 400 switches from a first threshold voltage V.sub.THOFF1 to a second threshold voltage V.sub.THOFF2. This changes the timing of switching-off of the MOSFET so it goes of when V.sub.D is further away from the V.sub.S. In this example, the RESET of the RS flip-flop 15 is triggered when V.sub.D is within 20 mV of V.sub.S. At this point, the MOSFET will have about 100 nano-seconds to complete turning off before V.sub.D becomes positive, which is to be avoid.

(12) The circuit 200 also comprises a comparator 16 to interrogate the V.sub.D in order to determine the timing of turning on the MOSFET. The comparator 16 is biased by V.sub.THON, which in this example is set at 150 mV. Comparator 16 compared to V.sub.D to V.sub.S and when V.sub.D is within V.sub.THON with respect to V.sub.S, the comparator 16 switches and triggers the SR flip-flop 15 and, through the AND gate 14 and the driver element 13, applies a voltage near V.sub.CC to the gate terminal of the MOSFET 300 to turn it on.

(13) The circuit 400 also comprises a UVLO circuit 17 coupled to VCC. When VCC drops below a second threshold, which in this example, is set at 3 Vabout 40% from the normal 5 V, the UVLO circuit 17 shuts down the controller circuit 200.