High electron mobility transistor and fabrication method thereof

Abstract

A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.

Claims

1. A method for forming a high-electron mobility transistor, comprising: providing a substrate; forming a buffer layer over the substrate; forming a GaN channel layer over the buffer layer; forming an AlGaN layer over the GaN channel layer; forming a GaN source layer and a GaN drain layer on the AlGaN layer within a source region and a drain region, respectively; forming a gate recess in the AlGaN layer between the source region and the drain region; forming a p-GaN gate layer in and on the gate recess; and forming a re-grown AlGaN film on the AlGaN layer, on the GaN source layer and the GaN drain layer, and on interior surface of the gate recess.

2. The method according to claim 1, wherein the GaN source layer and the GaN drain layer are composed of N.sup.++-doped GaN.

3. The method according to claim 1, wherein the GaN source layer and the GaN drain layer are composed of InGaN.

4. The method according to claim 1, wherein the gate recess penetrates through the AlGaN layer.

5. The method according to claim 1, wherein the gate recess does not penetrate through the AlGaN layer, and wherein a remaining thickness of the AlGaN layer at a bottom of the gate recess is equal to or smaller than 2 nm.

6. The method according to claim 1, wherein the re-grown AlGaN film has a thickness of less than 2 nm.

7. The method according to claim 6 further comprising: forming a protection layer covering the re-grown AlGaN film and the p-GaN gate layer.

8. The method according to claim 7 further comprising: forming a gate contact penetrating through the protection layer and directly contacting the p-GaN gate layer.

9. The method according to claim 7 further comprising: forming a source contact and a drain contact penetrating through the protection layer and directly contacting the GaN source layer and the GaN drain layer, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of a high electron mobility transistor according to an embodiment of the invention.

(2) FIG. 2 to FIG. 8 are schematic diagrams showing a method for fabricating a HEMT according to an embodiment of the invention.

DETAILED DESCRIPTION

(3) In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

(4) Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

(5) Please refer to FIG. 1, which is a cross-sectional view of a high electron mobility transistor according to an embodiment of the invention. As shown in FIG. 1, the high electron mobility transistor (HEMT) 1 includes a substrate 100 and a buffer layer 102 disposed on the substrate 100, a gallium nitride (GaN) channel layer 104 disposed on the buffer layer 102, an aluminum gallium nitride (AlGaN) layer 106 disposed on the GaN channel layer 104, a gate recess 110 is disposed in the AlGaN layer 106; a source region S and a drain region D are located on the opposite sides of the gate recess 110, a GaN source layer 121 and a GaN drain layer 122 grown on the AlGaN layer 106 within the source region S and the drain region D, respectively, and a P-type GaN (p-GaN) gate layer 112 located in and on the gate recess 110.

(6) According to an embodiment of the invention, the HEMT 1 may further comprise a re-grown AlGaN film 108 on the AlGaN layer 106, the GaN source layer 121 and the GaN drain layer 122, and on the inner surface of the gate recess 110.

(7) According to an embodiment of the invention, the HEMT 1 may further comprise a protection layer 130 covering the re-grown AlGaN film 108 and the P-type GaN gate layer 112. For example, the protection layer 130 may comprise silicon nitride, silicon oxide, or the like, but is not limited thereto. Further, a dielectric layer 140 may be formed on the protection layer 130, for example, silicon oxide or the like, but is not limited thereto.

(8) According to an embodiment of the invention, the HEMT 1 may further comprise an isolation structure 200, such as a trench isolation structure, surrounding the island-like active area that is comprised of the patterned GaN channel layer 104 and the patterned AlGaN layer 106.

(9) According to an embodiment of the invention, the GaN source layer 121 and the GaN drain layer 122 may be formed of N.sup.++ doped GaN. According to another embodiment of the present invention, the GaN source layer 121 and the GaN drain layer 122 may be composed of indium gallium nitride (InGaN).

(10) According to an embodiment of the invention, the gate recess 110 extends through the AlGaN layer 106, thereby exposing a portion of the GaN channel layer 104. According to another embodiment of the present invention, the gate recess 110 does not penetrate through the entire thickness of the AlGaN layer 106. The thickness of the AlGaN layer 106 at the bottom of the gate recess 110 is less than or equal to 2 nm. Within this thickness range, a two-dimensional electron cloud (2DEG) is not formed directly under the AlGaN layer 106.

(11) According to an embodiment of the invention, the thickness of the re-grown AlGaN film 108 is less than 2 nm.

(12) According to an embodiment of the invention, the HEMT 1 further comprises a gate contact CG penetrating the protection layer 130 and directly contacting the P-type GaN gate layer 112. According to an embodiment of the invention, the HEMT 1 further comprises a source contact CS and a drain contact CD, penetrating the protection layer 130, and directly contacting the GaN source layer 121 and the GaN drain layer 122, respectively.

(13) The structural feature of the present invention is that the HEMT 1 has a GaN source layer 121 and a GaN drain layer 122 composed of N.sup.++ doped GaN or InGaN, and has a gate recess 110. A P-type GaN gate layer 112 is disposed in and on the gate recess 110. In addition, the HEMT 1 has a re-grown AlGaN film 108 on the AlGaN layer 106, the GaN source layer 121 and the GaN drain layer 122, and on the inner surface of the gate recess 110. Combining the above features, the HEMT 1 of the present invention can realize a high withstand voltage or a high threshold voltage (Vt) and a low on-resistance (Ron) HEMT, overcoming the disadvantages and deficiencies in the prior art.

(14) Please refer to FIG. 2 to FIG. 8, which are schematic diagrams showing a method for fabricating a HEMT according to an embodiment of the invention. The same reference numerals are used to denote the same elements, layers, regions or material.

(15) As shown in FIG. 2, a substrate 100, such as a silicon substrate, is first provided. Next, a buffer layer 102, a GaN channel layer 104, an AlGaN layer 106, and a GaN layer 120 are sequentially formed on the surface of the substrate 100 in an epitaxial manner, wherein, according to an embodiment of the present invention, the GaN layer 120 may be an N.sup.++ doped GaN layer. According to an embodiment of the invention, the GaN layer 120 may be an InGaN layer. In the GaN channel layer 104, near the AlGaN layer 106, a two-dimensional electron cloud (2DEG) may be formed.

(16) Next, as shown in FIG. 3, an optical lithography and etching process may be performed to pattern the GaN layer 120 to form a GaN source layer 121 and a GaN drain layer 12 on the AlGaN layer 106 within the source region S and the drain region D, respectively. As described above, for example, the GaN layer 120 may be an N.sup.++ doped GaN layer, thus achieving the object of reducing the source and drain resistance. In addition, the dopant concentration and the activation thermal budget can be effectively controlled during the metal organic chemical vapor deposition (MOCVD) process in which the N.sup.++ doped GaN layer is grown in-situ.

(17) As shown in FIG. 4, another optical lithography and etching process may be performed to form a gate recess 110 in the AlGaN layer 106 between the source region S and the drain region D. According to an embodiment of the invention, the gate recess 110 extends through the AlGaN layer 106 to expose a portion of the GaN channel layer 104. According to another embodiment of the present invention, the gate recess 110 does not penetrate through the AlGaN layer 106. At this point, the remaining thickness of the AlGaN layer 106 at the bottom of the gate recess 110 is less than or equal to 2 nm. Within this thickness range, the 2DEG is not formed directly under the AlGaN layer 106.

(18) As shown in FIG. 5, a re-grown AlGaN film 108 is formed on the AlGaN layer 106, the GaN source layer 121 and the GaN drain layer 122, and on the inner surface of the gate recess 110. According to an embodiment of the invention, the thickness of the re-grown AlGaN film 108 is less than 2 nm. The re-grown AlGaN film 108 can repair surface damage caused by previous etching steps. Then, the P-type GaN layer 112G is grown on the surface of the re-grown AlGaN film 108.

(19) As shown in FIG. 6, another optical lithography and etching process may be performed to pattern the P-type GaN layer 112G into a P-type GaN gate layer 112. The P-type GaN gate layer 112 is formed in and on the gate recess 110.

(20) As shown in FIG. 7, an isolation structure 200, such as a trench isolation structure, is then formed surrounding the island-like active region comprised of the patterned GaN channel layer 104 and the patterned AlGaN layer 106. Then, a protection layer 130 is formed covering the re-grown AlGaN film 108 and the P-type GaN gate layer 112. For example, the protection layer 130 may comprise silicon nitride, silicon oxide, or the like, but is not limited thereto.

(21) Subsequently, as shown in FIG. 8, a dielectric layer 140, for example, silicon oxide or the like, but is not limited thereto, is formed on the protection layer 130. Then, a gate contact CG is formed, penetrating the protection layer 130, and directly contacting the P-type GaN gate layer 112. A source contact CS and a drain contact CD are formed, penetrating the protection layer 130, and directly contacting the GaN source layer 121 and the GaN drain layer 122, respectively.

(22) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.