DEEP JUNCTION LOW-GAIN AVALANCHE DETECTOR

Abstract

An avalanche diode including a gain region and a readout structure including an n-type (p-type) region having electrically isolated segments each including implanted regions; a p-type (n-type) region; and a first electrode on each of the segments. The gain region includes a p-n junction buried between the n-type region and the p-type region: an n.sup.+-type region having a higher n-type dopant density than the n-type region; a p.sup.+-type region having a higher p-type dopant density than the p-type region; and the p-n junction between the n.sup.+-type region and the p.sup.+-type region. A bias between the first electrodes and a second electrode (ohmically contacting the p-type (n-type) region) reverse biases the p-n junction. Electrons generated in response to electromagnetic radiation or charged particles generate additional electrons m the gain region through impact ionization but the segmented region comprises a low field region isolating the gain region from the first electrodes.

Claims

1. An avalanche diode, comprising: a semiconductor structure including: an n-type (p-type) region including a plurality of segments each including an implanted region having a higher dopant density than the n-type (p-type) region; a p-type (n-type) region; and a gain region between the n-type (p-type) region and the p-type (n-type) region, the gain region buried between the n-type (p-type) region and the p-type (n-type) region and the gain region including: an n.sup.+-type region having a higher n-type dopant density than the n-type region; a p.sup.+-type region having a higher p-type dopant density than the p-type region; and a p-n junction between the n.sup.+-type region and the p.sup.+-type region; a readout structure comprising a plurality of first electrodes, wherein at least one of the first electrodes is on each of the segments and the first electrodes on different segments are electrically isolated from one another; each of segments including a first ohmic contact between the implanted region and the at least one of the first electrodes on the implanted region; a second ohmic contact between the p-type (n-type) region and a second electrode; and wherein the p-n junction experiences a reverse bias electric field when an appropriate polarity bias is applied between the first electrodes and the second electrode.

2. The avalanche diode of claim 1, wherein the semiconductor structure consists essentially of silicon.

3. The avalanche diode of claim 1, further comprising: a first surface of the n-type (p-type) region; the p-n junction comprising a first interface between the n.sup.+-type region and the p.sup.+-type region; and a first distance D1 between the first interface and the first surface is in a range of 2-10 micrometers.

4. The avalanche diode of claim 3, wherein the first distance is in a range of 3-6 micrometers.

5. The avalanche diode of claim 1, wherein: the n.sup.+-type region has a first n-type dopant density and the p.sup.+-type region has a first p-type dopant density, and the first n-type dopant density is within 10% of the first p-type dopant density.

6. The avalanche diode of claim 5, wherein the first n-type dopant density and the first p-type dopant density are in a range of 2.6e{circumflex over ( )}16-3.8e{circumflex over ( )}16 dopant atoms per cm.sup.3.

7. The avalanche diode of claim 6, wherein: the n-type region has a second n-type dopant density in a range of 1e{circumflex over ( )}12-1e{circumflex over ( )}14 atoms per cm.sup.3, and the p-type region has a second p-type dopant density in a range of 1e{circumflex over ( )}12-1e{circumflex over ( )}14 atoms per cm.sup.3.

8. The avalanche diode of claim 3, further comprising: a second surface of the p-type (n-type) region on a side of the semiconductor structure opposite the first surface; and a second distance, between the second surface and the first interface, in a range of 20 micrometers to 100 micrometers.

9. The avalanche diode of claim 1, wherein: when the diode experiences depletion, the reverse bias electric field, a first n-type dopant density in the n.sup.+-type region and a second p-type dopant density in the p.sup.+-type region are in a range that achieves gain using impact ionization in the p-n junction without breakdown of the p-n junction; and a second n-type dopant density in the n-type region and a second p-type dopant density in the p-type region are in a range such that: the reverse bias electric field does not induce impact ionization in the n-type region or the p-type region, the second p-type dopant density enables saturation of the drift velocity in the p-type region, and the second n-type dopant density enables saturation of the drift velocity in the n-type region.

10. The avalanche diode of claim 1, wherein: starting at full depletion and as a function of increasing reverse bias voltage across the first electrodes and second electrode, a gain of the avalanche diode increases monotonically until breakdown in the p-n junction; and the gain is characterized as the response of the avalanche diode with the p-n junction divided by the response of the diode having: the p.sup.+-type region replaced with a continuation of the p-type region (having the same thickness as the p.sup.+-type region), and the n.sup.+-type region replaced with a continuation of the n-type region (having the same thickness as the n.sup.+-type region).

11. The avalanche diode of claim 1, wherein: each of the segments has a surface area of 3 by 3 micrometers or greater, or the number density of the segments is up to 10.sup.5 segments per square millimeter.

12. The avalanche diode of claim 1, further comprising: an electrostatic isolation barrier, comprising p-type (n-type) dopants, between adjacent segments, wherein: the electrostatic isolation barriers electrically isolate the first electrodes from each other, and the electrostatic isolation barriers extend to a depth that does not reach the p-n junction.

13. The avalanche diode of claim 7, wherein the barriers comprise a third p-type (n-type) dopant density in a range of 1e{circumflex over ( )}12-1e{circumflex over ( )}14 dopant atoms per cm.sup.3.

14. The avalanche diode of claim 7 further comprising: a first surface of the n-type (p-type) region, an electrostatic isolation barrier, comprising p-type (n-type) dopants, between adjacent segments, wherein: the electrostatic isolation barriers electrically isolate the first electrodes from each other, and the electrostatic isolation barriers extend to a depth that does not reach the p-n junction, and the dopant densities in the semiconductor structure are tuned so that the gain of the diode, as a function of position along a length of the segment, in any direction parallel to the first surface, does not vary by more than +/−10%.

15. The avalanche diode of claim 14, wherein for the p-type (n-type) region comprising a bulk region having a thickness of 50 micrometers or less, the majority of a signal charge, in response to incidence of charged particles or photons on the avalanche diode, is collected on the first electrodes within 500 picoseconds, enabling a repetition rate in excess of 1 GHz.

16. The avalanche diode of claim 13, wherein the implanted regions comprise a fourth n-type (p-type) dopant density in a range of 1e{circumflex over ( )}17-1.e{circumflex over ( )}19 dopant atoms per cm.sup.3.

17. The avalanche diode of claim 1, wherein the avalanche diode does not include a Junction Termination Extension (JTE) structure between the segments.

18. The avalanche diode of claim 1, wherein: the n-type (p-type) region, including the plurality of segments, comprises an n-type (p-type) region, and the p-type (n-type) region comprises a p-type bulk region so that the second ohmic contact is between the p-type (n-type) bulk region and the second electrode.

19. A method of making an avalanche diode, comprising: obtaining or creating a semiconductor structure including: an n-type (p-type) region; a p-type (n-type) region; and a gain region between the n-type region and the p-type region, the gain region buried between the n-type region and the p-type region and the gain region including: an n.sup.+-type region having a higher n-type dopant density than the n-type region; a p.sup.+-type region having a higher p-type dopant density than the p-type region; and a p-n junction between the n.sup.+-type region and the p.sup.+-type region; the surface of the n-type (p-type) region forming a readout structure, comprising: a plurality of segments in the n-type (p-type) region, each of the segments including an implanted region having a higher dopant density than the n-type (p-type) region; generating a plurality of first electrodes, wherein at least one of the first electrodes is on each of the segments and the first electrodes on different segments are electrically isolated from one another; forming a first ohmic contact between each of the implanted regions and the one of the first electrodes on the each of the implanted regions; and forming a second ohmic contact between the p-type (n-type) region and a second electrode, so that the p-n junction is reverse biased by application of an electric field of appropriate polarity between the first electrodes and the second electrode.

20. The method of claim 19, wherein the semiconductor consists essentially of silicon and the first electrodes are DC coupled to the implanted regions.

21. (canceled)

22. The avalanche diode of claim 1 wherein: an electron (hole) is generated in the p-type (n-type) region (comprising a bulk region) in response to incident charged particle(s) or photon(s); the electron (hole), accelerated in the reverse bias electric field applied across the gain region, generates additional electrons (holes) in the gain region through impact ionization in the gain region, and the n-type (p-type) region (including the segments) isolates the first electrodes from electric fields in the gain region so that there is no breakdown between the implanted regions while allowing the additional electrons (holes) to drift from the gain region through the n-type (p-type) region to the first electrodes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0086] Referring now to the drawings in which like reference numbers represent corresponding parts throughout:

[0087] FIG. 1: Conventional LGAD.

[0088] FIG. 2: Schematic of a Deep-Junction LGAD according to one or more examples, illustrating the use of the buried junction to localize the high electric-field region and isolate it from the readout structure.

[0089] FIG. 3: Two-dimensional electric field profile of the Baseline-1 configuration, at a bias voltage of 210V. The units of the axes are micrometers.

[0090] FIG. 4: Gain as a function of bias voltage for the Baseline-1 configuration.

[0091] FIG. 5: Integrated signal charge, summed over all channels, as a function of transverse position, for a pixel separation of 20 μm within the Baseline-1 model.

[0092] FIG. 6: Temporal signal profile as a function of bias voltage for the Baseline-1 configuration.

[0093] FIG. 7. Flowchart illustrating a method of making an avalanche diode.

[0094] Some of the drawings are better understood when provided in color and the specification makes reference to color versions of the drawings. Applicant considers the color versions of the drawings as part of the original disclosure and reserves the right to provide color versions of the drawings in later proceedings.

DETAILED DESCRIPTION OF THE INVENTION

[0095] In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0096] Technical Description

[0097] The present disclosure describes an entirely novel approach to the problem of improving the granularity of LGAD sensors—the Deep Junction (“DJ-LGAD”) LGAD comprising the high electric-field gain region (wherein impact ionization takes place) moved away from the readout structure.

[0098] Example Structure

[0099] FIG. 2 illustrates the LGAD comprises a diode (p-n) junction buried a few micrometers below and away from the upper surface of the LGAD (the upper surface comprising the surface where segmentation is imposed). In the example shown, such positioning of the high electric-field gain region avoids the need for the JTE.

[0100] More specifically, FIG. 2 illustrates an example avalanche diode 200 including a semiconductor structure 202 including an n-type region 204; a p-type region 206; and a gain region 208 buried between the n-type region 204 and the p-type region 206. The gain region includes an n.sup.+-type region 212 having a higher n-type dopant density than the n-type region; a p.sup.+-type region 214 having a higher p-type dopant density than the p-type region; and a p-n junction 210 including an interface 210a between the n.sup.+-type region and the p.sup.+-type region.

[0101] The n-type region 204 includes a plurality of segments 218, each of the segments including a first surface 216 of the n-type region 204 and the semiconductor structure.

[0102] FIG. 2 further illustrates the avalanche diode as including a readout structure 222 comprising a plurality of first electrodes 224, wherein at least one of the first electrodes is on each of the segments and the first electrodes on different segments are electrically isolated from one another. A second electrode 226 is deposited on a second surface 228 of the semiconductor structure/p-type region and an ohmic contact 230 is formed between the p-type region and the second electrode. The p-n junction is reverse biased by application of an electric field between the first electrodes in the readout structure and the second electrode. As illustrated in FIG. 2, each of the segments include implanted regions 232 having a higher dopant density than the n-type region 204. The implanted regions 232 form an ohmic contact with the first electrodes. Also shown in FIG. 2 are electrostatic isolation barriers 234 (e.g., p-type wells) electrically isolating the segments.

[0103] FIG. 2 illustrates the LGAD as comprising a gain layer including both the n.sup.+ region (dark blue section) and the p.sup.+ region (dark red section), rather than just a dark red section. In other words, the gain layer comprises the full p-n junction, rather than just the p.sup.+ doped area. A key benefit of burying the entire junction, rather than just the highly-doped p.sup.+ region, is that application of a reverse bias (creating a depletion zone) establishes an electric field in the region of the junction that is similar to that of a parallel-plate capacitor. Specifically, application of the reverse bias voltage creates two planes comprising near equal (but opposite sign) high charge density, so that the electric field in the region of the junction is sufficiently high to induce the limited and controlled impact ionization that is characteristic of LGADs. The electric fields are much lower outside the highly doped junction region, however, thereby avoiding the need to provide isolation between the readout segmentation and the junction.

[0104] Example Characterization

[0105] The structure of FIG. 2 was simulated with version K_2015.06-SP2 of the Sentaurus Device simulation package from the Synopsys Corporation. A challenge of designing a workable DJ-LGAD is to determine the doping profiles that:

[0106] (1) produce the right amount of impact ionization in the gain region, allowing for gain without breakdown; and

[0107] (2) also permit the electric field in all other regions of the bulk (including the “N isolation layer” between the junction and the readout structure) to be (i) high enough to saturate the drift velocity but (ii) low enough so as to not induce additional, uncontrolled impact ionization that leads to breakdown between segments.

[0108] Table 1 illustrates a sample doping profile (“Baseline-1” configuration) that achieves these conditions (1) and (2), while maintaining electric fields at the readout surface low enough to allow for conventional segmentation techniques and avoid the use of a JTE. All further results presented herein are for the simulated behavior of this Baseline-1 configuration.

TABLE-US-00001 TABLE 1 Doping profile parameters for the Baseline-1 version of the DJ-LGAD. The dopant densities or levels expressed herein in scientific notation MeN per centimeter cube (cm.sup.3), where m is a real number and n is an integer, are equivalent to standard notation m × 10.sup.n. Element Doping Level Extent in Depth N isolation layer Constant doping of density From 0 μm (surface) to 3e12 N/cm{circumflex over ( )}3 beginning of N.sup.++ “gain plate” layer N.sup.++ gain plate (upper half of Gaussian doping, peak of Peak at 4 μm, Gaussian width gain layer) 3.0e16 N/cm{circumflex over ( )}3 of 0.17 μm P.sup.++ gain plate (lower half of Gaussian doping, peak of Peak at 5.5 μm, Gaussian gain layer) 3.0e16 N/cm{circumflex over ( )}3 width of 0.17 μm P drift region Constant doping of density End of P.sup.++ “gain plate” layer 3.0e12 N/cm{circumflex over ( )}3 to 50 μm P stop Constant doping of density 1 μm deep, 1 μ wide 1.0e13 N/cm{circumflex over ( )}3 N.sup.++ implant Constant doping of density At surface 1.0e19 N/cm{circumflex over ( )}3 Gain layer doping tolerance Effective operation between (N.sup.++ and P.sup.++ varied together) 2.9e{circumflex over ( )}16 and 3.5e{circumflex over ( )}16

[0109] FIG. 3 shows the resulting two-dimensional electric field profile, as a function of depth into the Baseline-1 detector and of a lateral coordinate parallel to the surface of the device, fora bias voltage of 210V. For bias voltages above 100 Volts, the electric field in the p-type drift region and the n-type isolation region is relatively insensitive to the applied voltage, leading to stable charge collection properties. The impact ionization process, which depends upon electric field in the gain region, is also well controlled, leading to the smooth dependence of gain upon bias voltage shown in FIG. 4.

[0110] FIG. 5 shows the gain variation as a function of lateral position that results from the electric field depicted in FIG. 3; uniformity at the +/−4% level is observed. Gain is defined by the collected charge in the LGAD over the collected charge in a same thickness silicon sensor without the gain layer structure.

[0111] FIG. 6 shows the temporal signal profile as a function of applied bias voltage (obtained using the simulation). A sharp rising edge, conducive to a fast timing measurement, is observed for all bias voltages, with a slew-rate that grows monotonically with bias voltage. Consistent with the saturation drift velocity (approximately 100 μm per nanoseconds) of carriers in silicon, the majority of the charge within this 50 μm device is collected within 500 picoseconds, suggesting an achievable device repetition rate in excess of 1 GHz.

[0112] Process Steps

[0113] FIG. 7 is a flowchart illustrating a method of making an avalanche diode (referring also to FIG. 2).

[0114] Block 700 represents obtaining or creating a semiconductor structure (e.g., epitaxial layers) on a substrate. In one or more examples, the semiconductor structure is a silicon semiconductor structure and the substrate is a silicon substrate (or the semiconductor structure and the substrate may comprise or consist essentially of silicon). In one example, the semiconductor structure includes a bulk p-type region; a gain region including a p-n junction on or above the bulk p-type region; and an n-type region (isolation region) on or above the gain region (n-side up configuration). In another example, the semiconductor structure includes a bulk n-type region; a gain region including a p-n junction on or above the bulk n-type region; and the p-type region (isolation region) on or above the gain region (p-side up configuration). The gain region includes an n.sup.+-type region having a higher n-type dopant density than the n-type region; a p.sup.+-type region having a higher p-type dopant density than the p-type region; and the p-n junction between the n.sup.+-type region and the p.sup.+-type region. The p.sup.+-type region typically forms a junction interface in physical contact with the n.sup.+-type region. Example p-type dopants include, but are not limited to, boron, gallium, aluminum, and indium. Example n-type dopants include, but are not limited to, phosphorus, arsenic, antimony, bismuth and lithium.

[0115] Block 702 represents forming a readout structure so that the surface of the n-type (p-type) region forms the readout structure. The step comprises defining a plurality of segments in the n-type region or the p-type region depending on the configuration (n-side up or p-side up).

[0116] Block 704 represents creating or generating (e.g., depositing) a plurality of first electrodes forming an ohmic contact with the readout structure and a second electrode forming an ohmic contact with the p-type (n-type) region. At least one of the first electrodes is on each of the segments and the first electrodes on different segments are electrically isolated from one another. Established segmentation schemes for conventional (non-LGAD) silicon diode sensors may also be used. The step further comprises forming a first ohmic contact between the implanted regions and the first electrodes, and a second ohmic contact between the bulk p-type region and the bulk n-type region and a second electrode, so that the p-n junction is reverse biased by application of an electric field of appropriate polarity between the first electrodes and the second electrode. The second ohmic contact is typically formed on a second surface of the semiconductor structure opposite the first surface.

[0117] Block 706 represents the end result, an avalanche diode. The avalanche diode can be used in many applications, including but not limited to, as a pixel sensor (e.g., at the large hadron collider (LHC) or proposed Electron-Ion Collider (EIC)) with fast timing capabilities.

[0118] The avalanche diode can be embodied in many ways including, but not limited to, the following (referring also to FIG. 2).

[0119] 1. An avalanche diode 200, comprising a semiconductor structure 202 including a first region 204a doped with a first polarity type dopant (n-type or p-type); a second region 206a doped with a second polarity type dopant (n-type or p-type and opposite polarity to the first polarity type dopant); and a gain region 208 between the first region and the second region. The first region 204a includes a plurality of segments 218 each including implanted regions 232 having a higher dopant density than the first region. In a first possibility, the first region 204a comprises an n-type region 204 and the second region 206a comprises a p-type region 206. In a second possibility, the first region comprises a p-type region and the second region comprises an n-type region. These two possibilities are expressed herein as the first region 204a comprising an n-type (p-type) region and the second region comprising a p-type (n-type) region 206 which define the second region as being p-type when the first region is n-type and the second region as being n-type when the first region is p-type.

[0120] The gain region 208 is buried between the n-type (p-type) region 204a and the p-type (n-type) region 206a and the gain region 208 includes: [0121] an n.sup.+-type region 212 having a higher n-type dopant density than the n-type region 204; [0122] a p.sup.+-type region 214 having a higher p-type dopant density than the p-type region 206; and [0123] a p-n junction 210 between the n.sup.+-type region 212 and the p.sup.+-type region 214;

[0124] a readout structure 222 comprising a plurality of first electrodes 224, wherein at least one of the first electrodes is on each of the segments 218 and the first electrodes on different segments are electrically isolated from one another;

[0125] a first ohmic contact between the implanted region and the first electrode 224 on the implanted region (e.g., a first ohmic contact between each of the implanted regions and the one of the first electrodes on the each of the implanted regions);

[0126] a second ohmic contact 230 between the p-type (n-type) region and a second electrode 226; and

[0127] wherein the p-n junction 210 experiences a reverse bias electric field when an appropriate polarity bias is applied between the first electrodes 224 and the second electrode 226.

[0128] 2. The avalanche diode of example 1, wherein e semiconductor structure consists essentially of silicon.

[0129] 3. The avalanche diode of example 1 or example 2, further comprising:

[0130] a first surface 216 of the n-type (p-type) region 204a;

[0131] the p-n junction 210 comprising a first interface 210a between the n.sup.+-type region and the p.sup.+-type region; and

[0132] a first distance D1 between the first interface 210a and the first surface 216, wherein the first distance D1 is in a range of 2-10 micrometers (e.g., 2 micrometers≤D1≤10 micrometers), as illustrated in FIG. 2.

[0133] 4. The avalanche diode of example 3, wherein the first distance D1 is in a range of 3-6 micrometers (e.g., 3 micrometers≤D1≤6 micrometers).

[0134] 5. The avalanche diode of any of the preceding examples, wherein:

[0135] the n.sup.+-type region 212 has a first n-type dopant density and the p.sup.+-type region 214 has a first p-type dopant density, and

[0136] the first n-type dopant density is within 10% (e.g., within 5%, or within 1%) of the first p-type dopant density, or the same as the first p-type dopant density.

[0137] 6. The avalanche diode of example 5, wherein the first n-type dopant density N.sub.D1 and the first p-type dopant density N.sub.A1 are in a range of 2.6e{circumflex over ( )}16-3.8e{circumflex over ( )}16 dopant atoms per cm.sup.3 (e.g., of 2.6e{circumflex over ( )}16≤N.sub.D1, N.sub.A1≤3.8e{circumflex over ( )}16).

[0138] 7. The avalanche diode of any of the preceding examples, wherein:

[0139] the n-type region 204 has a second n-type dopant density N.sub.D2 in a range of 1e{circumflex over ( )}12-1e{circumflex over ( )}14 atoms per cm.sup.3 (e.g., of 1e{circumflex over ( )}12≤N.sub.D2≤1e{circumflex over ( )}14), and

[0140] the p-type region 206 has a second p-type dopant density N.sub.A2 in a range of 1e{circumflex over ( )}12-1e{circumflex over ( )}14 atoms per cm.sup.3 (e.g., of 1e{circumflex over ( )}12≤N.sub.A2≤1e{circumflex over ( )}14).

[0141] 8. The avalanche diode of any of the preceding examples, further comprising:

[0142] a second surface 228 of the p-type (n-type) region on a side of the semiconductor structure opposite the first surface 216; and

[0143] a second distance D2 (as illustrated in FIG. 2), between the second surface 228 and the first interface 210a, in a range of 20 micrometers to 100 micrometers (e.g., 20 micrometers≤D2≤100 micrometers).

[0144] 9. The avalanche diode of any of the preceding examples, wherein:

[0145] when the avalanche diode 200 experiences the reverse bias electric field, a first n-type dopant density in the n.sup.+-type region 212 and a second p-type dopant density in the p.sup.+-type region 214 are in a range that achieves gain using impact ionization in the p-n junction 210 without breakdown of the p-n junction 210; and

[0146] a second n-type dopant density in the n-type region 204 and a second p-type dopant density in the p-type region 206 are in a range such that: [0147] the reverse bias electric field does not induce impact ionization in the n-type region 204 or the p-type region 206, [0148] the second p-type dopant density enables saturation of the drift velocity in the p-type region 206, and [0149] the second n-type dopant density enables saturation of the drift velocity in the n-type region 204.

[0150] 10. The avalanche diode of any of the preceding examples, wherein:

[0151] starting at full depletion and as a function of increasing reverse bias voltage across the first electrodes 224 and second electrode 226, a gain of the diode increases monotonically (e.g., always upwards) until breakdown in the p-n junction 210; and

[0152] the gain is characterized as the response of the diode 200 with the p-n junction 210 divided by the response of the diode having:

[0153] the p.sup.+-type region 214 replaced with a continuation of the p-type region 206 (having the same thickness as the p.sup.+-type region) and

[0154] the n.sup.+-type region 212 replaced with a continuation of the n-type region 204 (having the same thickness as the n.sup.+-type region).

[0155] 11. The avalanche diode of any of the preceding examples, wherein:

[0156] each of the segments 218 has a surface area A of 3 by 3 micrometers or greater, or

[0157] the number density of the segments is up to 10.sup.5 segments per square millimeter.

[0158] 12. The avalanche diode of any of the preceding examples, further comprising:

[0159] an electrostatic isolation barrier 234, comprising p-type (n-type) dopants, between adjacent segments, wherein:

[0160] the barriers electrically isolate the first electrodes 224 from each other, and

[0161] the barriers extend to a depth D3 that does not reach the p-n junction 210.

[0162] 13. The avalanche diode of example 12, wherein the barriers 234 comprise a third p-type (n-type) dopant density N.sub.3 in a range of 1e{circumflex over ( )}12-1e{circumflex over ( )}14 dopant atoms per cm.sup.3 (e.g., 1e{circumflex over ( )}12≤N3≤1e{circumflex over ( )}14).

[0163] 14. The avalanche diode of examples 6, 7 and 12:

[0164] wherein the dopant densities in the semiconductor structure 202 are tuned so that the gain of the diode 200, as a function of position along a length L of the segment, in any direction parallel to the first surface 216, does not vary by more than +/−10%.

[0165] 15. The avalanche diode of example 14, wherein for the p-type (n-type) region comprising a bulk region having a thickness D4 of 50 micrometers or less, the majority (e.g., greater than 90%) of the signal charge is collected within 500 picoseconds, enabling a repetition rate in excess of 1 GHz.

[0166] 16. The avalanche diode of any of the preceding examples, wherein the implanted regions 232 comprise a fourth n-type (p-type) dopant density N in a range of 1e{circumflex over ( )}17-1e{circumflex over ( )}19 dopant atoms per cm.sup.3 (e.g., 1e{circumflex over ( )}17≤N.sub.4≤1e{circumflex over ( )}18).

[0167] 17. The avalanche diode 200 of any of the preceding examples, wherein the diode does not include a Junction Termination Extension (JTE) structure between the segments.

[0168] 18. The avalanche diode of any of the preceding examples, wherein:

[0169] the n-type (p-type) region including a plurality of segments 218 comprises an n-type region 204, and the p-type (n-type) region comprises a p-type bulk region 206 so that the second ohmic contact 230 is between the p-type bulk region 206 and the second electrode 226, as illustrated in FIG. 2.

[0170] The avalanche diode of any of the preceding examples, wherein:

[0171] the n-type (p-type) region including a plurality of segments comprises a p-type region (i.e., the n-type region 204 in FIG. 2 is a p-type region), and the p-type (n-type) region comprises a n-type hulk region p-type region 206 is an n-type region) so that the second ohmic contact is between the n-type bulk region and the second electrode.

[0172] 20. A method of making an avalanche diode, comprising:

[0173] obtaining or creating a semiconductor structure including: [0174] an n-type (p-type) region; [0175] a p-type (n-type) region; and [0176] a gain region between the n-type region and the p-type region, the gain region buried between the n-type region and the p-type region and the gain region including: [0177] an n.sup.+-type region having a higher n-type dopant density than the n-type region; [0178] a p.sup.+-type region having a higher p-type dopant density than the p-type region; and [0179] a p-n junction between the n.sup.+-type region and the p.sup.+-type: region; [0180] the surface of the n-type (p-type) region forming a readout structure, comprising: [0181] a plurality of segments in the n-type (p-type) region, each of the segments including implanted regions having a higher dopant density than the n-type (p-type) region;

[0182] generating a plurality of first electrodes, wherein at least one of the first electrodes is on each of the segments and the first electrodes on different segments are electrically isolated from one another;

[0183] forming a first ohmic contact between each of the implanted regions and the one of the first electrodes on the each of the implanted regions; and

[0184] forming a second ohmic contact between the p-type (n-type) region and a second electrode, so that the p-n junction is reverse biased by application of an electric field of appropriate polarity between the first electrodes and the second electrode.

[0185] 21. The method of example 20, wherein the semiconductor consists essentially of silicon.

[0186] 22. The method of example 20 or 21, wherein the first electrodes are DC coupled to the implanted regions.

[0187] 23. The method or device of any of the preceding examples wherein:

[0188] an electron (hole) is generated in the p-type (n-type) region 206a (comprising a bulk region) in response to incident charged particle(s) or photon(s), including X-rays;

[0189] the electron (hole), accelerated in the reverse bias electric field applied across the gain region 208, generates additional electrons (holes) in the gain region through impact ionization in the gain region, and

[0190] the n-type (p-type) region 204a (including the segments 218) isolates the first electrodes 224 from electric fields in the gain region so that there is no breakdown between the implanted regions 232 while allowing the additional electrons (holes) to drift from the gain region 208 through the n-type (p-type) region 204a to the first electrodes 224.

[0191] 24. The method or device of any of the preceding examples, wherein the readout structure comprises the segments and the first electrodes on the segments, so that when the readout structure is electrically connected in or to a readout circuit, the readout circuit measures a quantity of the charged particles (electrons or holes) collected on the first electrodes in response to charged particle(s) or photon(s) (including X-rays) incident on the avalanche diode.

[0192] Advantages and Improvements

[0193] As described above, conventional LGADs are biased with high electric fields required to induce the impact ionization process, leading to breakdown between the separated n-p junctions that are used to simultaneously deplete the sensors and establish the readout segmentation. As a result, working LGAD devices have included a Junction Termination Extension (JTE) that provides electrostatic isolation between neighboring implants, but at the cost of introducing a dead region between the sensor segments that is insensitive to the deposited charge from an incident particle. The width of this dead region is 50 μm or more, making conventional LGAD sensors inefficient for granularity scales much below 1 mm. The following devices have been proposed to circumvent the JTE limit.

[0194] (1) AC-coupled (“AC-LGAD”) LGADs that eliminate the need for the JTE by making use of a completely planar (non-segmented) junction structure, while establishing the granularity entirely through the electrode structure, which is AC-coupled to the planar device through a thin layer of insulator. Since charge is not collected directly by the electrodes, there is a point-spread function that relates the signal location to the pad (electrode) response that is a property of the effective AC network formed by the highly doped gain layer just below the insulating layer and the electrode structure. The AC coupling also leads to a signal that is zero when integrated over all time, leading to a recovery period for which the polarity of collected charge is of opposite polarity to that of the signal pulse, potentially compromising the repetition rate of the device.

[0195] (2) Inverse (“ILGAD”) LGADs also eliminate the need for the JTE by making use of a planar junction structure, In this case, the electrode structure is placed on the side of the device opposite the junction. However, prototypes with appealing signal characteristics have yet to be achieved. In addition, the manufacture of these devices requires processing on both sides of the sensor, which is significantly more difficult than the single-sided processes used for conventional, AC, and DJ LGADs.

[0196] (3) Trench-isolated (“TI-LGAD”) LGADs attempt to replace the JTE with a physical trench etched around the edge of the detector segment, which is then filled with insulator. This structure might be used to reduce the dead area between segments to as little as 5 μm. However, much work remains to be done to show that this approach will produce a stable sensor, and to see how small the dead region can be made.

[0197] Therefore, these approaches (1)-(3) for increasing LGAD granularity make use of more complex, and less proven segmentation techniques. Exemplary device embodiments described herein, on the other hand, include the diode junction gain layer buried below a lightly-doped isolation layer, enabling the use of conventional segmentation techniques to achieve high granularity. This allows for the removal of constraints on the granularity of LGADs while maintaining their attractive properties of internal gain, timing resolution and repetition rate.

CONCLUSION

[0198] This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.