Method for driving electro-optic displays

Abstract

A large area display having multiple sub-units arranged in rows and columns and a method of driving the multiple sub-units as a single display are provided. Each sub-unit has an associated pixel row driver and pixel column driver. The large area display may also include a chip select means that provides a separate chip select signal to the pixel row driver of each row of sub-units, so that in the row of sub-units for which the associated row driver has received the chip select signal, only the rows of pixels within a single row of sub-units are supplied data at any one time. Column data and delayed Gate Start Pulse signals are fed to the pixel column drivers in each column of sub-units such that the appropriate column data values are supplied to the associated pixel column drivers.

Claims

1. A method of driving a large area display comprising a plurality of sub-units arranged in a plurality of rows and columns of sub-units, each sub-unit having an associated pixel row driver and an associated pixel column driver, the sub-units within each column of subunits being interconnected such that the associated pixel column drivers drive the pixel column electrodes of all the sub-units within the column of subunits such that the plurality of sub-units of the large area display are driven as a single display, the method comprising: sequentially providing a separate chip select signal to each pixel row driver associated with a row of sub-units, sequentially supplying data to the drivers of each row of pixels in the row of sub-units for which the associated row driver has received the chip select signal so that only the drivers of the rows of pixels within a single row of sub-units are supplied data at any one time, supplying column data to a first shift register of a first column driver as a series of column data values under the control of a Gate Start Pulse signal, and supplying the column data to a second shift register of a second column driver as a series of column data values under the control of a delayed Gate Start Pulse signal.

2. A method according to claim 1 wherein the Gate Start Pulse signals are provided to a programmable logic device which generates the delayed Gate Start Pulse signal at a time appropriate for the second column driver to begin receiving data.

3. A method according to claim 2 wherein the column data are supplied to the first and second column drivers as a series of column data extending across all the pixel columns in all the sub-units, and the delayed Gate Start Pulse signal causes bits 1 to N of the series of data (where N is an integer equal to the number of columns in the sub-units of the first column) to be placed in the first shift register of the first column driver, and bits (N+1 ) to 2N to be placed in the second shift register of the second column driver.

4. A large area display comprising: a plurality of sub-units arranged in a plurality of rows and columns of sub-units, each sub-unit having an associated pixel row driver and an associated pixel column driver, the sub-units within each column of sub-units being interconnected such that the associated pixel column driver drives the pixel column electrodes of all the sub-units within the column of sub-units; chip select means for providing a separate chip select signal to the pixel row driver of each row of sub-units, so that in the row of sub-units for which the associated pixel row driver has received the chip select signal, only the rows of pixels within a single row of sub-units is supplied data at any one time; column data supply means for supplying column data to the pixel column drivers as a series of column data values; means for feeding, for each pixel column scanned, delayed Gate Start Pulse signals to the pixel column drivers in each column of sub-units after the first so that the pixel column drivers in each column of sub-units after the first receive the delayed Gate Start Pulse signals and such that the appropriate column data values are supplied to the associated pixel column drivers; and wherein the plurality of sub-units of the large area display are driven as a single display.

5. A large area display according to claim 4 wherein the means for feeding delayed Gate Start Pulse signals comprises means for generating Gate Start Pulse and Gate Clock signals, the Gate Start Pulse signal indicating the start of a new row of data and the Gate Clock signal indicating that a new column data value is to be supplied, and a programmable logic device which receives the Gate Start Pulse and Gate Clock signals and generates the delayed Gate Start Pulse signals.

6. A large area display according to claim 5 wherein the column data supply means is arranged to supply the column data to the column drivers as a series of column data extending across all the columns in all the sub-units of a row of sub-units, and the means for feeding delayed Gate Start Pulse signals are arranged to cause bits 1 to N of the series of data (where N is a integer equal to the number of columns in the sub-units of the first column) to be placed in shift registers of the column drivers in the first column of sub-units, and bits (N+1 ) to 2N to be placed in shift registers of the column drivers in the second column of sub-units.

7. A large area display according to claim 4 further comprising optical means arranged along an edge between adjacent sub-units and is configured to reduce an apparent width of a gap between the sub-units.

8. A large area display according to claim 7 wherein the optical means comprises a lens molded into a viewing surface of a sub-unit.

9. A large area display according to claim 4 further comprising a layer of an electro-optic medium applied over the sub-units.

10. A large area display according to claim 9, wherein the electro-optic medium is at least one of a rotating bichromal member or electrochromic electro-optic medium.

11. A large area display according to claim 9, wherein the electrophoretic medium comprises a plurality of electrically charged particles disposed in a fluid, the plurality of electrically charged particles being capable of moving through the fluid under the influence of an electric field.

12. A large area display according to claim 11 wherein the electrically charged particles and the fluid are confined within a plurality of capsules or microcells.

13. A large area display according to claim 11 wherein the electrically charged particles and the fluid are present as a plurality of discrete droplets surrounded by a continuous phase comprising a polymeric material.

14. An electro-optic display according to claim 11 wherein the fluid is gaseous.

Description

BRIEF DESCRIPTION OF THE DRAWING

(1) The sole FIGURE of the accompanying drawing is a schematic top plan view of a large area display of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(2) As already noted, the accompanying drawing is a schematic top plan view of a large area display of the present invention. This large area display is formed from six sub-units arranged in three rows and two columns, the individual sub-units being denoted R[ow]1 C[olumn]1 etc. (The terms rows and columns are used herein not in the layman's sense of referring to horizontal and vertical lines but in the conventional manner by those skilled in the technology of active matrix electro-optic displays, i.e., row refers to a line of pixels or sub-units which are selected simultaneously for data transfer to source drivers and column refers to a group of pixels interconnected by a column electrode or groups of sub-units that share the same Gate Start Pulse signal. Thus, in the FIGURE, the rows of both pixels and sub-units are vertical as illustrated, while the columns are horizontal.) For purposes of illustration, it will be assumed that the individual sub-units have a resolution of 800 rows by 600 columns, so that the entire large area display shown in the FIGURE is an electro-optic display having a resolution of 2400 rows by 1200 columns. Although the FIGURE, for ease of illustration, shows substantial gaps between adjacent sub-units, it will be appreciated that in practice every attempt should be made to reduce these gaps to the minimum possible size so that overall display does appear to the observer as a single continuous display with no visible breaks within the active area of the display. Methods for reducing the visual effect of breaks between the sub-units are described below.

(3) Each sub-unit has an associated row driver 1 and column driver 2. (This is convenient and conventional but not strictly necessary. A single row or column driver of sufficient capacity could operate multiple adjacent physical displays, or multiple low capacity low or column drivers could be used in a single sub-unit. In such cases, it may be necessary to distinguish drivable sub-units from physical sub-units; this invention is basically concerned with the former.) Each row driver 1 receives a chip select signal (designated CS) from the display controller (not shown). However, each row of sub-units receives a different chip select signal, three signals designated CS0, CS1 and CS2 being supplied to the sub-units in rows 1, 2 and 3 respectively. The three signals CS0, CS1 and CS2 are timed such that the 800 rows in row 1 are scanned, followed by the 800 rows in row 2 and finally the 800 rows in row 3. In effect, the three chip select signals CS0, CS1 and CS2 enable the 2400 lines of the large area display to be scanned exactly as if it were a single conventional display.

(4) The handling of the input signals to the column drivers 2 is somewhat more complicated. As already mentioned, in a conventional electro-optic display, the column data (defining what voltages to be asserted on the various column electrodes) are supplied to the column drivers as a linear series of digital column data values under the control of a Gate Start Pulse (GSP) signal and a Gate Clock (GCLK) signal, the GSP signal indicating the start of a new row of data and the GCLK signal indicating that a new column data value is supplied. From the shift register, the data is latched and fed to digital/analogue converters which supply the appropriate voltages to each column electrode in a manner which is entirely conventional and need not be described in detail herein. In principle, one could load the column drivers for both columns of sub-units of the large area display shown in the FIGURE by taking the output from the shift registers of the column drivers of the first column of sub-units and sending them to the shift registers of the second column of sub-units. However, in practice, most commercial column drivers and/or connector interfaces do not provide an appropriate output from the column driver shift register. Accordingly, it is necessary for the large area display shown in the FIGURE to be provided with different circuitry for ensuring that the column drivers for the second column of sub-units (hereinafter the second column drivers) to be provided with appropriate inputs to their shift registers.

(5) For this purpose, the large area display is provided with a programmable logic device (CPLD), which receives the GSP and GCLK signals from the display controller and generates a delayed GSP (dGSP) signal at a time appropriate from the second column drivers to begin receiving data into their shift registers, this dGSP signal (denoted GSP+delay in the FIGURE) being fed to the inputs of the second column drivers which would normally receive the GSP signal. As already noted, the column drivers are designed so that, upon receipt of an appropriate transition in the GSP signal, the column drivers place data into a shift register at a rate of one bit per Gate Clock (GCLK) pulse. In the case of the large area display shown in the FIGURE, upon receipt of the appropriate transition in the GSP signal, the column drivers for the first column of sub-units (the first column drivers) proceed to place 600 successive bits of data from the display controller into their shift registers at the rate of one bite per GCLK signal. The CPLD, upon receipt of the appropriate transition in the GSP signal, starts to count GCLK pulses, but does not generate any change in the level of the dGSP signal as yet. Note that since the second column drivers have not as yet experienced any transition in the dGSP signal, none of the first 600 bits of data have been placed in the shift registers of these second column drivers.

(6) After the receipt of the 600th bit of column data, the shift registers of the first column drivers are full, and subsequent bits are ignored by the first column drivers. However, when the 600th GCLK pulse is received, the CPLD generates an appropriate transition in the dGSP signal, so that the second column drivers begin to place incoming bits of data from the display controller into their shift registers. The second column drivers proceed to accumulate 600 bits of data in this manner. Thus, at the end of the entire process, the shift registers of the first column drivers contain bits 1-600 from the display controller, while the shift registers of the second column drivers contain bits 601-1200.In effect, the entire large area display appears to the display controller as a single 1200 pixel wide display.

(7) From the foregoing, it will be seen that the present invention simplifies the hardware design of a large area display and greatly simplifies the software required to operate the display since the driving electronics can treat the system of six sub-units as one display with three source drivers and two column drivers.

(8) It will be apparent to those skilled in the art that numerous changes and modifications can be made in the specific embodiments of the invention described above without departing from the scope of the invention. For example, the large area display shown in the FIGURE could readily be adapted to accommodate additional columns of sub-units by arranging the CPLD to generate a plurality of dGSP signals at appropriate intervals, with the first dGSP signal being fed to the second column drivers, the second dGSP signal to the third column drivers, the third dGSP signal to the fourth column drivers etc., the various dGSP signals being timed so that (again assuming each display is 600 columns wide), at the end of each complete line, the shift registers of the first column drivers contain bits 1-600 from the display controller, the shift registers of the second column drivers contain bits 601-1200, the shift registers of the third column drivers contain bits 1201-1800, the shift registers of the fourth column drivers contain bits 1801-2400, etc.

(9) The specific embodiment of the invention shown in the FIGURE is limited to a number of rows of sub-units equal to the number of chip select (CS) signals (three in the specific embodiment discussed above) available from the display controller. However, this limitation can be overcome by interposing between the display controller and the CS inputs of the various row controllers a row selection circuit which receives the RESET, CS0, CS1 and CS2 signals from the display controller (the RESET signal being a signal which indicates that the row controllers should reset to an initial state ready to begin a complete new scan), and, as the display controller repeatedly cycles through the CS0, CS1 and CS2 signals, generates appropriate CS signals for more than three rows of sub-units. For example, in a display with nine rows of sub-units, the row selection circuit might operate as follows (where the successive rows of the table below are assumed to follow each other at regular intervals, and CSRn indicates a signal applied to the CS input of row controllers in row n of the sub-units):

(10) TABLE-US-00001 Signal from Output from row display controller selection circuit CS0 CSR1 CS1 CSR2 CS2 CSR3 CS0 CSR4 CS1 CSR5 CS2 CSR6 CS0 CSR7 CS1 CSR8 CS2 CSR9 (Cycle repeats)

(11) In effect, and again assuming two columns of 800600 pixel sub-units, what appears to the display controller to be the writing of three successive 16001800 images is in reality the writing of a single 16005400 image.

(12) As noted above, one of the inherent problems with a large area display composed of a plurality of sub-units is concealing from a viewer, as far as possible, the junctions between sub-units, since customer acceptance of such displays is very adversely affected if viewers can see a pattern of non-switching areas between the sub-units. In many cases, it is not possible to extend the electro-optic material to the extreme edges of the sub-units since many types of sub-unit require some type of edge seal either to hold an electro-optic material in position or to prevent the entry of moisture and other environmental contaminants which may adversely affect the performance of the sub-unit.

(13) Methods for concealing the junctions between sub-units may be divided into optical methods and physical methods. The term optical methods refers to methods in which the join is physically present but the optical properties of the display are arranged to wholly or partially hide the junction area from a viewer. For example, a peripheral portion of one or both sub-units along the junction may be modified so the viewer sees an image of the peripheral portion which is wider than the peripheral portion itself, so that the image covers at least part of the junction area, thus hiding the non-switching junction area. Appropriate forms of lens for effecting such widening of the image are well known, and are used for example in lenticular displays to enable an image of a series of narrow spaced strips to form a continuous image for a viewer. To provide the necessary lens without major expense, it is generally advantageous to modify the form of the polymeric protective layer which will typically be present on the viewing surface of a display; such polymeric protective layers are often formed of thermoplastics (for example, polyethylene terephthalate), and can readily be embossed or thermally formed to provide the necessary lens. Since the effect of the lens is to create an image of certain pixels wider than the pixels themselves, some distortion of the image may be visible at the junction, and to avoid such distortion it may be desirable to make pixel in the peripheral area smaller in one dimensions than other pixels in the display, such that the reduced size pixels appear full sized in the image produced by the lens.

(14) The term physical methods refers to methods in which the structure of the sub-units is arranged so as to produce a reduced junction area between adjacent pixels. In one important physical method, a flexible electro-optic medium is used, and this flexible medium is carried over the edge of the sub-unit in the junction area; in many cases, it will be necessary or desirable to provide a curved edge on the sub-unit to avoid damage to the electro-optic medium. Any necessary edge seal for the electro-optic medium can then be provided on a side surface of the sub-unit at a location spaced from the viewing surface of the large area display where the edge seal is hidden by the overlying electro-optic medium. If the electro-optic medium is carried over the edges of both sub-units in the junction area in this manner, the non-switching area can be reduced to a negligible width and hence made virtually invisible to a view of the large area display.

(15) In view of these numerous changes and modifications, the whole of the foregoing description is to be interpreted in an illustrative and not in a limitative sense.