Electronic memory device and test method of such a device

Abstract

The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

Claims

1. A method for testing an electronic memory device, the electronic memory device including: a memory matrix organized in rows and columns, the memory matrix having memory cells, wherein the cells of one row are forming one or more memory words; an address decoder with address input lines for selecting a row according to a particular address given on the address input lines, the address defined by a fixed number of bits; and read/write lines for reading/writing at least cine word of a row selected by the particular address, the address decoder including additional address mask input lines, each address mask input line assigned to a respective address input line, herein an address mask input line in an activated state has an effect of ignoring the assigned address input line; the method comprising: testing a particular bit of the address other than a lowest bit of the address, the testing the particular bit including: A) erasing the memory matrix by putting all address mask input lines into the activated state; B) putting all the address mask input lines in the activated state except the particular bit of the assigned address mask input line to ignore all bits of the address except the particular bit to be tested; C) setting the particular bit of the address to 0; D) performing a write operation with a dedicated word that is the same for different selected lines; E) reading at least a first row 0 and a highest column; F) comparing read values of the first row 0 and the highest column with a pattern defined by the written dedicated word and an initial value; and G) in case the comparing in step F) discloses a difference, mark the electronic memory device as defective.

2. The method according to claim 1, wherein each step A) to G) is carried out for all successive particular bits of the address.

3. The method according to claim 1, wherein step E) and F) are performed by reading of the memory matrix row by row.

4. The method according to claim 1, further comprising before step E): D) setting the particular bit of the address to 1; D) performing a write operation with an inverse of the dedicated word for other selected lines.

5. The method according to claim 1, wherein the initial value after an erase operation is 1.

6. An electronic memory device comprising: a memory matrix organized in rows and columns, the memory matrix having memory cells, wherein the cells of one row are forming one or more memory words; an address decoder with address input lines for selecting a row according to a particular address given on the address input lines; and read/write lines for reading/writing at least one word of a row selected by the particular address, wherein erasing a row of the memory matrix has an effect that all cells of said row are set to a defined value, the address decoder includes additional address mask input lines, each address mask input line being assigned to a respective address input line, wherein an address mask input line in an activated state has an effect of ignoring the assigned address input line for selecting at least one row, and the address decoder is configured so that, when a particular bit of the address other than a lowest bit of the address is tested, the address mask input lines are put into the activated state to erase the memory matrix, and all the address mask input lines are put in the activated state except the particular bit of the assigned address mask input line to ignore all bits of the address except the particular bit to be tested.

7. The electronic memory device according to claim 6, wherein the memory matrix is a non-volatile memory matrix.

8. The electronic memory device according to claim 6, wherein a plurality of address mask input lines in the activated state are having an effect of ignoring the assigned address input lines for selecting rows.

9. The electronic memory device according to claim 6, wherein a column driver unit is connected with the memory matrix for either erasing content of selected rows or writing a word into the selected rows.

10. The electronic memory device according to claim 6, wherein the address decoder includes first inverters to receive respectively the address mask input lines and to provide inverted address mask inputs, first NAND gates respectively receiving the inverted address mask inputs and corresponding row address input lines, and second NAND gates respectively receiving outputs of the first NAND gates and the inverted address mask inputs, and wherein the outputs of the first NAND gates and outputs of the second NAND gates are used and combined per three through third NAND gates followed by second inverters for selecting particular rows of the memory matrix.

11. The electronic memory device according to claim 6, wherein the address decoder includes first NOR gates to receive row address input lines and corresponding assigned address mask input lines, and second NOR gates receiving outputs of the first NOR gates and address mask input lines, and wherein the outputs of first NOR gates and outputs of the second NOR gates are used and combined per three through third NOR gates for selecting particular rows of the memory matrix.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The working principle of the invention will now be described more in detail with reference to the accompanying drawings wherein:

(2) FIGS. 1a and 1b already cited show two embodiments of a typical scheme of an address decoder circuit according to the state of the art;

(3) FIGS. 2a and 2b show two embodiments of a modified structure of an address decoder circuit allowing to speed up the address decoder test and the memory test according to the invention; and

(4) FIG. 3 shows a part of memory matrix with the allocated lines from address decoder circuit according to FIGS. 2a and 2b, an allocated column driver unit and an allocated read unit.

DETAILED DESCRIPTION OF THE INVENTION

(5) As shown in FIGS. 2a and 2b of the present invention, the circuit according to the state of the art as depicted in FIGS. 1a and 1b is modified by adding a bus of addr_msk signals. To each input address line addr_in_0, addr_in_1, addr_in_2, respective address mask input lines addr_msk_0, addr_msk_1, addr_msk_2 are assigned.

(6) In more details for the first embodiment of the address decoder 10 shown in FIG. 2a, there are three first inverters 21 to receive respectively the address mask input lines addr_msk_0, addr_msk_1, addr_msk_2 and to provide three inverted address mask inputs addr_msk_n_0, addr_msk_n_1, addr_msk_n_2. Three first NAND gates 22 respectively receive the inverted address mask inputs addr_msk_n_0, addr_msk_n_1, addr_msk_n_2 and three corresponding address inputs addr_in_0, addr_in_1, addr_in_2 for an address bus of 3 bits. Three second NAND gates 23 respectively receive the outputs of the first NAND gates 22 and the inverted address mask inputs addr_msk_n_0, addr_msk_n_1, addr_msk_n_2. The outputs of the first NAND gates 22 and the outputs of the second NAND gates 23 are used and combined per three through third NAND gates 24 followed by three second inverters 25 for selecting particular rows WL_0, WL_1, WL_2, WL_3, WL_4, WL_5, WL_6, WL_7 of the memory array.

(7) For the second embodiment in FIG. 2b, there are not the first inverters, and the first NAND gates are replaced by three first NOR gates 26. The second NAND gates are replaced by three second NOR gates 27. Finally the third NAND gates and second inverters are replaced by only three third NOR gates 28 for selecting particular rows WL_0, WL_1, WL_2, WL_3, WL_4, WL_5, WL_6, WL_7 of the memory array.

(8) Each bit of this bus of the addr_msk_x signals allows to ignore one bit of the address. In other words, an activated state of an address mask input line has the effect of ignoring the assigned input address line. As above-mentioned the example of the implementation of such a circuit with the additional addr_msk_x lines is depicted in FIGS. 2a and 2b for example for a memory of 8 rows and 8 columns.

(9) This modified structure of the address decoder allows speeding up the address decoder test and the memory matrix or array test as explained below. There is a supplementary input bus with the same width as the width of the address inputs. This bus is called <<addr_msk bus>>, in the following denoted by addr_msk bus only.

(10) The addr_msk bus comprises in the example according to FIGS. 2a and 2b the lines addr-msk_0, addr_msk_1 and addr_msk_2 for a bus of three bits in this case.

(11) The addr_msk bus is used for a test of the address decoder and the memory array by the following way. The electronic memory device with the address decoder can be tested by a separate testing of each bit of the address. The memory can be a non-volatile memory. The test is done by several steps, in which each step checks the decoding of one bit of the row address.

(12) It is to be noted that the number of first inverters, first NAND gates, and second NAND gates of the first embodiment in FIG. 2a depends of the number of bits of address bus. It is the same case for the second embodiment in FIG. 2b with the first NOR gates and second NOR gates.

(13) FIG. 3 shows an electronic memory device 1 with a memory matrix or array 2 organized in rows and columns. The memory matrix 2 has memory cells, wherein the cells of one row are forming one or more memory words. In this example, one word of m bits can be programmed or written on each row of n rows referenced WL_0, WL_1, WL_n2, WL_n1 by an adequate input pattern through a column driver unit 3. An address decoder according to FIGS. 2a and 2b, that is not shown in FIG. 3, is connected to the memory matrix for selecting a particular row according to the address in case, where the addr_msk bus is disabled. In case where at least one line of the addr_msk bus is activated, a plurality of rows of the memory matrix is selected. The column driver unit 3 allows either erasing the content of selected row(s) or writing one or more words into selected row(s) of the memory matrix. Through the column driver unit 3, m column signals BL_0, BL_1, BL_2, BL_3, BL_4, BL_5, BL_6, BL_m1 are provided for erasing or writing the selected rows by the adequate input pattern.

(14) The erasing occurs with a so called High Voltage HV obtained by a conventional charge pump not shown and with a control signal write for the column driver unit 3. After an erase operation all selected rows have a defined value, usually 11 . . . 11. It has to be noted, the width m of a row respectively the number m of columns is independent from the number n of rows. Finally a read unit 4 is also connected to the memory matrix 2 for reading a particular row or a part of a row selected by a particular address on the address bus by passing a conventional sense amplifier 5. For that a read signal controls a control circuit of the read unit 4 and the sense amplifier 5. A read operation however does not make sense, for a plurality of rows selected by a particular address with an activated addr_msk bus.

(15) The method for testing a memory matrix is explained below for an address bus with n=3 respectively with 8 rows and a width of a word of 8, respectively the number of columns m=8. The width of a row is completely independent from the number of rows. In the test method, there are two variants explained hereafter.

(16) Step

(17) The write and read operation of a checkerboard pattern allows to test bit 0 of the address as well as the shorts between the odd/even word lines. Said step 1 comprises in a first variant the following sub-steps:

(18) 1.1 Erase the memory, i.e. all the cells of the memory matrix by putting addr_msk to 111 (=activated for all address mask lines) and performing an erase operation with HV, see FIG. 3. 111 stands in this order for:

(19) addr_msk_2=1

(20) addr_msk_1=1

(21) addr_msk_0=1.

(22) 1.2 Set addr_msk to 110 to ignore all bits of the address except the LSB (assigned address input line), wherein 110 stands in this order for:

(23) addr_msk_2=1

(24) addr_msk_1=1

(25) addr_msk_0=0.

(26) 1.3 Set addr_in to xx0 to select even lines/rows.

(27) 1.4 Perform the write operation by the column driver unit with the pattern d.sub.in=01010 . . . 01. In the nomenclature introduced above the pattern d.sub.in stands in principle for a word.

(28) 1.5 Set addr_in to xx1 to select odd rows.

(29) 1.6 Perform the write operation with the pattern d.sub.in=10101 . . . 10.

(30) 1.7 Read and check/compare the checkerboard pattern. It should look like depicted in the following table, in which the checkerboard pattern is for a test of bit 0 of the address and eventually shorts in the memory array.

(31) TABLE-US-00002 row\ column 7 6 5 4 3 2 1 0 0 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 2 0 1 0 1 0 1 0 1 3 1 0 1 0 1 0 1 0 4 0 1 0 1 0 1 0 1 5 1 0 1 0 1 0 1 0 6 0 1 0 1 0 1 0 1 7 1 0 1 0 1 0 1 0

(32) Reading the checkerboard pattern means a reading of the whole memory matrix row by row according to the above-mentioned table. In this example 8 read operations have to be performed. These 8 reading operations respectively reading the whole memory matrix will be denoted in the following shortly by read matrix.

(33) For a second variant of the test method, the steps 1.5 and 1.6 are not necessary when taking into account the initial value of 1 of each cell after an erase operation of the non-volatile memory device.

(34) It has to be noted, that erasing the memory has the effect, that the content of all cells are set for example to 1 in this particular case.

(35) Step 2

(36) The write and read operation of a checkerboard pattern allows to test bit 1 of the address as well as the shorts between groups of odd/even word lines. Said step 2 comprises in the first variant the following sub-steps:

(37) 2.1 Erase the memory, i.e. all the cells of the memory matrix by putting addr_msk to 111 and performing an erase operation with HV, as shown in FIG. 3.

(38) 2.2 Set addr_msk to 101 to ignore all bits of the address except bit 1.

(39) 2.3 Set addr_in to x0x.

(40) 2.4 Perform the write operation with the pattern d.sub.in=00110011.

(41) 2.5 Set addr_msk in to x1x.

(42) 2.6 Perform the write operation with the pattern d.sub.in=11001100.

(43) 2.7 Read and check/compare the memory content. It should look like depicted in the following table, in which the checkerboard pattern is for a test of bit 1 of the address and also shorts in the memory array at step 2.

(44) TABLE-US-00003 column row 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 2 1 1 0 0 1 1 0 0 3 1 1 0 0 1 1 0 0 4 0 0 1 1 0 0 1 1 5 0 0 1 1 0 0 1 1 6 1 1 0 0 1 1 0 0 7 1 1 0 0 1 1 0 0

(45) Step 2 can be performed alternatively as follows in the second variant of the test method in order to save (respectively in order to omit) one write operation:

(46) 2.1 Erase the memory, i.e. all the cells of the memory matrix by putting addr_msk to 111, and performing an erase operation with HV, as shown in FIG. 3.

(47) 2.2 Set addr_msk to 101 to ignore all bits of the address except bit 1.

(48) 2.3 Set address to x0x.

(49) 2.4 Perform the write operation with d.sub.in=00110011.

(50) 2.7 Read and check/compare the memory content. It should look like in the following table, in which only one row and column needs to be read. So the memory content would look like as follows, in which the checkerboard pattern is for a test of bit 1 of the address and also shorts in the memory array at an alternative step 2.

(51) TABLE-US-00004 row\ column 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 0 0 1 1 0 0 1 1 5 0 0 1 1 0 0 1 1 6 1 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1

(52) Step 3

(53) The write and read operation of a checkerboard pattern allows to test bit 2 of the address as well as the shorts between groups of odd/even word lines. Said step 3 comprises in the first variant the following sub-steps:

(54) 3.1 Erase the memory, i.e. all the cells of the memory matrix by putting addr_msk to 111, and performing an erase operation with HV, as shown in FIG. 3.

(55) 3.2 Set addr_msk to 011 to ignore all the bits of the address except the bit 2.

(56) 3.3 Set address to 0xx.

(57) 3.4 Perform the write operation with the pattern d.sub.in=00001111.

(58) 3.5 Set addr_in to 1xx.

(59) 3.6 Perform the write operation with the pattern d.sub.in=11110000.

(60) 3.7 Read and check/compare the memory content. It should look as depicted in the following table, in which the checkerboard pattern of step 3 is for a test of bit 2 of the address and also shorts in the memory array.

(61) TABLE-US-00005 column row 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 2 0 0 0 0 1 1 1 1 3 0 0 0 0 1 1 1 1 4 1 1 1 1 0 0 0 0 5 1 1 1 1 0 0 0 0 6 1 1 1 1 0 0 0 0 7 1 1 1 1 0 0 0 0

(62) Again also step 3 can be performed alternatively as follows in the second variant of the test method in order to save (respectively in order to omit) one write operation:

(63) 3.1 Erase the memory, i.e. all the cells of the memory matrix by putting addr_msk to b111 and performing an erase operation with HV, as shown in FIG. 3.

(64) 3.2 Set addr_msk to 011 to ignore all bits of the address except bit 2.

(65) 3.3 Set address to 0xx.

(66) 3.4 Perform the write operation with the pattern d.sub.in=00001111.

(67) 3.5 Read and check/compare the memory content. It should look as depicted in the following table, in which only one row and column needs to be read. So the memory content would look like as follows, in which the checkerboard pattern is for a test of bit 2 of the address and also shorts in the memory array at an alternative step 3.

(68) TABLE-US-00006 row\ column 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 2 0 0 0 0 1 1 1 1 3 0 0 0 0 1 1 1 1 4 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1

(69) These patterns also fully check the bit line decoding. This step can be combined with the simultaneous write and read for the test of the bit line decoding especially for memories having a larger number of columns than the number of the rows. It has to be noted in the first variant of the test method, that in the step <<0.6>> an inverse pattern d.sub.in is used, that is a pattern inverse to the pattern in the step <<0.4>>.

(70) The test time reduction depends on the memory size. It is most efficient for large memory blocks. The time reduction is shown in the next table for a memory size of 2.sup.3=8 words as explained above. Not considered is the time needed for test of the bit 0, since it is done by the checkerboard patterns which is anyway used for test of the memory cells.

(71) For a Memory with 2.sup.3=8 Rows Respectively 3 Address Lines

(72) TABLE-US-00007 Accelerated Accelerated with odd only Standard with CKB (Alternative pattern) Number of erase 1 2 2 operations Number of write 8 4 2 operations Total HV 9 6 4 operations (erase + write) Total HV 100 66 44 operations [%] Read matrix 1 3 3

(73) In the previous table, it is mentioned the test time reduction. For that, it is indicated the number of operations according to the example given above with steps 2 and 3.

(74) For a Memory with 2.sup.n Rows Respectively n Address Lines

(75) TABLE-US-00008 accelerated with accelerated odd only standard with CKB (Alternative pattern Number of erase 1 (n 1) (n 1) operations HV Number of write .sup.2.sup.n 2 .Math. (n 1) (n 1) operations Total HV 2.sup.n + 1 3 .Math. (n 1) 2 .Math. (n 1) operations (erase + write) Total HV 100 3 .Math. (n 1)/(2.sup.n + 1) 2 .Math. (n 1)/(2.sup.n + 1)) operations [%] Read matrix 1 (n 1) (n 1)

(76) In the previous table, it is indicated the number of operations for a memory with 2.sup.n rows, respectively n address lines and the corresponding steps 2 to 3.

(77) The reduction of operations in relation to the standard testing is given in the following table, for some typical values of n respectively for a memory size of 2.sup.n words. Said table shows the numerical reduction of operations in relation to the standard testing.

(78) TABLE-US-00009 Total operations Total operations including HV including HV accelerated with accelerated with n 2.sup.n CKB [%] odd only [%] 3 8 66.66 44.44 4 16 52.94 35.29 8 64 8.17 5.45 10 1024 2.63 1.76 12 4096 0.81 0.54

(79) The electronic memory device and the test method disclosed herein are not limited to the purpose as given above. The electronic memory device described as above can be also used for other purposes like:

(80) Simultaneous Write of Two Rows

(81) The same content can be written into two (or even more) rows by one write operation to improve the reliability of the data. The two worst must differ by one bit in address only.

(82) Dynamically Scalable Erase Block

(83) The erase operation can be performed on different memory blocks by using the function described above. The only limitation is the size of the blockit must be a power of two. This feature a scalable erase block is particular useful in applications, where an updated/patch of a software portion has to be carried out.

(84) Redundancy Enabling on the Fly

(85) The redundancy can be simply enabled by ignoring some address bits and it can be even different for different memory wordsthe cycling requirements and gate disturb requirements can be generally different for each word of the memory. Even more than two cells in parallel can be used if needed.

(86) The redundancy means two (or even more) memory cells in parallel to store one bit. The bit can be correctly read even if one of the memory cells doesn't work correctly.

(87) Logical Operation Between Different Words

(88) A logical OR operation can be performed with bits on different words by ignoring of some bits of the address during the reading.

(89) From the description that has just been given, multiple variants of the test method of the electronic memory device, and the electronic memory device can be devised by those skilled in the art without departing from the scope of the invention defined by the claims.