Vacuum-cavity-insulated flow sensors

Abstract

A vacuum-cavity-insulated flow sensor and related fabrication method are described. The sensor comprises a porous silicon wall with numerous vacuum-pores which is created in a silicon substrate, a porous silicon membrane with numerous vacuum-pores which is surrounded and supported by the porous silicon wall, and a cavity with a vacuum-space which is disposed beneath the porous silicon membrane and surrounded by the porous silicon wall. The fabrication method includes porous silicon formation and silicon polishing in HF solution.

Claims

1. A method for fabricating a vacuum-cavity-insulated flow sensor comprising: providing a single crystal silicon substrate; forming a first anodization mask to expose a closed stripe area on the surface of said silicon substrate; performing a first anodization in a HF solution at a lower anodic current density to form a closed porous silicon wall with a thickness ranging from 20 to 60 microns and a width ranging from 30 to 60 microns in said silicon substrate; forming a second anodization mask to expose the area on the surface of said silicon substrate which is surrounded by said closed stripe area or said closed porous silicon wall; performing a second anodization in a HF solution at a lower anodic current density to form a porous silicon layer with a thickness ranging from 10 to 60 microns in said silicon substrate which is surrounded and supported by said closed porous silicon wall; continually performing said second anodization in a HF solution at a higher pulse anodic current density to form a cavity with a thickness ranging from 1 to 20 microns and a length ranging from 400 to 2000 microns under said porous silicon layer and to convert said porous silicon layer into a porous silicon membrane that is suspended over said cavity; depositing a dielectric film on the surface of said silicon substrate including the surface of said closed porous silicon wall and said porous silicon membrane using RF sputtering or high vacuum LPCVD; creating a heating element on the surface of said dielectric film disposed at a middle of said porous silicon membrane; creating two temperature sensing elements on the surface of said dielectric film disposed parallel with said heating element at two opposite sides; creating three pairs of metal conducting strips with three pairs of metal bonding pads disposed opposite to two sides of said porous silicon membrane for respectively connecting said heating element and said temperature sensing elements to an external circuit therefore.

2. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said single crystal silicon substrate has a resistivity ranging from 0.1 to 0.001 ohm-cm.

3. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said anodization mask is silicon-rich silicon nitride layer.

4. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said anodization at a lower anodic current density is performed in a HF solution consisting of 49 wt. % HF in water and ethanol, having a HF concentration ranging from 12 to 35 vol % and at an anodic current density ranging from 20 mA to 80 mA/square cm.

5. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said anodization at a higher pulse anodic current density is performed in a HF solution consisting of 49 wt. % HF in water and ethanol, having a HF concentration ranging from 12 to 35 vol. % and at a pulse current density ranging from 100 mA to 500 mA/square cm with a pulse width ranging from 10 to 100 ms and a frequency ranging from 1 to 10 Hz.

6. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said dielectric layer is silicon nitride layer or silicon oxide layer which is sputtered at a pressure ranging from 0.001 to 10 Pa.

7. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said dielectric layer is silicon nitride layer or silicon oxide layer which is deposited at a pressure ranging from 0.001 to 10 Pa. by high vacuum LPCVD.

8. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said heating element is a polysilicon resistor.

9. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said heating element is a platinum resistor.

10. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said temperature sensing element is thermopile consisting of p-type polysilicon or n-type polysilicon and aluminum or gold.

11. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said temperature sensing element is thermopile consisting of p-type polysilicon and n-type polysilicon.

12. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said temperature sensing element is platinum resistors or nickel resistors.

13. A method for fabricating a vacuum-cavity-insulated flow sensor according to claim 1 wherein said temperature sensing element is polysilicon resistors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The exemplary embodiment(s) of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.

(2) FIG. 1 illustrates the perspective, partially cross-sectional, diagrammatic sketch of a vacuum-cavity-insulated flow sensor in accordance with the present invention.

(3) FIG. 2 illustrates the cross-sectional view showing a first silicon-rich silicon nitride masking layer formed on the surface of a silicon substrate which is step 1 for fabricating the vacuum-cavity-insulated flow sensor in accordance with the present invention.

(4) FIG. 3 illustrates the cross-sectional view showing a closed porous silicon wall formed in the silicon substrate which is step 2 for fabricating the vacuum-cavity-insulated flow sensor in accordance with the present invention.

(5) FIG. 4 illustrates the cross-sectional view showing a second silicon-rich silicon nitride masking layer on the silicon substrate which is step 3 for fabricating the vacuum-cavity-insulated flow sensor in accordance with the present invention.

(6) FIG. 5 illustrates the cross-sectional view showing a porous silicon layer formed in the region surrounding by the porous silicon wall which is step 4 for fabricating the vacuum-cavity-insulated flow sensor in accordance with the present invention.

(7) FIG. 6 illustrates the cross-sectional view showing an air filled cavity is created beneath the porous silicon layer so that the porous silicon layer becomes a suspended porous silicon membrane, which is step 5 for fabricating the vacuum-cavity-insulated flow sensor in accordance with the present invention.

(8) FIG. 7 illustrates the cross-sectional view showing a dielectric layer deposited on the surface of the silicon substrate including the surface of the porous silicon wall and the porous silicon layer and therefore the air-filled cavity under the porous silicon layer becomes a vacuum-cavity, which is step 6 for fabricating the vacuum-cavity-insulated flow sensor in accordance with the present invention.

(9) FIG. 8 illustrates the cross-sectional view showing a heating element formed on the dielectric layer, which is preferred to be polysilicon resistor and is positioned at the center region of the top of the suspended porous silicon membrane in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

(10) Referring to FIG. 1, a preferable embodiment of a vacuum-cavity-insulated flow sensor according to the present invention, comprises a single crystal silicon substrate (101), a porous silicon wall with numerous vacuum-pores therein (102) which is disposed in the silicon substrate, a porous silicon membrane with numerous vacuum-pores therein (103) which is surrounded and supported by the porous silicon wall, a cavity with vacuum inside thereof (104) which is disposed under the porous silicon membrane, a dielectric layer (105) deposited on the surface of the silicon substrate which includes the surface of the porous silicon wall and the porous silicon membrane, heating element (106) disposed laterally passing through at the middle of the porous silicon membrane, two temperature sensing elements (107) disposed at two opposite sides of the heating element, and three pairs of metal conducting strips (108) with three pairs of metal bonding pads (109) disposed at three sides of the porous silicon membrane.

(11) According to the present invention, the silicon substrate (101) is heavily doped p-type or n-type single crystal silicon having a resistivity ranging from 0.1 to 0.001 ohm-cm.

(12) The porous silicon wall (102) is created in the silicon substrate (101) and has a resistivity 10 times higher than the silicon substrate. The porous silicon membrane (103) is created in the region surrounded and is supported by the porous silicon wall (102). It should be noted that in the anodization process for forming the porous silicon membrane the porous silicon wall blocks the anodic current flow through therein. So the porous silicon membrane can be surrounded and supported by the porous silicon wall without any laterally extending. The porous silicon wall (102) and the porous silicon membrane (103) have almost a same thickness which ranges from 10 to 60 microns. The width of the porous silicon wall ranges from 20 to 50 microns and the length of the porous silicon membrane ranges from 400 to 2000 microns. The cavity (104) is created under the porous silicon membrane (103). It is also should be noted that the cavity is formed under the porous silicon membrane and the porous silicon wall because the anodic current for forming the cavity is limited to flow from the back side of the silicon substrate to the bottom of the porous silicon membrane and the porous silicon wall without any extending to the outside region of the porous silicon wall. So the edge of the cavity (104) completely disposed under the porous silicon wall (102). The thickness and length of the cavity (104) range respectively from 1 to 20 microns and from 400 to 2000 microns.

(13) It well known that in a vacuum environment there is no thermal conduction to take place because the thermal conductivity of the residual gas therein is zero. It is clear that if a micromachined gap can be drawn into vacuum the heat lost caused by thermal conduction of the micromachined gap can be avoided. Hear said vacuum usually means that the pressure in the micromachined gap is down to 0.001 to 10 Pa.

(14) Generally, the mechanical strength of a porous silicon structure formed by anodization in a HF solution decreases with the porosity of the porous silicon structure. In order to make the porous silicon structure such as a porous silicon membrane to withstand higher pressure, the thickness of the porous silicon structure is preferred to be relatively large but not too much which is reasonable to be 10 to 50 microns.

(15) It is also well known that the thermal conductivity of porous silicon decreases greatly up to 0.002 W/cm K as the porosity is larger than 30% and is almost three orders of the amplitude lower than that of crystal Si1.56 W/cm K. For thermal insulation application, a thicker porous silicon membrane does not increase heat lost too much, but increase mechanical strength significantly.

(16) The dielectric layer (105) is preferred to be a silicon nitride or a silicon oxide layer. To draw the cavity and the porous silicon membrane into vacuum, the dielectric layer (106) should be formed using a high vacuum deposition technique such as RF-sputtering, high vacuum LPCVD. In these deposition techniques, the working pressure is less than 10 Pa. so that the porous silicon wall (102), the porous silicon membrane (103), and the cavity (104) all can be drawn into vacuum at this process.

(17) It is preferred that the heating element (107) is a resistor such as polysilicon resistor or platinum resistor and the temperature sensing elements (109) are thermopiles or thermistors.

(18) Flow measurements are based on heat exchange between the sensor and the flowing fluid. Under flow, the downstream temperature sensing element is heated up and the upstream temperature sensing element is cooled down. As output signal of the sensor, the difference between the two temperature sensing elements outputs is measured. In this way, the sensitivity of the sensor is improved and any error due to changes of the heater resistance, induced by temperature changes (sensor offset), is minimized.

(19) Referring now to the drawings, from FIG. 2 to FIG. 8, there are cross-sectional views showing a method for fabricating a vacuum-cavity-insulated flow sensor according to the first embodiment of the present invention.

(20) Referring to FIG. 2, a single side polished, crystalline plane (100) oriented p-type silicon wafer (201) with a resistivity ranging from 0.1 to 0.001 ohm-cm is provided. A 3000 Angstroms-thick Si rich silicon nitride layer (202) is deposited on the surface of the wafer (201) by LPCVD (low pressure chemical vapor deposition). A photoresist process is performed to create a first mask pattern with an exposed region having a width ranging from 2 to 10 microns in the silicon nitride layer (202). The shape of the region surrounded by the exposed region is square or rectangular. The unwanted silicon nitride layer is selectively removed by plasma etching.

(21) Referring to FIG. 3, in order to make a porous silicon wall (204) in the silicon substrate (201), an anodization process is performed in a HF solution. A double electrochemical cell is used for the anidization process. The used HF solution consists of 49 wt. 49% HF in water and ethanol. The used HF concentration in a HF solution ranges from 12 to 36 wt. %. The used anodic current density ranges from 20 mA to 80 mA/square cm. The resulted the porous silicon wall has a width ranging from 20 to 50 microns and a thickness ranging from 20 to 60 microns. As shown in the figure that during the anodization process an anodic current (203) flow from the back surface of the silicon substrate to the exposed region of the first mask pattern in three different ways: upwards, to-right and to-left. The porous silicon wall (204) is formed also in three directions: downwards, to-left and to-right so that the width of the porous silicon wall is larger than the width of the exposed region of the first mask pattern.

(22) Referring to FIG. 4, another 3000 Angstroms-thick Si rich silicon nitride layer (205) is deposited on the surface of the wafer (201) by LPCVD (low pressure chemical vapor deposition). Then another photoresist process is performed to create a second mask pattern with an exposed region in the silicon nitride layer. It should be noted that the porous silicon wall (204) now is covered by the silicon nitride layer. The exposed region is square or rectangular. The unwanted silicon nitride layer is selectively removed by plasma etching.

(23) Referring to FIG. 5, another anodization process is performed to form a porous silicon layer (207) in the silicon substrate (201). The used HF solution also consists of 49 wt. 49% HF in water and ethanol. The used HF concentration in a HF solution also ranges from 12 to 36 wt. %. The used anodic current density also ranges from 20 mA to 80 mA/square cm. The resulted porous silicon layer (207) has a thickness ranging from 10 to 60 microns and a length ranging from 400 to 2000 microns. It should be noted that the resistivity of the porous silicon wall (203) is to times as large as the silicon substrate (201). A shown in the figure during the anodization process, the anodic current (206) cannot flow through the porous silicon wall to the exposed region of the nitride layer from the back side of the silicon substrate. So porous silicon can only form in the region surrounding by the porous silicon wall until the thickness of the formed the porous silicon layer to reach the same thick as the porous silicon wall.

(24) Referring to FIG. 6, a cavity (209) is formed by continuing the anodization process performed in FIG. 4. Since the cavity can only be formed in the silicon substrate by silicon electro-polishing in HF solution at a higher anodic current density. So the used anodic current density is increased to 100 mA to 500 mA/square cm. But when the anodic current density is too high, it is easy for the porous silicon layer to detach from the silicon substrate, because too much hydrogen gas is produced at the bottom of the porous silicon layer. To overcome this problem, a pulse anodic current is used, which has a pulse width ranging from 10 to 100 ms and a frequency ranging from 1 to 10 Hz.

(25) As shown in the figure the anodic current (208) flow still cannot through the porous silicon wall and the porous silicon layer is limited in the region surrounded by the porous silicon wall.

(26) Referring to FIG. 7, a dielectric layer (210) is formed on the whole surface of the silicon substrate (201) including the porous silicon wall (204) and the porous silicon layer (207). The dielectric layer is a RF sputtered silicon nitride or silicon oxide at a pressure ranging from 0.1 to 10 Pa. As an alternative the dielectric layer is a high vacuum LPCVD deposited silicon nitride or silicon oxide. During the process for forming the dielectric layer the cavity (209), the porous silicon wall (204) and the porous silicon layer (207) are drawn into vacuum. The pressure inside the cavity, the pores of the porous silicon wall and the porous silicon layer is nearly the same as the operation pressure of the RF sputter or LPCVD furnace. The thickness of the dielectric layer is preferred to be 2000 to 5000 angstroms. In order to reduce stress, annealing is performed at 950 degree C. for 30 min.

(27) Referring to FIG. 8, a heating element (211) is formed on the dielectric layer (210). The heating element is preferred to be polysilicon resistor. To do this a polysilicon layer is deposited by LPCVD on the surface of the dielectric layer (210). Then a photoresist process is followed to remove unwanted polysilicon. The resulted polysilicon resistor is disposed at the center of the porous silicon layer (membrane). As an alternative the heating element is a platinum resistor which is created by sputtering and lift-off process. Still as alternative the heating element is a nickel resistor which is created by electron beam evaporation or sputtering.

(28) It is preferred that the temperature sensing elements (212) are two thermopiles each comprising 10 to 30 thermocouples. Each thermopile consists of p-type polysilicon or n-type polysilicon and aluminum or gold. The needed polysilicon portion is formed at the process for forming the polysilicon resistor. The needed aluminum portion or gold portion is formed at the process for forming conduction interconnection including conduction stripes (213) and bonding pads (not shown in the figure). As an alternative the temperature sensing elements are two platinum resistors which are created at the process for forming platinum resistor used for heating element. Still as alternative the temperature sensing elements are two nickel resistors which are created at the process for forming nickel resistor used for heating element. Still as alternative the temperature sensing elements are two polysilicon resistors which are created at the process for forming polysilicon resistor used for heating element.

(29) While the present invention has been described with reference to particular embodiments of the vacuum-cavity-isolation flow sensors, it is obvious that other embodiments can be used without departing from the teachings herein. Obviously, many modifications and variations are possible in light of the teaching herein. It is therefore to be understood that within the scope of the appended claims, the present invention may be practiced other than as specifically described.