Power semiconductor device

Abstract

A power semiconductor device is described. The device comprises a silicon carbide substrate and a layer of monocrystalline silicon having a thickness t.sub.Si no more than 5 m disposed directly on the substrate or directly on an interfacial layer having a thickness no more than 100 nm which is disposed directly on the substrate. The device comprises a lateral transistor, such as a laterally-diffused metal oxide semiconductor transistor or lateral insulated gate bipolar transistor, comprising first and second contacts laterally-spaced contact regions disposed in the monocrystalline silicon layer.

Claims

1-15. (canceled)

16. A power semiconductor device comprising: a silicon carbide substrate; a layer of monocrystalline silicon having a thickness no more than 5 m disposed directly on an interfacial layer having a thickness no more than 100 nm which is disposed directly on the substrate; and a lateral power transistor which is a laterally-diffused metal oxide semiconductor transistor or insulated gate bipolar transistor, the transistor comprising: first and second contact laterally-spaced contact regions disposed in the monocrystalline silicon layer, and a drift region disposed in the monocrystalline silicon layer.

17. A device according to claim 16, wherein the substrate comprises a 4H-SiC substrate.

18. A device according to claim 16 or 17, wherein the substrate is semi-insulating.

19. A device according to claim 16, wherein the substrate has a thickness no more than 300 m.

20. A device according to claim 16, wherein the substrate has a thickness no more than 50 m.

21. A device according to claim 16, wherein the monocrystalline silicon layer has a thickness no more than 2 m.

22. A device according to claim 16, wherein the monocrystalline silicon layer has a thickness no more than 1 m.

23. A device according to claim 16, wherein the monocrystalline silicon layer has a thickness no more than 300 nm.

24. A device according to claim 16, wherein the monocrystalline silicon layer comprises an n-type region or p-type region.

25. A device according to claim 16, wherein the interfacial layer comprises a dielectric material.

26. A device according to claim 16, wherein the interfacial layer comprises a semiconductor material.

27. A method of operating a device according to claim 16 at a temperature of at least 200 C., the method comprising: applying a drain-source voltage of at least 100 V.

28. A method according to claim 27, comprising: applying a drain-source voltage up to 600 V.

29. A device according to claim 16, wherein the lateral device is operable at a temperature of at least 200 C. and a drain-source voltage of at least 100 V.

30. A device according to claim 16, wherein the interfacial layer has a thickness no more than 50 nm.

31. A device according to claim 16, wherein the interfacial layer has a thickness of up to 5 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0021] FIG. 1 is a vertical section of a first semiconductor device;

[0022] FIG. 2 is a vertical section of a second semiconductor device;

[0023] FIG. 3 is a vertical section of a third semiconductor device;

[0024] FIG. 4 is a vertical section of a fourth semiconductor device;

[0025] FIG. 5 is a vertical section of a fifth semiconductor device;

[0026] FIG. 6 is a vertical section of a sixth semiconductor device;

[0027] FIG. 7 is a process flow diagram of a method of fabricating a semiconductor device;

[0028] FIGS. 8A to 8D are vertical sections through a semiconductor device at different stages during fabrication;

[0029] FIG. 9 illustrates plots of simulated current density against reverse drain-source bias;

[0030] FIG. 10 are greyscale plots of electric field distribution; and

[0031] FIG. 11 show simulated plots of current density and internal junction temperature.

DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS

[0032] In the following, like parts are denoted by like reference numerals.

Device Structures

First Power Semiconductor Device

[0033] Referring to FIG. 1, a first power semiconductor device comprising a first laterally-diffused metal oxide semiconductor (LDMOS) transistor 1 is shown.

[0034] The device comprises a semi-insulating, six-step hexagonal silicon carbide (6H-SiC) substrate 2. The substrate 2 has a thickness, t.sub.sub, of 300 m. The substrate 2 can be thinner and the substrate thickness, t.sub.sub, can be as small as 50 m.

[0035] A layer 3 of lightly-doped n-type monocrystalline silicon is disposed on an upper surface 4 of the substrate 2. A field oxide 5 is located at an upper surface 6 of the silicon layer 3 and has first and second windows 7.sub.1, 7.sub.2 defining first and second laterally-separated upper surfaces 6.sub.1, 6.sub.2 of the silicon layer 3.

[0036] A gate oxide 8 is disposed within the first window 7.sub.1 on the upper surface 6.sub.1 of the silicon layer 3. The gate oxide 8 runs along the upper surface 6.sub.1 of the silicon layer 3 and abuts the field oxide 5 thereby forming a step 9. A layer of heavily doped n-type polycrystalline silicon 10 (which may also be referred to as the gate poly) is disposed on the gate oxide 8 and runs over the step 9 onto the field oxide 5. Additionally or alternatively, a layer of metallization, such as aluminium (Al), can be used. The gate poly 10 includes an extension 11. Silicon dioxide spacers (not shown) may be formed on the sides of the gate poly 10. The silicon layer 3 provides a drift region 12.

[0037] A p-type body 13 in the form of a lightly-doped p-type diffusion well is disposed within the silicon layer 3 at the first upper surface 6.sub.1. The p-type body 13 extends laterally under the gate oxide 8. An n-type buffer 14 in the form of a moderately-doped n-type well is disposed within the silicon layer 3 at the second upper surface 6.sub.2. First and second contact regions 15.sub.1, 15.sub.2 (herein referred to as source region and drain region respectively) in the form of respective heavily-doped, shallow n-type diffusion wells are disposed in the p-type well 13 and n-type buffer 14 at the first and second upper surfaces 6.sub.1, 6.sub.2. A body contact region 16 in the form of a heavily-doped, shallow p-type diffusion well is disposed at the first upper surface 6.sub.1 adjacent to the source contact 15.sub.1.

[0038] Deep trench isolation in the form of oxide-lined, poly silicon-filled trenches 17.sub.1, 17.sub.2 extending downwardly from the field oxide 5 through the silicon layer 3 to the substrate 2 are used to electrically isolate the transistor 1 from neighbouring transistor (not shown).

[0039] A layer 18 of silicon dioxide runs over the gate poly 10 and the field oxide 5, and has windows 19.sub.1, 19.sub.2. Layers 20.sub.1, 20.sub.2 of metallization are disposed on the silicon dioxide layer 18 covering windows 19.sub.1, 19.sub.2. The first metallisation layer 20.sub.1 provides a source terminal S and the second metallisation layer 20.sub.2 provides a drain terminal D. The metallization layers 20.sub.1, 20.sub.2 each comprise a bi-layer comprising a high-barrier metal silicide base layer comprising, for example, platinum silicide (PtSi), and a high-conductivity overlayer comprising, for example, aluminium (Al).

[0040] The silicon layer 3 has a thickness, t.sub.Si, of 1 m. However, the silicon layer 3 can be thicker, for example, up to 2 m or even 5 m. Preferably, however, the silicon layer 3 is as thin as possible and can be as thin as 300 nm. The current rating of the device can be increased by making the gate width larger. The gate width may be at least 100 m, at least 500 m, at least 1 mm or at least 2 mm.

[0041] The contacts regions 15.sub.1, 15.sub.2, source S and drain D may have one or more different geometries or layouts.

[0042] For example, the contacts regions 15.sub.1, 15.sub.2, source S and drain D may extend along the y-axis so as to form generally parallel stripes. The contacts regions 15.sub.1, 15.sub.2 may have the same length along the y-axis. However, one contact region 15.sub.1, 15.sub.2 (and its corresponding metallization S, D) may be longer than the other contact region 15.sub.1, 15.sub.2 (and its corresponding metallization S, D), thereby giving the device 1 a wedge-like appearance in plan view.

[0043] Alternatively, the device 1 may be arranged such that one of the contact regions 15.sub.1, 15.sub.2 (and its corresponding metallization S, D) is disposed at the centre of the device 1 and the other contact region 15.sub.1, 15.sub.2 (and its corresponding metallization S, D) is arranged as a concentric ring, thereby giving the device a circular appearance in plan view.

[0044] The power semiconductor device can have one or more advantages.

[0045] Being silicon-based, the transistor 1 may not suffer high channel resistance problems typically exhibited by silicon carbide devices.

[0046] Furthermore, the 6H-SiC substrate 2 can be semi-insulating and can provide electrical isolation due to having a wide band gap which results in low conductivity: the resistivity of the substrate can exceed 10.sup.7 cm. The 6H-SiC substrate 2 has a high breakdown electric field which can increase breakdown voltage by a factor of about two to three times, as the vertical electric field is allowed to spread through silicon carbide. Moreover, 6H-SiC has the highest thermal conductivity of all the common silicon carbide polytypes and so can efficiently conduct heat away from the active area of the device thereby reducing the effect of self-heating.

[0047] Thus, the power semiconductor device, in comparison to bulk silicon or silicon-on-insulator devices, can be used in environments at higher ambient temperatures, to operate more efficiently at a given temperature and/or to run at a higher power throughput.

Second Power Semiconductor Device

[0048] Referring to FIG. 2, a second power semiconductor device comprising a second LDMOS transistor 21 is shown.

[0049] The second power semiconductor device is substantially the same as the first power semiconductor device except that an interfacial layer 22 is interposed between the substrate 2 and the silicon layer 3. The interfacial layer 22 is in direct contact with the upper surface 4 of the substrate and the silicon layer 3 is in direct contact with an upper surface of the interfacial layer 22.

[0050] The interfacial layer 22 can aid bonding of the silicon layer 3 and the substrate 2.

[0051] The interfacial layer 22 may consist of a dielectric material, such as silicon dioxide, silicon nitride (Si.sub.xN.sub.y), aluminium oxide (Al.sub.2O.sub.3) or hafnium oxide (HfO.sub.2). The interfacial layer 22 may consist of polycrystalline silicon.

[0052] The interfacial layer 22 (whether it is a dielectric or a semiconductor) has a thickness, t.sub.int, no more than 100 nm. Preferably, the interfacial layer 22 has a thickness of about 50 nm.

Third Power Semiconductor Device

[0053] Referring to FIG. 3, a third power semiconductor device comprising a third LDMOS transistor 31 is shown.

[0054] The third power semiconductor device is substantially the same as the first power semiconductor device except that it employs so called linear doping along the length of the drift region 12 which can help to improve blocking voltage. In particular, dopant concentration in the silicon layer 3 increases from the source to the drain. The doping concentration increases by an order of magnitude, i.e. n.sub.d2=10.Math.n.sub.d1, where n is the doping concentration (in this case, of donors) under the drain and n.sub.d1 is the doping concentration under the source.

Fourth Power Semiconductor Device

[0055] Referring to FIG. 4, a fourth power semiconductor device comprising a fourth LDMOS transistor 41 is shown.

[0056] The fourth power semiconductor device is substantially the same as the first power semiconductor device except that it employs a reduced surface field (RESURF) doping profile which can help to improve breakdown voltage and minimise on-resistance. In particular, a p-type region 42 is provided between the n-type drift region 12 and the substrate 2.

Fifth Power Semiconductor Device

[0057] Referring to FIG. 5, a fifth power semiconductor device comprising a fifth LDMOS transistor 51 is shown.

[0058] The fifth power semiconductor device is substantially the same as the first power semiconductor device except that a thicker silicon layer 3 is used. This can shift the current rating versus breakdown voltage trade-off back toward the current throughput. In particular, the silicon layer 3 can have a thickness, t.sub.Si, greater than 2 m, up to 5 m.

Sixth Power Semiconductor Device

[0059] In the embodiments hereinbefore described, the lateral transistors take the form of field-effect transistors. However, the transistor can take other forms.

[0060] Referring to FIG. 6, a sixth power semiconductor device comprising an insulated gate bipolar transistor (IGBT) 61 is shown.

[0061] The sixth power semiconductor device is substantially the same as the first power semiconductor device except that the second contact region 15.sub.2 is of opposite polarity type, i.e. a heavily-doped p-type shallow well which sits in the n-type body region 14. The first and second contact regions 15.sub.1, 15.sub.2 in this type of device are referred to as emitter and collector regions respectively.

Fabrication

[0062] Referring to FIG. 7 and to FIGS. 8A to 8D, a method of fabricating a power semiconductor device will now be described.

[0063] An SOI wafer 81, which comprises a silicon substrate 82 (or handle), a buried silicon oxide layer 83 and surface oxide layer 84, and substrate wafer 2, such as a 6H-SiC wafer, are cleaned using solvent and acid dips (not shown) and a megasonic rinse (not shown) (step S1). Optionally, a thin layer of silicon dioxide (not shown) may be deposited on the surface 86 of SOI wafer 81 to render the surface hydrophilic (step S2).

[0064] The surface 86 is then plasma activated, for example, using an EVG LT 810 Series Plasma Activation System (step S3).

[0065] The surfaces 86, 4 of the SOI wafer 81 and the substrate wafer 2 are aligned and brought together to form a composite wafer 88 (step S4). The composite wafer 88 is annealed at 1,000-1,200 C. for 30 seconds to strength interfacial bond (step S5).

[0066] The SOI wafer 81 is then ground and polished to remove the handle 82 (step S6). The oxide layer 83 is then removed using hydrofluoric acid (not shown) (step S7) and the resulting surface 87 is chemically-mechanically polished (step S8) to thin the silicon layer 84 to produce the silicon layer 3 (FIG. 1) of the desired thickness.

[0067] The transistor is then fabricated (step S9). This may start with forming the field oxide 5 (FIG. 1) at the surface of the silicon layer 3 by thermal oxidation using a LOCOS process. The transistors can be fabricated in a manner well known per se.

Simulated Device Characteristics

[0068] Referring to FIGS. 9, 10 and 11, simulated characteristics, carried out using SILVACO Atlas software, of a LDMOS transistor (Si/SiC MOSFET) having a layer of silicon disposed directly on an semi-insulating 6H-SiC substrate and a comparative example in the form of an LDMOS transistor (SOI MOSFET) disposed on a silicon-on-insulator (SOI) substrate comprising of type a p-doped handle wafer (N.sub.A=110.sup.17 cm.sup.3) and 1 m of buried oxide are shown.

[0069] Both transistors have the same structure and dimensions. The transistors have a layer of silicon having a thickness of 2 m. The drift region is 45 m long between source and drain regions and narrows to 1 m beneath the field oxide.

[0070] For the Si/SiC MOSFET, the drift region is lightly n-doped Si (N.sub.D=110.sup.15 cm.sup.3). For the SOI MOSFET, however, linear doping is used so increasing the doping in the drift region from N.sub.D=110.sup.15 cm.sup.3 at the source to N.sub.D=110.sup.16 cm.sup.3 at the drain so as to maximise the breakdown voltage of the transistor.

[0071] FIG. 9 shows simulated breakdown voltages in which source-to-drain voltage is increased until leakage current begins to rise exponentially. As seen in FIG. 1, despite having similar structures, the Si/SiC MOSFET reaches 600 V, compared to 210 V for the linearly doped SOI MOSFET (without the linear doping, the breakdown voltage is just 110 V).

[0072] FIG. 10 shows electric field distribution in the Si/SiC and SOI MOSFETs at the point of avalanche breakdown. The contours (which are black when they exceed the critical electric field of Si) are shown to have very different distributions in each of the device structures.

[0073] In the SOI MOSFET, the electric field is highly concentrated towards the drain end of the drift region, with the insulating buried oxide not allowing any significant vertical spreading of the electric field.

[0074] In the Si/SiC MOSFET, however, there is significant vertical spreading of the electric field into the substrate. This results in a more even spread of the electric field laterally along the drift region from source to drain.

[0075] Self-heating characteristics of the Si/SiC and SOI MOSFETs are tested by looking at the forward bias characteristics.

[0076] Referring to FIG. 11, the solid shapes represent the output J.sub.DS-V.sub.DS characteristics of each device, without considering the effects of temperature. A gate bias of 7V is applied to each device and is driven well into the saturation region as V.sub.DS is ramped up thereby increasing the power dissipated in the device. The hollow shapes represent results using electro-thermal simulations. The bottom graph shows the localised temperature of the devices as V.sub.DS is ramped up. The decreasing current is an effect known as negative resistance, where the rise in temperature causes the internal resistance of the drift region to rise, reducing the total current throughput. At V.sub.DS=200 V, self-heating is responsible for a 10% reduction in current throughput in the Si/SiC MOSFET compared to a 20% reduction in the SOI MOSFET. Furthermore, the internal junction temperature of the SOI MOSFET at this point has risen by 108 C., a temperature rise over three times greater than the Si/SiC MOSFET.

Modifications

[0077] It will be appreciated that various modifications may be made to the embodiments hereinbefore described. Such modifications may involve equivalent and other features which are already known in the design, manufacture and use of power semiconductor devices and component parts thereof and which may be used instead of or in addition to features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment. For example, the interfacial layer of the second power semiconductor device may be used in combination with the linear doping of the second power semiconductor device.

[0078] The transistors may be p-type rather than n-type. Thus, a p-type silicon layer may be used and the body regions and contact regions may be of a suitable conductivity type.

[0079] A semi-insulating 6H-SiC substrate need not be used. An n- or p-type doped 6H-SiC substrate can be used. Other polytypes of SiC, such as 4H-SiC, can be used.

[0080] Substrates other than SiC which have high thermal conductivity can be used such as, for example, diamond or aluminium nitride (AlN).

[0081] The silicon layer need not be formed by wafer bonding a silicon-on-insulator wafer onto a substrate wafer (with or without a thin dielectric layer), grinding back the handle wafer, etching (using hydrofluoric acid) the oxide and polishing the surface. The silicon layer can be formed using Smartcut. The silicon layer can be formed by bonding a silicon wafer to a substrate wafer (with or without a thin dielectric layer), then grinding back and polishing the silicon wafer. The silicon wafer can be formed by epitaxially growing a layer of silicon on the substrate using molecular beam epitaxy (MBE) or chemical vapour deposition (CVD).