CLOCK SIGNAL GENERATOR, ON-CHIP CLOCK SYSTEM, AND CHIP

Abstract

The technology of this application relates to a clock signal generator, an on-chip clock system, and a chip. The clock signal generator includes a first transistor, a second transistor, a flip-flop, and a power supply end. A first electrode of the first transistor and a first electrode of the second transistor are coupled to the power supply end, and a second electrode of the first transistor and a second electrode of the second transistor are coupled to a common ground. A first input end of the flip-flop is coupled to the first electrode of the first transistor, and a second input end of the flip-flop is coupled to the first electrode of the second transistor. The clock signal generator can make a frequency of an output clock signal more stable.

Claims

1. A clock signal generator, comprising: a first transistor; a second transistor; a flip-flop; and a power supply end, wherein a first electrode of the first transistor and a first electrode of the second transistor are coupled to the power supply end, and a second electrode of the first transistor and a second electrode of the second transistor are coupled to a common ground; and a first input end of the flip-flop is coupled to the first electrode of the first transistor, and a second input end of the flip-flop is coupled to the first electrode of the second transistor.

2. The clock signal generator according to claim 1, further comprising: a control signal generation circuit, wherein signal output ends of the control signal generation circuit are respectively coupled to a control electrode of the first transistor and a control electrode of the second transistor, and the control signal generation circuit periodically provides a control signal to the control electrode of the first transistor and the control electrode of the second transistor, to alternately turn on and turn off the first transistor and the second transistor based on the control signal.

3. The clock signal generator according to claim 2, wherein the control signal is a voltage signal.

4. The clock signal generator according to claim 2, further comprising: a first capacitor; and a second capacitor, wherein a first electrode of the first capacitor is coupled to the control electrode of the first transistor, a second electrode of the first capacitor is coupled to the common ground, and the first transistor is periodically turned on or turned off based on charging/discharging of the first capacitor, and a first electrode of the second capacitor is coupled to the control electrode of the second transistor, a second electrode of the second capacitor is coupled to the common ground, and the second transistor is periodically turned on or turned off based on charging/discharging of the second capacitor.

5. The clock signal generator according to claim 4, wherein the control signal is a current signal, and the control signal generation circuit is configured to alternately and periodically provide the current signal to the first electrode of the first capacitor and the first electrode of the second capacitor to charge the first capacitor and the second capacitor.

6. The clock signal generator according to claim 4, further comprising: a third transistor, wherein a control electrode and a first electrode of the third transistor are coupled to the power supply end, and a second electrode of the third transistor is coupled to the common ground; and the control signal generation circuit is configured to generate a current signal based on a voltage signal between the first electrode and the second electrode of the third transistor.

7. The clock signal generator according to claim 5, further comprising: a current mirror circuit, wherein the control signal generation circuit provides the current signal to the current mirror circuit, and the current mirror circuit performs mirror processing on a received current based on a preset proportion, and provides a processed current to the first electrode of the first capacitor and the first electrode of the second capacitor.

8. The clock signal generator according to claim 5, further comprising: a first selector; and a second selector, wherein a control end of the first selector is coupled to a first output end of the flip-flop, a first input end of the first selector is coupled to an output end of the control signal generation circuit, a second input end of the first selector is coupled to the common ground, and an output end of the first selector is coupled to the control electrode of the first transistor, a control end of the second selector is coupled to a second output end of the flip-flop, a first input end of the second selector is coupled to an output end of the control signal generation circuit, a second input end of the second selector is coupled to the common ground, and an output end of the second selector is coupled to the control electrode of the second transistor, the first selector periodically gates the first input end and the second input end of the first selector under control of a clock signal that is output by the first output end of the flip-flop, to periodically charge and discharge the first capacitor, and the second selector periodically gates the first input end and the second input end of the second selector under control of the clock signal that is output by the first output end of the flip-flop, to periodically charge and discharge the second capacitor.

9. The clock signal generator according to claim 1, wherein the first input end of the flip-flop is coupled to the first electrode of the second transistor through an even quantity of phase inverters.

10. The clock signal generator according to claim 6, wherein the second input end of the flip-flop is coupled to the first electrode of the third transistor through an even quantity of phase inverters.

11. The clock signal generator according to claim 6, wherein a quantity of first transistors, a quantity of second transistors, and a quantity of third transistors are in a preset proportion; and a parameter of the first transistor, a parameter of the second transistor, and a parameter of the third transistor are the same.

12. An on-chip clock system, wherein the on-chip clock system comprises the clock signal generator according to claim 1.

13. A chip, wherein the chip comprises the on-chip clock system according to claim 12.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0023] To describe the technical solutions in embodiments of this application more clearly, the following briefly introduces the accompanying drawings for describing embodiments of this application. It is clear that the accompanying drawings in the following description show merely a part of embodiments of this application, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.

[0024] FIG. 1 is an example schematic diagram of a structure of a clock circuit in the conventional technology;

[0025] FIG. 2 is an example schematic diagram of a structure of a clock signal generator according to an embodiment of this application;

[0026] FIG. 3 is an example schematic diagram of another structure of a clock signal generator according to an embodiment of this application;

[0027] FIG. 4 is an example schematic diagram of still another structure of a clock signal generator according to an embodiment of this application;

[0028] FIG. 5 is an example schematic diagram of a structure of a voltage-current conversion circuit according to an embodiment of this application;

[0029] FIG. 6 is an example schematic diagram of still another structure of a clock signal generator according to an embodiment of this application; and

[0030] FIG. 7 is an example schematic diagram of a specific structure of a clock signal generator according to an embodiment of this application.

DESCRIPTION OF EMBODIMENTS

[0031] The following clearly describes the technical solutions in embodiments of this application with reference to the accompanying drawings in embodiments of this application. It is clear that the described embodiments are a part but not all of embodiments of this application. All other embodiments obtained by a person of ordinary skill in the art based on embodiments of this application without creative efforts shall fall within the protection scope of this application.

[0032] The term “first”, “second”, or the like mentioned in this specification does not indicate any order, quantity, or importance, but is used only for distinguishing between different components. Likewise, the term “a/an”, “one”, or the like is not intended to indicate a quantity limitation either, but is intended to indicate at least one. The term “coupling”, “connection”, “link”, or the like is not limited to a physical or mechanical connection, but may include an electrical connection, whether directly or indirectly.

[0033] The term “unit” mentioned in this specification is usually a functional structure that is obtained through division based on logic, and the “unit” may be implemented only by hardware, or implemented by a combination of software and hardware.

[0034] In embodiments of this application, the term “and/or” describes an association relationship between associated objects and indicates that at least three relationships may exist. For example, A and/or B may indicate the following three cases: Only A exists, both A and B exist, and only B exists.

[0035] In embodiments of this application, the word “example”, “for example”, or the like is used to represent giving an example, an illustration, or a description. Any embodiment or design scheme described as “example” or “for example” in embodiments of this application should not be explained as being more or having more advantages than another embodiment or design scheme. Exactly, use of the word “example”, “for example”, or the like is intended to present a related concept in a specific manner.

[0036] In the descriptions of embodiments of this application, unless otherwise stated, “a plurality of” means two or more than two. For example, a plurality of processing units refer to two or more processing units. A plurality of systems refer to two or more systems.

[0037] FIG. 1 shows a typical clock circuit in the conventional technology. As shown in FIG. 1, the clock circuit includes a voltage-current conversion unit 01 configured to convert a voltage signal into a current signal, and a clock signal unit 02 configured to generate a clock signal. The voltage-current conversion unit 01 is a previous-stage circuit of the clock circuit. An integrated operational amplifier B1 converts a voltage into a current and provides the current to a gate electrode of a transistor A1, so that a signal is input to the clock signal unit 02 through the transistor A1. The clock signal unit 02 is a post-stage circuit of the clock circuit. Two comparators C1 and C2 are disposed in the clock signal unit 02, and are configured to generate trigger signals of an SR flip-flop. It can be learned from FIG. 1 that, one of signal input ends of the comparator C1 and one of signal input ends of the comparator C2 are respectively connected to a drain electrode of a transistor A3 and a drain electrode of a transistor A4. A gate electrode of the transistor A3 and a gate electrode of the transistor A4 are controlled by a drain current of the transistor A1, so that a signal used to trigger the SR flip-flop depends on signals output by the voltage-current conversion circuit 01, the comparator C1, and the comparator C2. In this way, a clock signal CLK generated by the SR flip-flop has a feature of following the current generated by the integrated operational amplifier B1 and the signals output by the comparator C1 and the comparator C2. When a signal VREF that is input to an input end of the integrated operational amplifier B1 or a component in the voltage-current conversion unit 01 changes with a change of a temperature or a power supply, the clock signal CLK also changes. In this case, stability of the clock signal output by the clock circuit is greatly reduced. In addition, compared with input signals of the comparator C1 and the comparator C2, output signals of the comparator C1 and the comparator C2 usually have a delay. The delay usually limits a maximum frequency of the clock signal output by the clock circuit. In view of this, an embodiment of this application provides a clock signal generator, so that a comparator may not be disposed, and a clock signal is generated by controlling a first transistor and a second transistor to be turned on or turned off. A frequency of the clock signal is related only to turn-on and turn-off times of the first transistor and the second transistor. The clock signal with a stable frequency can be output by stably controlling the turn-on and turn-off times of the first transistor and the second transistor. In addition, in some implementations provided in this embodiment of this application, turn-on and turn-off of the first transistor and the second transistor are controlled through charging/discharging of a capacitor, so that the turn-on and turn-off times of the first transistor and the second transistor are not affected by a delay, a temperature drift, and the like of an integrated operational amplifier in a voltage-current conversion unit. This can further improve a maximum frequency of the clock signal output by the clock circuit.

[0038] FIG. 2 is a schematic diagram of a structure of a clock signal generator according to an embodiment of this application.

[0039] In FIG. 2, a clock signal generator 100 includes a power supply end Vdd and a clock signal generation circuit 10. The clock signal generation circuit 10 includes a transistor T1, a transistor T2, and an SR flip-flop.

[0040] In this embodiment, the transistor T1 and the transistor T2 each include a control electrode, a first electrode, and a second electrode. The first electrode of the transistor T1 and the first electrode of the transistor T2 are separately coupled to the power supply end Vdd. The power supply end Vdd is configured to receive electric energy provided externally. The second electrode of the transistor T1 and the second electrode of the transistor T2 are separately coupled to a common ground Gnd. The transistor T1 and the transistor T2 herein may be insulated gate field effect transistors, for example, may be PMOS transistors or NMOS transistors. This is not limited herein. When the transistor T1 and the transistor T2 are NMOS transistors, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode. When the transistor T1 and the transistor T2 are PMOS transistors, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode. The figure schematically shows a case in which the transistor T1 and the transistor T2 are NMOS transistors.

[0041] The SR flip-flop includes an input end S, an input end R, an output end QN, and an output end Q. The input end S of the SR flip-flop is connected to the first electrode of the transistor T1. The input end R of the SR flip-flop is connected to the first electrode of the transistor T2. The output end QN or the output end Q of the SR flip-flop is configured to output a clock signal. FIG. 2 schematically shows a case in which the output end Q of the SR flip-flop outputs a clock signal. That is, the clock signal generator 100 outputs the clock signal through an external interface Clk_out. In a working process of the SR flip-flop, when level signals or logic signals currently received by the input end S and the input end R of the SR flip-flop are different from a level signal or a logic signal received last time, jumps of a level signal at the output end QN and a level signal at the output end Q of the SR flip-flop are triggered. To make a signal output by the clock signal generator 100 more stable, generally, the input end S and the input end R of the SR flip-flop receive signals of different levels or different logic at a same moment. That is, when the input end S receives “logic 0”, the input end R receives “logic 1”; when the input end S receives “logic 1”, the input end R receives “logic 0”.

[0042] As shown in FIG. 2, the clock signal generator 100 may further include a control signal generation circuit 20 configured to control turn-on and turn-off of the transistor T1 and the transistor T2. The control signal generation circuit 20 may include but is not limited to a programmable logic controller (PLC), a digital signal processor (DSP), a signal generator, and the like. Output ends of the control signal generation circuit 20 are respectively coupled to the control electrode of the transistor T1 and the control electrode of the transistor T2.

[0043] Specifically, as shown in FIG. 2, the control signal generation circuit 20 may include two output ends, where one output end is coupled to the control electrode of the transistor T1, and the other output end is coupled to the control electrode of the transistor T2. Herein, a signal output by the control signal generation circuit 20 may be a voltage signal. The transistor T1 is used as an example. The control signal generation circuit 20 and the second electrode of the transistor T1 may be coupled to the same common ground, so that the control signal generation circuit 20 may apply a voltage signal between the control electrode and the second electrode of the transistor T1. When the voltage signal is greater than a turn-on voltage of the transistor T1, the transistor T1 is turned on. When the voltage signal is stopped being applied, the transistor T1 is turned off. In this embodiment, the control signal generation circuit 20 may control the transistor T1 and the transistor T2 to be alternately turned on and turned off. That is, when the transistor T1 is turned on, the transistor T2 is turned off; when the transistor T2 is turned on, the transistor T2 is turned off. Therefore, the input end S and the input end R of the SR flip-flop can alternately receive signals of different levels.

[0044] With reference to the circuit structure shown in FIG. 2, a working principle of the clock signal generator 100 in this embodiment of this application is described.

[0045] A working status of the transistor T1 is used as an example. A signal received by the input end S of the SR flip-flop is first described. When the transistor T1 is turned on, an electric potential at a node a is an internal resistance voltage drop of the transistor T1. Generally, the internal resistance voltage drop of the transistor T1 is very small and can be almost ignored. Herein, the electric potential at the node a may be considered as 0 V. In this case, the input end S of the SR flip-flop receives a low-level signal or “logic 0”. When the transistor T1 is turned off, the electric potential at the node a is an electric potential of the power supply end Vdd. In this case, the input end S of the SR flip-flop receives a high-level signal or “logic 1”. For a working status of the transistor T2 and a signal received by the input end R of the SR flip-flop, refer to descriptions of the transistor T1 and the signals received by the input end S of the SR flip-flop.

[0046] In a first time period, the transistor T1 is controlled to be turned on, and the transistor T2 is controlled to be turned off. In this case, the input end S of the SR flip-flop receives a low-level signal or “logic 0”, and the input end R of the SR flip-flop receives a high-level signal or “logic 1”. In this case, the Q end outputs the low-level signal or the “logic 0”. In a second time period, the transistor T1 is controlled to be turned off, and the transistor T2 is controlled to be turned on. In this case, the input end S of the SR flip-flop receives a high-level signal or “logic 1”, and the input end R of the SR flip-flop receives a low-level signal or “logic 0”. In this case, the Q end outputs the high-level signal or the “logic 1”. Therefore, based on a to-be-generated clock cycle, the transistor T1 and the transistor T2 are periodically controlled to be turned on or turned off, so that high-level and low-level signals, that is, clock pulse signals, can be alternatively output at the output end Q of the SR flip-flop.

[0047] It can be learned from FIG. 2 that, in this embodiment of this application, the input end S and the input end R of the SR flip-flop are respectively connected to the first electrode of the transistor T1 and the first electrode of the transistor T2, so that signals that are input to the input end S and the input end R of the SR flip-flop can be separated from control signals that control the transistor T1 and the transistor T2 to be turned on or turned off. In comparison with the clock circuit shown in FIG. 1 in which the output end of the comparator is connected to the input end of the SR flip-flop, in this embodiment of this application, a period or a frequency of the clock pulse signal of the output end of the SR flip-flop is related only to turn-on times and turn-off times of the transistor T1 and the transistor T2. The SR flip-flop can output a stable clock signal provided that the turn-on times and the turn-off times of the transistor T1 and the transistor T2 are stably controlled. This avoids a clock frequency change caused by a change of a delay of a signal output by the comparator with a temperature, so that the frequency of the clock signal output by the clock signal generator 100 is more stable. Signals applied to the control electrode of the first transistor T1 and the control electrode of the second transistor T2 may alternatively be implemented through charging/discharging of a capacitor. Specifically, FIG. 3 is a schematic diagram of a structure of another clock signal generator according to an embodiment of this application.

[0048] As shown in FIG. 3, a capacitor C1 is connected between a control electrode of a transistor T1 and a common ground Gnd, and a capacitor C2 is connected between a control electrode of a transistor T2 and the common ground Gnd. In this case, a changeover switch may be disposed inside a control signal generation circuit 20 to charge/discharge the capacitor C1 and the capacitor C2. When the control signal generation circuit 20 charges the capacitor C1 and the capacitor C2, a control signal output by the control signal generation circuit 20 is a current signal. The capacitor C1 is used as an example. The control signal generation circuit 20 inputs a current signal to the capacitor C1, the capacitor C1 is charged, and an electric potential at a node n1 gradually rises. When the electric potential at the node n1 rises to a specific value, so that a voltage between the control electrode and a second electrode of the transistor T1 is greater than a turn-on voltage, the transistor T1 is turned on. When an internal current signal generation end of the control signal generation circuit 20 is switched to a low electric potential end (for example, a common ground end), the capacitor C1 is discharged. Under an action of the capacitor C1, the electric potential at the node n1 does not change abruptly. When the capacitor C1 is discharged to a specific value, and a voltage on the transistor T1 is less than the turn-on voltage, the transistor T1 is turned off When the capacitor C1 is charged, the capacitor C2 is discharged. When the capacitor C2 is charged, the capacitor C1 is discharged. Therefore, the transistor T1 and the transistor T2 are alternately turned on and turned off by controlling alternate charging/discharging of the capacitor C1 and the capacitor C2. In a possible implementation, the clock signal generator 100 further includes a third transistor T3, as shown in FIG. 4. In FIG. 4, the transistor T3 may be an NMOS transistor, a PMOS transistor, or the like. This is not limited herein. A control electrode and a first electrode of the transistor T3 are coupled to a power supply end Vdd. The power supply end Vdd is configured to receive electric energy provided externally. A second electrode of the transistor T3 is coupled to a common ground Gnd. When external electric energy of the clock signal generator 100 is provided to the control electrode and the first electrode of the transistor T3 through the power supply end Vdd, a voltage between the control electrode and the second electrode of the transistor T3 is greater than a turn-on voltage, and the transistor T3 is turned on. In this case, an electric potential at a node b in FIG. 4 is equal to a voltage drop between the first electrode and the second electrode of the transistor T3. In FIG. 4, as long as a voltage difference between electric energy provided by the power supply end Vdd and the common ground Gnd is greater than a conduction voltage of the transistor T3, the transistor can work in on-state, and even if a power signal changes, the electric potential at the node b is not greatly affected. Therefore, a stable voltage signal can be provided for a control signal generation circuit 20 by disposing the transistor T3, so that the control signal generation circuit 20 provides a stable current signal for a clock signal generation circuit 10.

[0049] In FIG. 4, the control signal generation circuit 20 may convert a voltage signal between the first electrode and the second electrode of the transistor T3 into a current signal, and alternately provide the current signal to the capacitor C1 and the capacitor C2 shown in FIG. 3.

[0050] In this implementation, the control signal generation circuit 20 may be a circuit whose output current and input voltage are in a proportional relationship. In the conventional technology, any circuit whose output current and input voltage can be in a proportional relationship may be used as the control signal generation circuit 20 shown in this application. This is not specifically limited herein. In specific implementation, the control signal generation circuit 20 may have a structure shown in FIG. 5. In the control signal generation circuit shown in FIG. 5, a current output by an output end of an integrated operational amplifier B1 is equal to a sum of a bias voltage of the integrated operational amplifier and an electric potential at a node b divided by a resistance value of a resistor R. The bias voltage of the integrated operational amplifier B1 and the resistance value of the resistor R are set, so that the output current of the integrated operational amplifier B1 and the electric potential at the node b have a proportional relationship.

[0051] In some optional implementations, the clock signal generator 100 may further include a current mirror circuit 30. FIG. 6 is a schematic diagram of a connection relationship between the current mirror circuit 30 and other circuit elements. An output end of a control signal generation circuit 20 is coupled to an input end of the current mirror circuit 30. An output end of the current mirror circuit 30 is coupled to a control electrode of a transistor T1 and a control electrode of a transistor T2 in a clock signal generation circuit 10. After performing mirror processing on a received current signal, the current mirror circuit 30 provides the current signal to a capacitor C1 and a capacitor C2 in the clock signal generation circuit 10 through the output end. The control signal generation circuit 20 may be a circuit whose output current and input voltage are in a proportional relationship, for example, may have a circuit structure of the control signal generation circuit 20 shown in FIG. 5. The current mirror circuit 30 may be a current mirror circuit for performing mirror processing on a current at a preset ratio, or a circuit for amplifying a current at a preset ratio. For example, a ratio of currents of an input end and an output end of the current mirror circuit is 1:N. Herein, N is an integer greater than or equal to 1. In other words, in this optional implementation, the current mirror circuit 30 performs, at a preset ratio, mirror processing on a current input by the control signal generation circuit 20, and provides a processed current to the clock signal generation circuit 10.

[0052] In this optional implementation, a requirement on the control signal generation circuit 20 can be reduced by disposing the current mirror circuit 30. When a relatively large current needs to be input to the clock signal generation circuit 10, the current mirror circuit 30 may be used for implementation, so that stability of the control signal generation circuit 20 can be improved. This further improves stability of a clock signal generated by the clock signal generator 100.

[0053] With reference to FIG. 7, the following describes a specific structure of a clock signal generator 100 according to an embodiment of this application.

[0054] In FIG. 7, the clock signal generator 100 includes a clock signal generation circuit 10, a control signal generation circuit 20, a current mirror circuit 30, a transistor T3, a power supply end Vdd, and a clock signal output end Clk_out. The clock signal generation circuit 10 includes a transistor T1, a transistor T2, an SR flip-flop, a capacitor C1, and a capacitor C2. For connection relationships between components in the clock signal generation circuit 10, refer to related descriptions in FIG. 2 and FIG. 3. For structures of units and connection relationships in the control signal generation circuit 20 and the current mirror circuit 30, refer to related descriptions in FIG. 4 to FIG. 6.

[0055] In the clock signal generator 100 shown in FIG. 7, the clock signal generation circuit 10 further includes a selector M1 and a selector M2. A control end k1 of the selector M1 is coupled to an output end QN of the SR flip-flop. An input end d1 of the selector M1 is coupled to an output end of the current mirror circuit 30. An input end d2 of the selector M1 is coupled to a common ground Gnd. An output end o1 of the selector M1 is coupled to a control electrode of the transistor T1. A control end k2 of the selector M2 is coupled to an output end Q of the SR flip-flop. An input end d3 of the selector M2 is coupled to the output end of the current mirror circuit 30. An input end d4 of the selector M2 is coupled to the common ground Gnd. An output end o2 of the selector M2 is coupled to a control electrode of the transistor T2. The capacitor C1 is coupled between the control electrode of the transistor T1 and the common ground Gnd. The capacitor C2 is coupled between the control electrode of the transistor T2 and a common ground Gnd.

[0056] Working principles of the selector M1 and the selector M2 are described by using the selector M1 as an example. When the control end k1 of the selector M1 receives “logic 0” or a low-level signal, the selector M1 gates the input end d1. In this case, an output end of a current mirror circuit 30 is connected to the control electrode of the transistor T1, the capacitor C1 is charged, and an electric potential at a node n1 gradually rises. When the electric potential at the node n1 rises to a specific value, so that a voltage between the control electrode and a second electrode of the transistor T1 is greater than a turn-on voltage, the transistor T1 is turned on. When the control end k1 of the selector M1 receives “logic 1” or a high-level signal, the selector M1 gates the input end d2. In this case, the control electrode of the transistor T1 is connected to the common ground Gnd, and the capacitor C1 is discharged. Under an action of the capacitor C1, the electric potential at the node n1 does not change abruptly. When the capacitor C1 is discharged to a specific value, and a voltage on the transistor T1 is less than the turn-on voltage, the transistor T1 is turned off. The working principle of the selector M2 is the same as that of the selector M1.

[0057] In FIG. 7, the transistor T1 and the transistor T2 are turned on or turned off through charging/discharging of the capacitor C1 and the capacitor C2. The capacitor C1, the capacitor C2, the selector M1, the selector M2, the transistor T1, the transistor T2, and the SR flip-flop work together to periodically generate a clock signal.

[0058] Specifically, a level signal at the output end QN of the SR flip-flop is the same as a level signal at an input end S of the SR flip-flop, and a level signal at the output end Q of the SR flip-flop is the same as a level signal at an input end R of the SR flip-flop.

[0059] It is assumed that at a current moment, the output end QN of the SR flip-flop outputs “logic 1” or a high-level signal, and the output end Q of the SR flip-flop outputs “logic 0” or a low-level signal. In a first time period, the capacitor C1 is charged, and the electric potential at the node n1 gradually rises. When the electric potential at the node n1 rises to a specific value, the transistor T1 is turned on, so that an electric potential at a node a1 is a low electric potential. The input end S of the SR flip-flop receives the low-level signal or the “logic 0”, and in this case, the output end QN of the SR flip-flop is triggered to flip. That is, the output end QN of the SR flip-flop outputs the “logic 0” or the low-level signal. The capacitor C2 is discharged, and an electric potential at a node n2 gradually decreases. When the electric potential at the node n2 decreases to a specific value, the transistor T2 is turned off, so that an electric potential at a node a2 is a high electric potential. The input end R of the SR flip-flop receives the high-level signal, and in this case, the output end Q of the SR flip-flop is triggered to flip. That is, the output end Q of the SR flip-flop outputs the “logic 1” or the high-level signal. Then, a second time period is entered.

[0060] In the second time period, the capacitor C1 is discharged, and the electric potential at the node n1 gradually decreases. When the electric potential at the node n1 decreases to a specific value, the transistor T1 is turned off, so that the electric potential at the node al is a high electric potential. The input end S of the SR flip-flop receives the high-level signal or the “logic 1”, and in this case, the output end QN of the SR flip-flop is triggered to flip. That is, the output end QN of the SR flip-flop outputs the “logic 1” or the high-level signal. The capacitor C2 is charged, and the electric potential at the node n2 gradually rises. When the electric potential at the node n2 rises to a specific value, the transistor T2 is turned on, so that the electric potential at the node a2 is a low electric potential. The input end R of the SR flip-flop receives the low-level signal, and in this case, the output end Q of the SR flip-flop is triggered to flip. That is, the output end Q of the SR flip-flop outputs the “logic 0” or the low-level signal.

[0061] In this way, through charging/discharging of the capacitor C1 and the capacitor C2, the output end Q and the output end QN of the SR flip-flop periodically output the high-level signal and the low-level signal. That is, the clock signals are formed at the output end Q and the output end QN separately. A clock frequency of the clock signal is a level signal flipping frequency of the output end Q or a level signal flipping frequency of the output end QN.

[0062] It can be learned from FIG. 7 that, in this embodiment, the transistor T1 and the transistor T2 are controlled through charging/discharging of the capacitor C1 and the capacitor C2, so as to trigger level flipping of the output end QN and the output end Q of the RS flip-flop to generate a clock signal.

[0063] A difference from the conventional technology shown in FIG. 1 lies in that, turn-on times and turn-off times of the transistor T1 and the transistor T2 in this embodiment are related only to charging/discharging times of the capacitor C1 and the capacitor C2. The clock frequency output by the clock signal generator 100 can be controlled by controlling the charging/discharging times of the capacitor C1 and the capacitor C2. The charging/discharging times of the capacitor C1 and the capacitor C2 are related to materials and capacities of the capacitor C1 and the capacitor C2, and charging/discharging constants of the capacitors. In this way, the turn-on times and turn-off times of the transistor T1 and the transistor T2 are turned off from an output current of the control signal generation circuit 20, so that the clock signal output by the SR flip-flop is turned off from the control signal generation circuit. This avoids a change of a turn-on/off time of a transistor caused by a temperature drift and a change of a static operating point of an integrated operational amplifier in the control signal generation circuit, and improves stability of an output clock signal. In addition, in some application scenarios, when a relatively high clock frequency is required, a capacitor with a small capacity and a short charging/discharging time may be used. When a relatively low clock frequency is required, a capacitor with a large capacity and a long charging/discharging time may be used. Therefore, a maximum frequency of a clock signal to be output by the clock signal generator 100 can be effectively increased, and performance of the clock signal generator is improved.

[0064] In some implementations, the input end S of the SR flip-flop is coupled to a first electrode of the transistor T1 through an even quantity of phase inverters; and the input end R of the SR flip-flop is coupled to a first electrode of the transistor T2 through an even quantity of phase inverters. FIG. 7 schematically shows a case in which the input end S of the SR flip-flop is coupled to the first electrode of the transistor T1 through two phase inverters F1 and F2, and the input end R of the SR flip-flop is coupled to the first electrode of the transistor T2 through two phase inverters F3 and F4. The clock signal generator 100 can improve a driving capability of a circuit by disposing the phase inverter F1, the phase inverter F2, the phase inverter F3, and the phase inverter F4. This improves flipping speeds of the level signals at the input end S and the input end R of the SR flip-flop.

[0065] In some implementations, parameters of the transistor T1, the transistor T2, and the transistor T3 are associated. Specifically, to provide a stable static operating point for the clock signal generator 100, the transistor T1 and the transistor T2 may have a same physical parameter and a same operating parameter, that is, have same parameters such as a conduction voltage drop, an internal resistance, and a power. There may be a proportional relationship between physical parameters and a proportional relationship between operating parameters of the transistor T1 and the transistor T3. In this way, a current flowing through the node a1 is the same as a current flowing through the node a2, and a current flowing through a node b and a current flowing through the node a1 have a proportional relationship. This reduces a temperature drift of the static operating point of the clock signal generator 100.

[0066] In the embodiments shown in FIG. 2 to FIG. 7, a case in which a relationship between a quantity of transistors T1, a quantity of transistors T2, and a quantity of transistors T3 is 1:1:1 is schematically shown. In some scenarios, the quantity of transistors T1, the quantity of transistors T2, and the quantity of transistors T3 may alternatively be in another proportional relationship. For example, there may be two transistors T1, the two transistors T1 are connected in series between the power supply end Vdd and the common ground Gnd, and there may be one transistor T2 and one transistor T3.

[0067] An embodiment of this application further provides an on-chip clock system. The on-chip clock system may include any clock signal generator described above and another structure such as a voltage source. The structure such as the voltage source is a conventional and common technology.

[0068] An embodiment of this application further provides a chip. The chip includes the foregoing on-chip clock system. The on-chip clock system including any clock signal generator described above may provide a stable clock signal for each module inside the chip, so that each module inside the chip works stably based on the clock signal.

[0069] Specifically, the chip may be an integrated circuit chip, and includes but is not limited to an artificial intelligence chip, a digital signal processing chip, an image processing chip, and the like. When the chip is configured to provide an image processing function and a data analysis and computing function for an application installed on a terminal device (for example, a mobile phone, a computer, or a wearable intelligent device), the electronic device may be a server device, and the chip may be disposed in the server device. When the chip is applied to the autonomous driving field to provide necessary vehicle-mounted computing, the electronic device may be a vehicle-mounted control device, and the AI chip may alternatively be disposed in the vehicle-mounted control device. Alternatively, the chip may be a 5G chip. In this case, the electronic device may be a base station hardware device that communicates with a terminal, and the AI chip may be disposed in the base station hardware device.

[0070] The foregoing describes embodiments of this application with reference to the accompanying drawings. However, this application is not limited to the foregoing specific implementations. The foregoing specific implementations are merely examples, but are not limitative. Inspired by this application, a person of ordinary skill in the art may further make many modifications without departing from the purposes of this application and the protection scope of the claims, and all the modifications shall fall within the protection scope of this application.