Integrators for current sensors

Abstract

An integrator for use with a current sensor provides a feedback loop reducing drift while maintaining wide bandwidth.

Claims

1. An integrator circuit for use with current sensors, comprising: an input for receiving an input signal from a current sensor; an op-amp receiving the input signal from the input, the op-amp having an output providing an output voltage signal, the output voltage signal being capable of being tapped for measurement; a diode pump comprising a first capacitor and a second capacitor, a load resistor, a diode, a transistor, and a power source, the diode pump receiving the output voltage signal and providing a diode pump output voltage signal; a FET having a critical threshold voltage; and an integrator resistor and an integrator capacitor in parallel; wherein, in the presence of a signal noise, the diode pump output voltage signal controls the FET to either close the gate when the diode pump output voltage signal exceeds the critical threshold voltage or open the gate when the diode pump output voltage signal is less than the critical threshold voltage, such that a drift resulting from the signal noise is minimized while simultaneously maintaining a bandwidth of the integrator.

2. The integrator circuit of claim 1, wherein the FET is a JFET.

3. The integrator circuit of claim 1, wherein the FET is a MOSFET.

4. The integrator circuit of claim 1, wherein the output voltage signal is tapped for measurement by an external meter.

5. The integrator circuit of claim 1, wherein the diode pump is constructed on a single chip.

6. The integrator circuit of claim 1, wherein the current sensor is a Rogowski coil.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 depicts an embodiment of a practical integrator known in the art for use with Rogowski coils.

(2) FIG. 2 depicts an embodiment of the invention, illustrating an integrator as a practical operational amplifier with frequency dependent gain control and automatic reset, allowing the feedback to drive the gate voltage of the FET via a frequency discriminator.

DETAILED DESCRIPTION OF THE INVENTION

(3) With reference to the Figures, FIG. 1 illustrates a typical integrator known in the art, in which the incoming current i.sub.1 is passed to an op-amp, resistors and a capacitor, and emerges as output signal V.sub.o providing the measurement of the incoming current. Such an integrator is prone to drift from high and low frequency noise, and while the choice of resistors may be able to reduce such drift, it can do so effectively only at the cost of a reduction of bandwidth. With lower values for the resistor R.sub.F, the capacitor C.sub.F is discharged quickly and drift is reduced, but the cutoff frequency is concomitantly lowered, thereby reducing the effective bandwidth of the integrator. With higher values for the resistor R.sub.F, the capacitor C.sub.F is discharged less rapidly, maintaining bandwidth, but the input current noise will be integrated, thereby resulting in larger drift.

(4) The invention described herein provides a feedback loop capable of reducing drift and maintaining bandwidth by using a FET in the circuit which acts as a voltage controlled variable resistor. In a typical n-type JFET, a negative voltage from gate to source V.sub.gs increases the depletion region. As V.sub.gs becomes more negative it decreases the channel width. The current going from drain to source I.sub.ds depends on the channel resistance drain to source r.sub.ds. When the depletion region widens and the channel narrows, the channel resistance r.sub.ds increases until the channel is depleted of all charge carriers and no current flows. The particular V.sub.gs where this occurs is known as the pinch off voltage V.sub.c. When the voltage drain to source V.sub.ds increases, V.sub.gs remains constant while the reverse bias voltage of each pn junction will increase as we move up the channel. The depletion region assumes a tapered shape and the channel becomes pinched off at the drain end. The maximum current at the drain I.sub.d occurs when V.sub.gs=0 and is defined as current drain to source shorted (or saturated), or I.sub.dss. When the JFET is biased with a large V.sub.ds and V.sub.c<V.sub.gs<0, it will operate in the active region (or the saturation) region.

(5) In the JFET linear region, (also known as the ohmic region or the triode region), the drain current is expressed as

(6) $\begin{array}{cc}{I}_d=V_{ds}\left(\frac{2I_{dss}}{V_c^2}\right)\left(V_{gs}-V_c-\frac{V_{ds}}{2}\right)& \left(2\right)\end{array}$

(7) When V.sub.ds<<2 (V.sub.gs−V.sub.c), i.e., when the FET is operating in the linear region,

(8) $\begin{array}{cc}{I}_d\approx V_{ds}\left(\frac{2I_{dss}}{V_c^2}\right)\left(V_{gs}-V_c\right)& \left(3\right)\end{array}$

(9) By definition, the channel resistance r.sub.ds is

(10) $\begin{array}{cc}{r}_{ds}=\frac{V_{ds}}{I_d}.Math.\mathrm{Vds}\mathrm{small}={\left[\left(\frac{2I_{dss}}{V_c^2}\right)\left(V_{gs}-V_c\right)\right]}^{-1}& \left(4\right)\end{array}$

(11) With the properties of such a FET, an improved integrator may be constructed. In FIG. 2, an integrator (1) of the invention is illustrated. The coil voltage V.sub.in (2) is the input of the operational amplifier and it is a relatively weak signal. After passing through resistor R.sub.1 (3) the signal passes to op-amp (4). Rather than using the input signal to control the integrator, as is done in conventional integrators, the invention uses the output V.sub.out (15) of the operational amplifier to automatically control the gain of the integrator (1), and in the extreme case of DC input signals, to reset the integrator (1).

(12) This control is accomplished by means of a frequency to voltage converter. In some embodiments, the converter is a diode pump comprising capacitors C.sub.1 (5) and C.sub.2 (6), resistor R (7), diode D.sub.1 (9), transistor T.sub.1 (10), and a power source (11). The first negative swing at the output V.sub.out (15) charges C.sub.1 (5) through the base-emitter diode of T.sub.1 (10) to V.sub.out (15), and the subsequent positive swing to zero causes C.sub.1 (5) to discharge into C.sub.2 (6) so that

(13) $\begin{array}{cc}{V}_p=V_{out}\left(\frac{C_1}{C_1+C_2}\right)& \left(5\right)\end{array}$

(14) where V.sub.p (8) is the diode pump output signal. The second negative swing of V.sub.out (15) charges C.sub.1 (5) to (V.sub.p+V.sub.out) volts because the right hand connection of C.sub.1 (5) is caught at V.sub.p (8) by T.sub.1 (10). When V.sub.out (15) starts to return to ground for the second time D.sub.1 (9) conducts immediately, in contrast to the situation in which V.sub.out (15) must rise by

(15) $V_{out}\left(\frac{C_1}{C_1+C_2}\right)$
before D.sub.1 (9) would conduct. The full rise of V.sub.out (15) is therefore shared by C.sub.1 (5) and C.sub.2 (6) as on the first positive swing, and the output therefore rises, as before by

(16) $V_{out}\left(\frac{C_1}{C_1+C_2}\right).$
This process is repeated so V.sub.p (8) is a staircase function whose steps are given by

(17) $V_{out}\left(\frac{C_1}{C_1+C_2}\right).$
The addition of the load resistor R (7) in parallel to the large C.sub.2 (6) results in equal increments of charge transfer per cycle and the pump acts as a frequency discriminator. The components of the diode pump are selected so that at DC (or an appropriately chosen low frequency limit) V.sub.p (8) reaches the critical threshold (V.sub.c) of the FET, which then begins to conduct. This will result in integrator capacitor C.sub.f (14) discharging much more quickly than it would in the conventional integrator depicted in FIG. 1. When V.sub.p (8) is less than V.sub.c, the FET is open, the net impedance of the feedback path is slightly smaller than integrator resistor R.sub.f (13). The resulting signal present at V.sub.out (15) may be tapped for reading by a meter in addition to it being used to control the gain of the integrator (1). Configured in this manner, the integrator maintains a large bandwidth while minimizing DC drift.

(18) In some embodiments, the diode pump may be constructed on a single chip such that all the components of the diode pump are situate on a single module. In other embodiments, the frequency-to-voltage converter may be a chip such as an LM331 converter, in which case a p type FET (such as a p type JFET) would be used in place of an n type FET.

(19) Those of skill in the art will readily appreciate that the components of the integrator and diode pump may be chosen to achieve particularly desired results in particular applications.

EXAMPLES

(20) The following Examples serve to illustrate the present invention and are not intended to limit its scope in any way.

Example 1—an Integrator for Use with Current Sensors

(21) An integrator (1) for use with current sensors such as Rogowski coils is constructed as follows. Resistors R.sub.1 (3) are selected with resistance of 10 kΩ ohms. Diode pump capacitor C.sub.1 (5) is selected with capacitance of 1 μF, and C.sub.2 (6) with capacitance of 100 μF. Load resistor R (7) is selected with resistance of 10 kΩ ohms. Integrator resistor R.sub.f (13) is selected with resistance of 100 kΩ ohms. Integrator capacitor C.sub.f (5) is selected with capacitance of 100 nF. The power source (11) is set to −10V. Diode D.sub.1 (9) is a 1N4148 standard silicon switching signal diode. Transistor T.sub.1 (10) is a 2N3906 standard PNP transistor. FET Q.sub.1 (12) is a JFET J310 standard N-channel JFET. The op-amp is selected from standard op-amps such as LM741 and LM324. When a signal from a current sensor such as a Rogowski coil is connected at V.sub.in (2) the integrator thus constructed provides at V.sub.out (15) from the op-amp a signal which may be read by a meter, and which signal provides an accurate measurement of the current with reduced drift and wide bandwidth.

(22) The present invention is not to be limited in scope by the specific embodiments described above, which are intended as illustrations of aspects of the invention. Functionally equivalent methods and components are within the scope of the invention. Various modifications of the invention, in addition to those shown and described herein, will be readily apparent to those skilled in the art from the foregoing description. Such modifications are intended to fall within the scope of the appended claims. All cited documents are incorporated herein by reference.