Circuit and method for frequency synthesis for signal detection in automatic voltage regulation for synchronous generators

Abstract

Automatic voltage regulation is shown involving full wave rectifying a power signal and generating a reference corresponding to an operating voltage level, line sampling the power signal and comparing it to the reference to generate a line sync signal synchronized to the power signal. Producing 90 out of phase signals synchronized to the line sync signal with a PLL locked onto the line sync signal that outputs a phase error signal. Generating a quadrature signal from the phase signals. Sampling the peaks of the rectified power signal using the quadrature signal to produce a control signal. Subtracting the error signal and damping signal from the reference to produce a duty cycle modulation signal. The duty cycle modulation signal controls a duty cycle of a field voltage control signal that oscillates at a predetermined frequency. The field voltage control signal is low-pass filtered to produce the damping signal. The control signal is utilized to detect a short circuit condition and engage a circuit protection device. The reference voltage may also be obtained from another generator so that the output voltage is controlled to operate in sync with the other generator.

Claims

1. An automatic voltage regulator circuit, the circuit comprising: a direct current power supply circuit configured to receive a power signal to be regulated and, responsive thereto, full wave rectify the received power signal and generate a DC reference voltage signal, where a voltage level of the DC reference voltage corresponds to a desired steady state operating voltage level for the power signal; a line sampling circuit configured to receive the power signal and compare the power signal to the DC reference voltage signal in order to generate a line sync signal synchronized to an oscillation frequency of the power signal; a quadrature signal generator circuit configured to receive the line sync signal and produce first and second phase signals that are synchronized to the line sync signal and 90 out of phase with one another, where the quadrature signal generator circuit includes a phase locked loop circuit configured to lock onto the frequency of the line sync signal using a lock frequency that is at least twice the oscillation frequency of the power signal, where the phase locked loop circuit is configured to output a phase error signal that corresponds to a phase difference between the line sync signal and an oscillating frequency of the phase locked loop; a quadrature sync circuit configured to receive the first and second phase signals and, responsive thereto, generate a quadrature signal that is in quadrature with the line sync signal; a sample and hold circuit configured to receive the quadrature signal and the full wave rectified power signal and responsive thereto, sample the peak voltages of the full wave rectified power signal using the quadrature signal and hold the sampled peak voltages to produce a voltage level control signal representing a current absolute magnitude of the amplitude of the power signal; an error amplifier configured to receive the reference voltage, the voltage level control signal, and a damping signal, where the error amplifier circuit is further configured to subtract the error signal and the damping signal from the reference voltage in order to produce a duty cycle modulation signal; a duty cycle modulator circuit configured to receive the duty cycle modulation signal and, responsive thereto, produce a field voltage control signal, where the field voltage control signal oscillates at a predetermined frequency with a duty cycle controlled by the duty cycle modulation signal; a stabilizer circuit configured to receive the field voltage control signal and, responsive thereto, low-pass filter the field voltage control signal in order to produce the damping signal; and a short circuit detection circuit configured to monitor the voltage level control signal and, if the voltage level control signal representing the current absolute magnitude exceeds a DC tripping threshold level, engage a circuit protection device.

2. An automatic voltage regulator circuit, the circuit comprising: a direct current power supply circuit configured to receive a power signal of a first power generator to be regulated and, responsive thereto, full wave rectify the received power signal and receive a DC reference voltage signal representing a voltage output of a second power generator where the first generator is desired to operate in synchronization with the second power generator; a line sampling circuit configured to receive the power signal and compare the power signal to the DC reference voltage signal in order to generate a line sync signal synchronized to an oscillation frequency of the power signal; a quadrature signal generator circuit configured to receive the line sync signal and produce first and second phase signals that are synchronized to the line sync signal and 90 out of phase with one another, where the quadrature signal generator circuit includes a phase locked loop circuit configured to lock onto the frequency of the line sync signal using a lock frequency that is at least twice the oscillation frequency of the power signal, where the phase locked loop circuit is configured to output a phase error signal that corresponds to a phase difference between the line sync signal and an oscillating frequency of the phase locked loop; a quadrature sync circuit configured to receive the first and second phase signals and, responsive thereto, generate a quadrature signal that is in quadrature with the line sync signal; a sample and hold circuit configured to receive the quadrature signal and the full wave rectified power signal and responsive thereto, sample the peak voltages of the full wave rectified power signal using the quadrature signal and hold the sampled peak voltages to produce a voltage level control signal representing a current absolute magnitude of the amplitude of the power signal; an error amplifier configured to receive the reference voltage, the voltage level control signal, and a damping signal, where the error amplifier circuit is further configured to subtract the error signal and the damping signal from the reference voltage in order to produce a duty cycle modulation signal; a duty cycle modulator circuit configured to receive the duty cycle modulation signal and, responsive thereto, produce a field voltage control signal, where the field voltage control signal oscillates at a predetermined frequency with a duty cycle controlled by the duty cycle modulation signal; and a stabilizer circuit configured to receive the field voltage control signal and, responsive thereto, low-pass filter the field voltage control signal in order to produce the damping signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Various embodiments in accordance with the present disclosure will be described with reference to the drawings, in which:

(2) FIG. 1 is a schematic diagram illustrating a simplified example of a generator system with automatic voltage regulation;

(3) FIG. 2 is a graph illustrating an example of a transient response of a conventional automatic voltage regulator;

(4) FIG. 3 is a functional block diagram illustrating an example of an automatic voltage regulator system in accordance with the present invention;

(5) FIG. 4 is a diagram illustrating a comparison of one example of a line sampling signal to a sampled generator output voltage signal;

(6) FIG. 5 is a functional block diagram illustrating an example of a transfer function for automatic voltage regulation in accordance with the present invention;

(7) FIG. 6 is a waveform diagram illustrating an example of sampling of a rectified power signal to obtain a representation of a voltage level of the generator output voltage;

(8) FIG. 7 is a functional block diagram illustrating another example of an automatic voltage regulator in accordance with some aspects of the present invention;

(9) FIG. 8 is a circuit diagram illustrating an example of one embodiment of circuitry for the DC power supply and line sampling circuits shown in FIG. 7;

(10) FIG. 9 is a circuit diagram illustrating an example of one embodiment of circuitry for the quadrature signal generator with phase locked loop circuit shown in FIG. 7;

(11) FIG. 10 is a circuit diagram illustrating an example of one embodiment of circuitry for the quadrature synchronization circuit shown in FIG. 7;

(12) FIG. 11 is a circuit diagram illustrating an example of one embodiment of circuitry for the power section circuit shown in FIG. 7;

(13) FIG. 12 is a circuit diagram illustrating an example of one embodiment of circuitry for the error amplifier circuit shown in FIG. 7;

(14) FIG. 13 is a circuit diagram illustrating an example of one embodiment of circuitry for the sample and hold circuit shown in FIG. 7;

(15) FIG. 14 is a circuit diagram illustrating an example of one embodiment of circuitry for the duty cycle modulator circuit shown in FIG. 7;

(16) FIG. 15 is a circuit diagram illustrating an example of one embodiment of circuitry for the voltage to hertz control circuit shown in FIG. 7;

(17) FIG. 16 is a photograph of an oscillogram illustrating a relationship between a line voltage sample signal and an output signal from a phase locked loop circuit in one example of an automatic voltage regulator;

(18) FIG. 17 is a photograph of an oscillogram illustrating a relationship between a line voltage sample signal and a quadrature signal produced in one example of an automatic voltage regulator;

(19) FIG. 18 is a photograph of an oscillogram illustrating a relationship between a line voltage signal and sampling pulses produced in one example of an automatic voltage regulator;

(20) FIG. 19 is a photograph of an oscillogram comparing an example of an automatic voltage control signal sample produced by a conventional circuit using rectification and filtering and a control signal produced in one example of the present automatic voltage regulator;

(21) FIG. 20 is a photograph of an oscillogram illustrating a relationship between an error signal and a corresponding output signal from a chopper circuit in response to a transient load event in one example of an automatic voltage regulator;

(22) FIG. 21 is a photograph of an oscillogram illustrating a relationship between the error signal of FIG. 20 and an output voltage of a generator in response to the transient load event of FIG. 20 in one example of an automatic voltage regulator;

(23) FIG. 22 is a control flow diagram illustrating the steps or stages of an exemplary process for voltage to hertz control that may be performed in a processor or similar device to implement a digital embodiment of another example of an automatic voltage regulator;

(24) FIG. 23 is a control flow diagram illustrating the steps or stages of an exemplary process for that may be performed in a processor or similar device to digitally produce an error signal in a digital embodiment of another example of an automatic voltage regulator; and

(25) FIG. 24 is a functional block diagram illustrating an example of a computer system suitable for some aspects of embodiments of an automatic voltage regulator.

(26) Note that the same numbers are used throughout the disclosure and figures to reference like components and features.

DETAILED DESCRIPTION

(27) The subject matter of embodiments of the present invention is described here with specificity to meet statutory requirements, but this description is not necessarily intended to limit the scope of the claims. The claimed subject matter may be embodied in other ways, may include different elements or steps, and may be used in conjunction with other existing or future technologies. This description should not be interpreted as implying any particular order or arrangement among or between various steps or elements except when the order of individual steps or arrangement of elements is explicitly described.

(28) According to one aspect of the present invention, a frequency synthesis technique is utilized to perform automatic voltage regulation to maintain the output voltage, rapidly recover from voltage drops due to heavy transients, and maintain a voltage to frequency (V/Hz) ratio under varying output loads. In one aspect of the frequency synthesis technique, a higher multiple frequency of a reference signal corresponding to the generator's desired output frequency is produced and phase locked to the reference signal by the use of a Phase Lock Loop (PLL) in conjunction with a frequency divider. The higher frequency signal is a multiple N of the reference frequency, where N is the division factor of the frequency divider. In one example, to regulate a generator configured to operate at 60 Hz, the frequency of the voltage controlled oscillator (VCO) of the PLL is 240 Hz and N is 4. FIG. 16 is an oscillogram illustrating the relationship between a line sync signal V.sub.LS (upper trace) and the PLL frequency (lower trace) in this example.

(29) The frequency of the output voltage of the generator is obtained by sampling the output voltage, such as with a transformer or other line sensing circuit. The sensed output voltage frequency is then compared to a reference voltage V.sub.REF, which is a stable temperature compensated DC voltage reference. In the examples described below, V.sub.REF is fixed at 6.8 Volts, but other reference voltage levels may be utilized in other embodiments without departing from the teachings of the present invention. The output of the comparator is the line sync signal (V.sub.LS), which is a square wave signal that is in phase with the output voltage of the generator. The V.sub.LS signal produced is a fast, clean and in-phase square wave AC voltage signal representing the generator's output phase. This signal is fed into the PLL voltage comparator to produce a flexible Volts/Hz capability that stems from using the PLL as a frequency to voltage converter.

(30) This PLL based frequency synthesis technique can reduce delay in the response of the AVR to transient conditions in the output voltage to improve recovery from transient conditions. The frequency synthesis technique may also permit a higher chopper frequency to be used in a DC modulator circuit that drives a power section to produce the field current in the field winding of the generator rotor, which may further reduce feedback delay in the AVR. The frequency synthesis technique may also produce a feedback control signal with a reduced noise level, such as the example shown in FIG. 19, which facilitates the introduction of derivative feedback. Note that in some high power applications, a three phase, full wave, one or two quadrant, depending upon the operational requirements, SCR bridge rectifier circuit may be employed in place of the chopper circuit. Response time may increase, e.g. 2.8 msec versus 1 msec, for the chopper function and the response may be less linear, but the long time constants generally associated with large, high power machines may permit such a substitution without departing from the teachings of the present invention.

(31) FIG. 3 is a block diagram that illustrates one embodiment of a simplified AVR circuit 100 illustrating some aspects of the present invention. The output voltage of the generator V.sub.GEN is input to DC power supply circuit 102, which then generates: a DC supply voltage VAC to power components in AVR circuit 100; a stable DC reference voltage V.sub.REF; and a full wave rectified signal V.sub.RS that reflects V.sub.GEN.

(32) The output voltage of the generator V.sub.GEN is also input to sampling circuit 110, which samples the output voltage V.sub.GEN and compares it to V.sub.REF in order to produce line sense voltage signal V.sub.LS, which represents the frequency of V.sub.GEN. The output of the comparison is a square wave signal that is in phase with V.sub.GEN. FIG. 4 is a graph illustrating the signal waveform of V.sub.LS in response to oscillations in V.sub.GEN with respect to V.sub.REF, which is 6.8 V is the example shown.

(33) V.sub.LS and V.sub.RS are input into PLL circuit 112 of FIG. 2, which uses V.sub.LS to identify the peaks in V.sub.RS and sample the magnitude of those peaks in order to produce control signal V.sub.CONTROL, which represents the absolute magnitude of the voltage of V.sub.GEN. Note that V.sub.CONTROL is a DC level signal that can be compared to the DC reference voltage V.sub.REF in order to generate a clean and precise error signal, which is important for regulating under heavy transient overloads to improve the transient response of the AVR control loop.

(34) PLL circuit 112 also produces phase error voltage signal V.sub.OP, which is the output from a voltage controlled oscillator (VCO) in the PLL and represents a highly responsive voltage to frequency conversion signal that reflects variations in the frequency of V.sub.GEN. V.sub.OP may be transformed into a voltage to Hertz control signal V.sub.VH that engages when the frequency of V.sub.GEN drops below a selected threshold, e.g. the 60 Hz operating frequency, to increase the frequency back to the selected operating frequency.

(35) V.sub.CONTROL, V.sub.REF, V.sub.VH and a damping signal V.sub.DAMP are all input to error amplifier 116, which subtracts the V.sub.CONTROL, V.sub.VH and V.sub.DAMP voltages from V.sub.REF in order to produce an error voltage signal that is amplified and output as a duty cycle modulator control voltage V.sub.DCMOD. The voltage level of V.sub.DCMOD is input to duty cycle modulator circuit 120, which may also be referred to as a chopper. The voltage level of V.sub.DCMOD controls the duty cycle of a square wave signal having a predetermined frequency, e.g. 1 KHz, that is output as V.sub.FIELD. V.sub.FIELD drives power section or exciter 130 to produce I.sub.FIELD, which is the current in the rotor field for generator 140. V.sub.FIELD is fed back through stabilizer 122 to produce the damping signal V.sub.DAMP, which is an internal negative feedback path that dampens the level of modulation to maintain the stability of the control loop.

(36) For automatic voltage regulation, if the voltage of V.sub.GEN drops, such as due to introduction of a heavy transient load, then the peak magnitudes of V.sub.RS will drop, which is sampled by PLL circuit 112 and reflected in the voltage level of V.sub.CONTROL. This, in turn, will impact the voltage level of V.sub.DCMOD causing the duty cycle of V.sub.FIELD to increase, thereby increasing the field current I.sub.FIELD, which, in turn, increases the voltage level of V.sub.GEN. As the voltage level of V.sub.GEN returns to its preselected level, e.g. 120 VAC, as reflected by V.sub.RS, V.sub.CONTROL will return to its steady state level causing V.sub.DCMOD to return to steady state and reducing the duty cycle of V.sub.FIELD to its steady state level.

(37) Likewise, for frequency control, if the frequency of V.sub.GEN drops, this will be reflected in the voltage level of the phase error signal V.sub.OP. If the frequency drop exceeds a preselected threshold, then voltage to Hertz circuit 114 will modify the voltage level of V.sub.VH, which will cause error amplifier 116 to modify V.sub.DCMOD to decrease the duty cycle of V.sub.FIELD and increase the frequency of the generator output voltage V.sub.GEN. As the frequency of V.sub.GEN returns to the selected operating frequency, V.sub.OP and, thus, V.sub.VH return to steady state levels resulting in V.sub.DCMOD reducing the duty cycle of V.sub.FIELD to a steady state consistent with the operating frequency.

(38) In accordance with one aspect of the present invention, some embodiments may permit adjustment of the generator output voltage within a given range, typically +/10% around a nominal voltage, i.e. 120 VAC line to ground, and maintain the selected voltage in spite of load changes within a specified steady state regulation specification, such as below 3%. This is achieved by generating a difference or error signal V.sub.CONTROL that results from the difference between a reference DC voltage and the sampling of the output voltage of the generator.

(39) In accordance with another aspect of the present invention, the generation of a fast responding clean error signal permits some embodiments of the present invention to regulate under heavy transient overloads. The significance of a high quality error signal may be observed from the basic relationship that links the error signal to the output voltage of the generator. In simplified form, this relationship may be expressed as: V.sub.GEN=H(s)*V.sub.ERROR, where H(s) is the open loop transfer function for the combination of the error amplifier, demodulator, exciter, and generator components.

(40) FIG. 5 is a block diagram illustrating in greater detail an example of a transfer function 150 representing a portion of the circuit of FIG. 3. At 152, the clean error signal V.sub.CONTROL obtained from sampling the output voltage V.sub.GEN is compared to the reference voltage V.sub.REF in order to produce a voltage signal V.sub.ERROR representing the difference between the desired output voltage, which is determined by magnitude of V.sub.REF, and the actual output voltage of V.sub.GEN. Note that by changing V.sub.REF, the desired output voltage for the generator system may be adjusted. This represents the outer control loop that provides proportional feedback for regulating the generator output voltage, and which includes the amplifier gain 154, the duty cycle modulator gain 156, the exciter's gain and delay 160, the generator's gain and delay 162 and the sensor's delay 164. An inner control feedback loop introduces a stabilizer gain to produce V.sub.DAMP by introducing a zero to the transfer function.

(41) In FIG. 5, the open loop transfer function, that is the Transfer Function with the proportional feedback or outer loop open can be expressed as follows:

(42) $H\left(s\right)=\frac{\mathrm{Ka}*\mathrm{Kb}*K\mathrm{mod}*\mathrm{Kex}*\mathrm{Kgen}*\left(I+\mathrm{Td}\right)}{\left(I+\mathrm{Te}\right)\left(I+\mathrm{Tg}\right)}$

(43) wherein:

(44) Te=Exciter's time constant;

(45) Tg=Generator's time constant;

(46) Ka, Kb=Gains of amplifiers in the error amplifier circuit;

(47) Kmod=Gain of the duty cycle modulator;

(48) Kex=Gain of the exciter;

(49) Kgen=gain of the generator; and

(50) Td is the zero that is introduced by the derivative feedback of the inner loop.

(51) Td represents an amount of derivative control that used in proportion to the ordinary proportional control provided by the outer loop and that may be adjusted.

(52) Accounting now for the introduction of V.sub.DAMP to the summer 152, as well as an optional V.sub.DROOP signal to control load current, V.sub.ERROR can be represented as follows:
V.sub.ERROR=V.sub.REFV.sub.CONTROLV.sub.DAMPV.sub.DROOP

(53) Here, V.sub.REF is an adjusted value of V.sub.REF that results from the output voltage control. For an example, see the voltage signal VRO of the error amplifier circuit 550 of FIG. 12, which is obtained by adjusting a potentiometer that is the generator output voltage control. In this example, V.sub.REF is a temperature compensated voltage reference of 6.8 Volts. In addition, it is assumed, in this example, that the time constants associated with the error amplifier and power sections are well below time constants Te and Tg. Examples of reference values reflecting these assumptions is, in milliseconds, 70<Te<500 and 400<Tg<1000. Table 1 below illustrates an example of the gain calculations to achieve a 1% steady state regulation specification:

(54) TABLE-US-00001 TABLE 1 Steady State Regulation Calculations Units Required Regulation No load to Full load 1% Max Peak Output Change 120 VAC 1% Regulation 1.70 Volts Proportional feedback loop constant Ksensor 0.032 Maximum Field excitation Voltage 100.0 Volts Error signal magnitude at 1% Regulation 0.055 Volts Total Gain required 1831 DC Modulator gain at 160 V max output chopper 64 voltage, DC = 1 Required Combined Error Amplifier Gain 35 Chosen Combined Gain for error amplifiers 36

(55) V.sub.DAMP is a voltage signal corresponding to the derivative of an attenuated voltage, where Kd is the attenuating constant in this example, that feeds the field of the exciter V.sub.FIELD. For example, the error amplifier circuit of FIG. 12 shows V.sub.FIELD passing through an adjustable attenuation network in order to produce V.sub.DAMP. V.sub.DROOP is an optional signal voltage that is a function of the output current of the output generator and is included here to demonstrate how droop control may be readily added to the circuit.

(56) From the Transfer Function of FIG. 5, it may be observed that if the V.sub.ERROR signal is zero, then no excitation will be available to the primary field of the exciter. In order to maintain regulation at steady state, the combined gain of the error amplifier and DC Modulator circuits is relatively high. The reference values provided in FIG. 5 and Table 1 above illustrate one example of values that produce sufficient gain for sufficient steady state operation.

(57) In FIG. 5, the outer loop from the generator output through frequency synthesis transfer block 164 to summer 152 provides Proportional Feedback from the sensed generator output, which results in generation of V.sub.CONTROL. The error signal V.sub.ERROR that results from the proportional feedback is a clean DC level signal. The inner loop from the output of DC modulator 156 through stabilizer block 158 produces the V.sub.DAMP signal, which is subtracted at summer 152 and provides Derivative Feedback from the field voltage V.sub.FIELD. The amount of derivative feedback is controlled by adjusting the value of Kd in stabilizer block 158, which also adjusts the value of Td as discussed above. This is commonly known as Damping Control in commercial AVRs. In the example discussed herein, the DC modulator block 156 is implemented as a chopper that operates at 1 Khz and is driven by a duty cycle modulator circuit. For example, as illustrated in FIGS. 11 and 14, the chopper 540 is an Insulated Gate Bipolar Transistor (IGBT) or Power MOSFET (e.g. IRF740) that is driven by a Duty Cycle modulator chip 520 (e.g. LM3524D). The resulting chopper signal is a modulated square wave signal V.sub.FIELD, which drives the exciter's field. The higher chopper frequency in this example, when compared to standard 60 Hz Phase Control silicon controlled rectifier (SCR) circuits, provides for a smoother Field current waveform and minimizes the time delay associated with the power section. For example, the time delay with the IGBT chopper 540 at 1 khz will be less than 1 milliseconds (msec). For a Full Wave single phase SCR phase control circuit, the delay could be as high as 8.3 msec.

(58) In order to generate the V.sub.CONTROL signal, the examples herein sample the peaks of the full rectified output voltage of the generator's output voltage. In the detailed example described herein with respect to FIG. 8, the output voltage is sampled through a transformer 302 followed by a two resistor network (RI and R2) that yields a peak voltage of 6.8V as the peak voltage of V.sub.RS from a generator output voltage V.sub.GEN of 120 VAC. The sampling of the full rectified peaks is accomplished by applying a sampling pulse that is synchronized with the peaks and is applied to a Sample and Hold circuit, such as the sample and hold circuit 600 shown in FIG. 13.

(59) In the example of FIG. 13, a pulse is generated in response to V.sub.Q1 and closes switch Sw1 for the length of the pulse (i.e 100 sec). V.sub.Q1 passes through a sample pulse generation circuit 610 that has parallel signal pathways each constructed using NAND gates and high pass filters, wherein the received V.sub.Q1 pulse travels at different speeds through each signal pathway. The difference in propagation time through the signal pathways results in a 100 microsecond pulse in the V.sub.QS signal that is synchronized to the peak of the V.sub.RS signal. The V.sub.QS signal drives switch Sw1 in holding circuit 620 to close for 100 microseconds to sample the V.sub.RS signal, which is a DC signal that is held in capacitor C23 and produces V.sub.CONTROL.

(60) In this example, the Sample and Hold (S/H) circuit 600 is sampling the peaks for 100 microseconds (secs) and holding the sampled value for 8.3 milliseconds, i.e. 180 degrees or half a cycle at 60 Hz, until another peak arrives. The resulting V.sub.CONTROL signal for a constant generator output voltage will be a substantially stable DC voltage level. Voltage variations in the generator output voltage level, in this example, are sampled and updated every 8.3 milliseconds. FIG. 6 is a waveform diagram that illustrates the sampling pulses produced in sampling signal V.sub.QS in response to V.sub.Q1. As FIG. 6 illustrates, the rectified voltage signal V.sub.RS is sampled for 100 sec at the peaks of the V.sub.RS signal and held for 8.3 msec. In practice, the V.sub.RS waveform may become distorted due to the sampling circuitry, such as a sampling transformer. However, the transient performance of an AVR in accordance with certain aspects of the present invention would not be significantly affected because the sampling of the rectified output voltage V.sub.RS occurs for a relatively small interval of time at substantially the peak of the voltage waveform. As a result, the control signal V.sub.CONTROL is resistant to distortion, such as the harmonic distortion introduced by a sampling transformer or the generator's output voltage. Predictable sources of distortion can be offset by adjusting the output voltage control VRO, which is set at 6.8 Volts in this example, to compensate for the distortion. A voltage change at the generator's output will change the DC level of V.sub.CONTROL.

(61) In this aspect of the present invention, the approach to designing the Transfer Function is to reduce the time response associated with the AVR control circuitry in the proportional feedback control loop to be substantially less, e.g. by a factor of approximately 10 to 40 times, than the time constants associated with the Exciter (Te) and the Generator (Tg). The error amplifier time constant, e.g. Ta and Tb, provide lead compensation to the error amplifier section. In this example, Ta corresponds to Amplifier 560 and Tb corresponds to Amplifier 570 in the error amplifier 550 of FIG. 12. Tcs and Tcd correspond to low pass filters in the derivative feedback network 580 of FIG. 12 and are significantly less than Te and Tg and are for the purpose of filtering out noise, which provides a clean damping signal V.sub.DAMP at the summing node.

(62) The sensor time constant Td has a delay of less than 8.3 msec. This removes a root of the characteristic equation normally associated with the voltage sensor and replaces it with a 8.3 msec time delay. The use of time delays in transfer functions is understood by those of skill in the art. Hence, the complete Transfer Function M(s) for an AVR in accordance with an aspect of the present invention can be described in terms of H(s), as defined above, as follows:
M(s)=H(s)/(1+H(s)K.sub.SENSOR*e.sup.ds),

(63) where ds represents the maximum time delay resulting from the frequency synthesis and sample and hold circuits described herein.

(64) The response of the AVR is fast enough to produce the damping control signal V.sub.DAMP generated in the error amplifier circuit 550 shown in FIG. 12. V.sub.DAMP improves the stability margin by adding a zero in the transfer function. Those of skill in the art will understand the use of derivative feedback effect to a closed loop transfer function to compensate for the roots introduced by Te or Tg, which typically have time constants on the order of 70 to 500 msec and against the disturbances introduced by load changes thus maintaining stability. For example, see Kuo, Benjamin, Automatic Control Systems, 3d Edition 1975; Vleeshouwers, Derivation of the Model of the Exciter for Synchronous Machine, Einhoven University of Technology EUT Report 92-E-258, June 1993; Glover et al., Power Systems Analysis and Design, 3rd edition, Brooks/Cole (2002).

(65) FIG. 7 is a block diagram illustrating one example of an automatic voltage regulator circuit 200 in accordance with the present invention, which is configured to regulate an output voltage V.sub.GEN of a generator electrically coupled to the AVR 200 by controlling the current provided to a field winding 240 for the exciter of the generator.

(66) A DC voltage power supply 202 is configured to receive V.sub.GEN and produce a 12 volt DC regulated supply voltage, which is the power supply to other components in AVR 200, full wave rectify V.sub.GEN to produce rectified voltage signal V.sub.RS, and produce a stable reference voltage V.sub.REF, which is 6.8 V in this example and is corresponds to the steady state operating voltage level of V.sub.GEN for which AVR 200 is designed. Other steady state operating voltage levels may call for different reference voltage levels. A line sampling circuit 210 is also configured to receive V.sub.GEN and compare it to V.sub.REF in order to generate line sync signal V.sub.LS, which is a square wave with pulses synchronized to the oscillation of the generator output voltage V.sub.GEN. FIG. 8 shows an example of a detailed embodiment of the circuitry for DC power supply 202 and line sampling circuit 210.

(67) Quadrature signal generator circuit 220 includes a phase locked loop (PLL) circuit that locks onto the frequency of line sync signal V.sub.LS and, using a lock frequency that is a multiple of the desired generator frequency, produces a pair of square wave signals V1 and V2 that are 90 out of phase with one another and synchronized with V.sub.LS. Quadrature sync circuit 222 uses V1 and V2 to generate a quadrature signal V.sub.Q1 that is in quadrature with V.sub.LS, i.e. phase shifted by 90. V.sub.Q1 is a square wave signal aligned to the peaks of the generator output voltage V.sub.GEN. V.sub.Q1 is fed to sample and hold circuit 226, which transforms V.sub.Q1 into a short duration pulse, e.g. 100 sec, aligned with the peaks of the generator output voltage V.sub.GEN that sample and hold circuit 226 uses to sample the peak voltages of the rectified voltage signal V.sub.RS, which represents the absolute magnitude of V.sub.GEN. Sample and hold circuit 226 samples the peaks of V.sub.RS and outputs generator control signal V.sub.CONTROL, which is a DC voltage signal that represents the current voltage level of V.sub.GEN. FIG. 17 is an oscillogram illustrating the relationship between V.sub.LS (upper trace) and V.sub.Q1 (lower trace) in this example.

(68) Quadrature signal generator circuit 220 also outputs a phase error signal V.sub.OP from the PLL that is an error output voltage signal that effectively converts the phase difference between the V.sub.LS signal and the oscillating frequency of the PLL to a voltage signal that can be used by Voltage to Hertz control circuit 224 to control the frequency of the generator. Voltage to Hertz control circuit 224 utilizes the DC phase error signal V.sub.OP and utilizes the reference voltage signal V.sub.REF to produce a voltage to frequency control signal V.sub.VH that represents a phase correction needed to maintain the desired frequency of V.sub.GEN.

(69) Error amplifier section 230 receives DC voltage signals V.sub.CONTROL, V.sub.VH, V.sub.REF and damping feedback voltage V.sub.DAMP. Error amplifier 230 subtracts V.sub.CONTROL, V.sub.VH and V.sub.DAMP from V.sub.REF, which determines the desired output voltage level, in order to produce duty cycle modulation signal V.sub.DCMOD. Note that droop control may be readily obtained in this example by providing a DC voltage signal for droop control that is also summed in error amplifier 230. V.sub.DCMOD is a DC voltage control signal that reflects the reference voltage selected to determine the desired output voltage level of V.sub.GEN, the voltage level of V.sub.GEN sensed at the generator output, the phase of the sensed voltage signal, and damping control for stability. At steady state, these voltage signals will remain substantially stable.

(70) V.sub.DCMOD drives duty cycle modulator 232, which, in this example, includes an oscillator that provides a chopper frequency, e.g. 1 kHz, used to produce field voltage control signal V.sub.FIELD. V.sub.FIELD is a square wave signal oscillating at the chopper frequency where the duty cycle of the square wave is controlled by V.sub.DCMOD. For example, when output voltage level of V.sub.GEN drops, e.g. in response to introduction of a transient load, this impacts V.sub.CONTROL and, in turn, causes V.sub.DCMOD to increase the duty cycle of V.sub.FIELD. The increased duty cycle of V.sub.FIELD increases the current in the field winding 240 of the generator causing the output voltage level of the generator to increase. Similarly, if the frequency of V.sub.GEN drops, then this will be reflected in V.sub.VH, which will cause V.sub.DCMOD to decrease the duty cycle of V.sub.FIELD, which also increases the frequency of V.sub.GEN in order to maintain the output frequency. V.sub.DAMP provides an internal stabilization control for the AVR circuit. Power section 234 includes high current devices that converts V.sub.FIELD into the field current in field winding 240.

(71) Synchronization is important for sampling the voltage level of V.sub.GEN so that the sampling pulses are substantially aligned with the peaks of V.sub.GEN, as represented in absolute terms in V.sub.RS. To maintain accuracy, synchronization should be maintained even in the event that the generator's output voltage changes in frequency, which often occurs when a transient load is introduced. In the present example, the sampling pulses of V.sub.QS are generated using a signal that is 90 deg out of phase with V.sub.LS. This signal is the quadrature signal of V.sub.LS and is labeled V.sub.Q. In an example of an implementation of quadrature synchronization circuit 222 shown in FIG. 10. Output frequency tracking capability is used to maintain a 90 degree phase shift between V.sub.LS and V.sub.Q to maintain the accuracy of sampling of the peaks of V.sub.GEN. FIG. 18 is an oscillogram illustrating the relationship between V.sub.GEN, which is represented by the sinusoidal trace, and a quadrature sampling signal, which is represented by the trace with sampling pulses aligned to the positive and negative peaks of V.sub.GEN.

(72) In the present example, the frequency synthesis approach permits the generation of a square wave signal that is synchronized with the output voltage of the generator at four times the frequency. This is the output VOP of the voltage controlled oscillator (VCO) of PLL circuit 410 in one implementation of quadrature signal generator 220 that is shown in FIG. 9. The PLL circuit 410, which is an IC 4046 in this implementation, tracks the frequency and phase of the incoming signal V.sub.LS so that the output of the VCO is in phase lock at four times the frequency of V.sub.LS. FIG. 16 is an oscillogram illustrating the relationship between V.sub.LS and the PLL output, wherein the upper trace represents V.sub.LS, which is a 60 Hz line signal in this example, and the lower trace is PLL output OUT VCO obtained at pin 4 of the PLL IC 410, which is a type 4046 integrated circuit for a phase locked loop with voltage controlled oscillator in this implementation. A 240 Hz PLL signal (460) is in lock with the 60 Hz signal. In this implementation, PLL Lock was tested to 30 Hz (120 Hz VCO frequency) and showed a linear characteristic in V/Hz.

(73) Quadrature Generator circuit 430, which is a type 4013 IC in this example, is a dual D flip flop connected so as to convert the 240 Hz signal output by the VCO to two 60 Hz signals VI and V2 that are separated by 90 degrees and are fed to the Quadrature Sync Circuit 222. Quadrature Sync Circuit 222 transforms these signals into V.sub.Q1, which is a signal separated by 90 degrees (e.g. quadrature) from V.sub.LS. FIG. 10 illustrates an example of one implementation of quadrature sync circuit 222. The relationship is illustrated in the oscillogram of FIG. 17, wherein the upper trace is V.sub.LS and the lower trace is V.sub.Q1. Quadrature signal V.sub.Q1 is separated by 90 deg from V.sub.LS, even if the frequency changes, so long as the PLL 410 in FIG. 9 holds lock.

(74) The V.sub.Q1 signal is input to Sample and Hold circuit 226, an example implementation of which is illustrated in FIG. 13. In FIG. 13, V.sub.Q1 is passed through two separate signal paths, where each path has a high pass filter, which are implemented by capacitor and resistor combinations C21/R59 and C22/R60. The second high pass filter C22/R60 delays the edge with respect to the edge passing through the first path filter C21/R59 and into a set of NAND gates that transform the two delayed signals into a short duration switching pulse in V.sub.QS. V.sub.QS controls a CMOS switch Sw1, implemented using a type 4066 IC in this example, which samples the rectified output voltage signal V.sub.RS at each peak, in this example, and holds the sampled DC voltage level using a capacitor C23 to produce the V.sub.CONTROL signal.

(75) The V.sub.QS signal produced by the NAND gates 610 is a series of pulses that are synchronized to the output voltage V.sub.GEN even if the output frequency varies with the top and bottom peaks of the generator's output voltage. FIG. 18 is an oscillogram illustrating the relationship between the line voltage V.sub.GEN, which is the sinusoidal trace, and the sampling pulses, which appear as spikes aligned with the peaks of the line voltage. V.sub.CONTROL is the result of synchronized sampling of the peaks of the full wave rectified generator's output voltage V.sub.RS. The synchronized pulses are thus applied to the sample and hold circuit of FIG. 13 in order to produce a DC voltage signal V.sub.CONTROL that represents the peak voltage level of the generator's output voltage V.sub.GEN, which is substantially level when V.sub.GEN is a constant voltage. In this example, V.sub.QS samples V.sub.RS every 8.3 msec.

(76) The resulting control voltage V.sub.CONTROL, obtained in accordance with the present invention, exhibits far less ripple voltage than the signal obtained from many conventional rectified RC type AVRs. FIG. 19 is an oscillogram that compares the control voltage obtained using a conventional approach utilizing full wave rectification with an RC filter with a 20 msec time constant versus the frequency synthesis approach of the present invention. In this example, the conventional signal is illustrated by the upper trace of the oscillogram and is essentially a saw tooth waveform. The upper trace shows a single phase full wave rectified and filtered 5V DC voltage with a 1.8 V peak to peak ripple. The level line of the lower trace of the oscillogram demonstrates an example of the V.sub.CONTROL signal obtained in accordance with the present invention when the output voltage of the generator V.sub.GEN is at steady state. Note that V.sub.CONTROL, in this example, is a constant 5 VDC signal that does not exhibit the ripple that is present in the conventional control signal in the upper trace.

(77) The sampling signal V.sub.Q1 is in quadrature synchronization with V.sub.LS, which, when fed through the sample and hold circuit of FIG. 13 obtains a stable, low noise voltage signal that is updated twice in every cycle of V.sub.GEN. That is, at 60 Hz generator output frequency, the V.sub.CONTROL signal is updated every 8.3 milliseconds in the case of single phase sampling, which produces a high quality control signal compared to conventional AVR approaches that utilize full wave rectification with an RC filter. The V.sub.CONTROL signal accurately represents the amplitude of the peaks output by the generator and is updated every half a cycle (e.g. 8.3 msec at 60 Hz) even if the frequency drifts so long as synchronization is maintained. Hence, it represents a time delay that will result in a phase shift in the Transfer Function. This phase shift will be small given the fact that the frequency response of the Exciter/Generator is typically close to two decades below 120 Hz. For illustrative purposes, a typical Exciter field time constant is 80 msec and the frequency response of the exciter is 2 Hz, and the phase shift is 6 degrees at a generator's voltage output frequency of 60 Hz. (See Vleeshouvers Eindhoven University of Technology EUT report 92-D-258.)

(78) Once phase lock on the generator output signal is obtained, the VCO will produce a voltage signal that will change linearly as a direct function of the frequency of the generator output voltage V.sub.GEN. Hence, a Frequency to Voltage characteristic is achieved that can be readily utilized to produce a flexible Voltage to Hz control signal, as will now be discussed.

(79) Volts per Hertz (V/Hz) control section: The PLL design shown in FIG. 9 exhibits a voltage to frequency conversion of 80 mV/Hz in the Vop signal output by the VCO of PLL circuit 410. The Vop signal that the PLL generates is an output voltage signal that is a linear function of the reference frequency. This frequency/voltage conversion property of Vop can be readily applied to obtain a control characteristic that maintains a constant Volts/Hz ratio in spite of frequency variations, thus avoiding saturation of the electromagnetic components of the load. Preferably, this characteristic has an adjustable start frequency (i.e. the maximum frequency at which the V/Hz starts) from a maximum of 60 Hz to a minimum that is the lowest frequency expected during overload conditions.

(80) It is also useful to provide a flexible Volts/Hz capability that can be adjusted so as to best assist the recovery of the prime mover/exciter/generator combinations in the case of a heavy transient overload. For example, it is useful to provide the ability to adjust the V/Hz ratio from 1:1 to a higher value so that the output voltage will drop faster as the prime mover speed decreases as a result of a transient overload. Additionally, the flexible Volts/Hz control capability may provide the ability to control the frequency at which the V/Hz ratio begins to adjust at a predetermined frequency below 60 Hz (usually between 59.5 Hz to 57 Hz) so as to provide effective regulation for light to moderate load changes.

(81) FIG. 15 is a circuit diagram illustrating one example of a voltage to hertz control circuit 700 in accordance with certain aspects of the present invention. PLL VCO input voltage Vop from PLL circuit 410 in FIG. 9, which is the filtered phase error signal output by the phase detector of PLL circuit 410, is input to a voltage follower amplifier 710, which is a CA 3140 high impedance operational amplifier in the example of FIG. 15 and which reduces the loading on the VCO output. The output Vo of the voltage follower amplifier 710 is input to a voltage amplifier 720 with gain that is adjustable using variable resistor Rh. The signal input to voltage amplifier 720 is the difference between the output of the voltage follower LM358 730, which supplies a calibrated voltage Vk that is adjusted by variable resistor Ra, and the adjusted phase error output Vo from voltage follower amplifier 710. Vk is a frequency reference voltage corresponding to a desired oscillating frequency that is fed into a voltage follower amplifier 730, in order to avoid loading the frequency reference voltage Vk, and produce a calibrated voltage reference. In the example shown, Vk is set to 6.2 V and the output of the VCO in PLL 410 of FIG. 9 is also adjusted to 6.2 V by variable resistor VRf. The circuit is thus calibrated to 60 HZ because the reference voltage Vk is the same as the VCO output voltage V.sub.OP so that the voltage at the input of voltage amplifier 720 is zero.

(82) As the frequency of V.sub.GEN decreases, so does the voltage that is input to the voltage amplifier 720 and its output decreases the reference voltage fed to the control loop of FIG. 5, which decreases the output voltage V.sub.GEN of the generator. The sharpness or slope of the decrease is adjusted by adjusting resistor Rh. At Rh=0, the V/Hz ratio is 1:1. At Rh maximum, in this example, the ratio is 1:2.6. These values may be selected by design criteria to obtain the V/Hz ratio for the desired range of performance.

(83) To adjust the frequency at which the V/Hz Characteristic is applied, a CMOS switch Sw2 is utilized at the output of amplifier 720. If switch Sw2 is disconnected, then the V/Hz functionality is disabled. When Sw2 is closed, the V/Hz control functionality will take effect with the V/Hz relationship determined by Rh, as explained above. The switch Sw2 is controlled by switching voltage signal Vsw that is the output of voltage follower amplifier 732, which is implemented as amplifier 730 in the same LM358 integrated circuit in the example shown, so that the section works as a voltage comparator. This comparator compares the VCO input voltage (Vo) with a voltage reference that is adjusted by a 10 K potentiometer. The potentiometer has an adjustment range of 0.4 V so that an adjustment range of 5 V is obtained with a V/Hz characteristic of 0.08 V/Hz. When V/Hz control circuit 700 is calibrated as described above, the V/Hz functionality can be controlled to engage at any selected frequency between 60 Hz and 55 Hz. Again, this range may be modified, but it is sufficient for a 60 Hz generator since it's unlikely that the frequency of output voltage V.sub.GEN will drop below 55 Hz under normal operating conditions. In this example, the voltage to hertz control circuit 700 provides a flexible V/Hz control functionality that may be adjusted from a ratio of 1:1 to 1:2.6. Circuit 700 can be configured to activate in at a selected frequency from 55-60 Hz. The 1:2.6 V/Hz selection combined with a sharp voltage drop per Hz assists the recovery of the frequency of the prime mover of the generator.

(84) In this example, the circuit is implemented using standard CMOS integrated circuits for the digital portion, such as the quadrature generator circuit 400 of FIG. 9 and the sample and hold circuit 600 of FIG. 13. Analog circuitry is used to implement the V/Hz control circuit 700 of FIG. 15 using standard operational amplifiers. The DC modulator or chopper circuit 650 of FIG. 14 utilizes a LM3524D integrated circuit that is specifically designed for use in switching power supplies. The LM3524 circuit provides a linear characteristic for duty cycle modulation from 1% to 98% responsive to the V.sub.DCMOD voltage output from error amplifier circuit 550 of FIG. 12, where V.sub.DCMOD ranges from 1 volt to 3.5 volts. The control voltage range of 2.5 volts when the DC modulator circuit 650 has a duty cycle of 1 defines the gain of the DC modulator circuit 650. For example, a 160 volts maximum output with a 2.5 volts input range implies a gain of 64. In order to obtain a rapid transient response, this example utilizes the clean and fast responding detection signal to produce an error signal V.sub.DCMOD that is used to control an Insulated Gate Bipolar Transistor (IGBT) in the DC modulator circuit 650. The DC modulator circuit 650 operates at a frequency of approximately 1 Khz, which is well above the 60 Hz frequency of the power generator.

(85) DC modulator circuit 650 utilizes linearly controlled Duty Cycle modulation in order to control the Field Current of field 240 in FIG. 7. This approach provides improved linearity compared to conventional SCR phase control techniques. Also, the higher DC modulator frequency combined with the fact that the voltage signal that is supplied is DC capacitor filtered voltage provides a much smoother field current. Further, the low noise detection signal minimizes jitter or blinking associated with no load or very light load conditions thus reducing damping requirements for addressing the jitter. The DC voltage supply obtained from a 120V AC full wave rectified and filtered AC voltage provides 160V DC, which may provide higher field current and, therefore, more field force as compared to a conventional full wave unfiltered supply. For example, a conventional 120 VAC full wave unfiltered supply, which is normally used with a SCR phase control based system, would supply 100V DC to the Exciter's field. The filter capacitor may be eliminated in some embodiments designed for higher power and/or voltage ratings that utilize a three phase full wave rectifier to feed the DC modulator.

(86) In the power circuit 500 embodiment shown in FIG. 11, a relay with an initial delay may be used to feed an IGBT 540 in order to supply initial current to the field winding 530. An initializing circuit may be used in some embodiments to maintain the output voltage oscillating between around 130 to 135V AC until the PLL locks and takes control, which typically occurs in approximately 5 seconds. Once initialized, the generator supplies the voltage selected with the voltage adjustment control. Short circuit protection is provided for the IGBT 540 by a desaturation technique that may disconnect the IGBT in less than 8 sec in case of a stiff short. The short circuit protection combined with a standard circuit breaker, e.g. a 5 A circuit breaker, generally provides adequate protection to the automatic voltage regulator circuit. The example shown in FIG. 11 is designed to supply up to 5 Amps continuous current at 40 degrees C. ambient temperature. The performance is generally limited by the capacity of a heatsink thermally coupled to the circuit. The power circuit 500 generally dissipates 4.5 W/Amp of output current.

(87) The design as described above allows for self-starting based on residual magnetism with a minimum voltage of 4 VAC at the generator's output, which is a common requirement for emergency diesel driven generators. It is noteworthy that the starting relay is not required to handle high voltages or currents regardless of the current rating output of the AVR. Calibration upon construction and/or repair can typically be made with a four digit digital multi-meter with a 0.5% precision in DC voltage measurement, which facilitates device production. Instruments are generally not needed when an AVR is installed since only the output voltage and damping are typically adjusted.

(88) As a result of the frequency synthesis technique of the present invention, the output of error amplifier sections 116 and 230 at steady state is essentially a constant 6.2 V DC voltage with no significant ripple in the examples discussed above. The duty cycle modulation control signal V.sub.DCMOD feeding the Duty cycle modulators 120 and 232 will also be an essentially constant average value, which leads to the field current provided to the field winding for the generator being constant and substantially ripple free.

(89) FIGS. 20 and 21 are oscillograms illustrating an example of transient response for a simulation in accordance with one example of the present invention when the load on the generator output jumps from 2% to 93% of maximum generator capacity. The upper trace of FIG. 20 represents the output at pin 6 of error amplifier 560 in FIG. 12, which is a relatively noise free and fast responding error signal. The lower trace is the output of the chopper circuit, such as the circuit of FIG. 15, which drives the field of the exciter. When the chopper output in the lower trace is low, then the full forcing voltage is being supplied to the field winding. When the chopper output is high, no excitation is being supplied to the field, which is then flywheeling. When the transient load increase occurs, the V.sub.DCMOD signal goes low and then returns to its steady state through a series of ramps, which causes the chopper output to apply several bursts of pulses to the field in order to increase the output of the generator in response to the transient thereby stabilizing the generator voltage. In the oscillogram of FIG. 20, the chopper response and field excitation occur with a delay of less than 1 msec based on the error signal.

(90) FIG. 21 is an oscillogram comparing the V.sub.DCMOD error signal (top trace) to the generator output voltage V.sub.GEN (lower trace). In FIG. 21, the error signal has a delay of 8.3 msec or less and has low noise and the duty cycle of the field forcing is approximately 85% for the first 12 milliseconds of the transient of the error signal shown in FIG. 20. The exciter's field will be fully driven, e.g. 150 VDC, in less than 9.3 msec after occurrence of the transient. The fast, low noise response of the error signal combined with the high level of field forcing leads to a rapid, well damped response of the generator output voltage.

(91) The embodiments discussed herein are directed to sampling a single phase of the output voltage V.sub.GEN. If greatly unbalanced loads are expected, then other embodiments can be designed such that three phases are monitored and the resulting pulses combined at the Sample and Hold circuit. This entails no additional complexity since it is merely duplicating the line sampling and synchronization circuits three times. The sampling frequency for frequency synthesis is also tripled reducing the delay associated with voltage sensing in the outer proportional control loop to 2.8 msec, i.e. 8.3 msec divided by 3. The additional cost may be relatively modest since low cost, low power parts may be utilized.

(92) Droop control may also be implemented at low cost in some embodiments by reducing the gain of the amplifier section, which increases the error signal in order to supply an incremental load and thus provide droop control. This may lead to a degradation of the regulation specification. Droop control that does not compromise regulation performance and is capable of improving the steady state regulation generally requires precise and fast measurement of the output current.

(93) Embodiments of the AVR described above can be implemented that accurately detect the magnitude of the peak value of an AC sinusoidal variable signal and present it as a DC voltage level. By sampling the outputs of each phase through the use of current transformers, the load current can be monitored as a DC voltage level with speed and precision, which allows the load current to be closely monitored. The DC level signals thus produced will accurately represent the magnitude of the output current.

(94) The DC level current control signals may be combined in a circuit that functions similarly to the Volts/Hz control circuit discussed above. However, while the slope is directly proportional for Volts/Hz control, i.e. the excitation drops as the frequency decreases, the slope is inversely proportional for Volts/Amps control, i.e. the excitation drops as the current increases, so the circuitry is modified accordingly. This will permit the current level at which the Droop control starts to be adjusted as well as the sharpness of the Droop control response as the current output increases. Sampling and representing the output current and output voltages as DC voltage levels allows for flexible control of the generator by adjusting the field excitation, which adjusts the V.sub.ERROR equation above for summer 152 by including the V.sub.DROOP output current control. The DC levels can be readily combined in the summer to provide a fast field excitation reduction when the predetermined current control limit is reached resulting in effective droop control. In stand-alone applications, the droop control can be adjusted so as to cancel the steady state 1% regulation drop by reversing the slope of the Volts/Amps characteristic as long as the output current rating of the generator is not exceeded.

(95) It is noteworthy that A/D conversion of DC levels is very straightforward if microprocessor control is utilized in implementation of the AVR. Further optimization may be accomplished through microprocessor control using a look up table that includes specific data characterization, i.e time constants and Field Current versus Output current, of the specific synchronous generator and both the V.sub.REF and the damping constant Kd may be adjusted in such embodiments in order to efficiently control a given Prime Mover generator setup by the AVR.

(96) One of ordinary skill in the art will readily recognize that many aspects of the AVR described herein may be implemented using digital or microprocessor based technology. FIGS. 22 and 23 are control flow diagrams illustrating a microprocessor based implementation of the V/Hz control and error amplifier sections, respectively, discussed above with regard to FIGS. 12 and 15. The digital embodiments shown utilize persistent memory, such as read only memories (ROMs), to store operating data so that the data is preserved in the event. The memory may be implemented using modifiable memory, such as electrically erasable programmable read only memory (EEPROM), in order to provide an ability to modify and customize the operating data for a particular application or generator.

(97) FIG. 22 shows an example of a voltage to Hz control function 800 implemented in a digital circuit that includes a computational device, e.g. a microcontroller or microprocessor, to implement the V/Hz section 224 of FIG. 7. FIG. 22 is a control flow diagram illustrating the steps or stages of an exemplary process for voltage to hertz control that may be performed in a digital embodiment of another example of an automatic voltage regulator.

(98) Quadrature signal generator circuit 220 also outputs a voltage signal V.sub.OP from the PLL that is an error output voltage signal that effectively converts the phase difference between the V.sub.LS signal and the oscillating frequency of the PLL to a voltage signal that can be used by Voltage to Hertz control circuit 224 to control the frequency of the generator. Voltage to Hertz control circuit 224 utilizes the DC voltage signal V.sub.OP and utilizes the reference voltage signal V.sub.REF to produce a voltage to frequency control signal V.sub.VH that represents a phase correction needed to maintain V.sub.GEN at the desired frequency.

(99) At step 802, voltage signal V.sub.OP from the PLL of quadrature signal generator circuit 220 is converted from analog to digital form. V.sub.OP is an error output voltage signal that effectively converts the phase difference between the V.sub.LS signal and the oscillating frequency of the PLL to a voltage signal that may be used to control the frequency of the generator. In one example, an analog to digital converter with ten bit resolution is utilized to accommodate an input range of 10 VDC, which provides an equivalent resolution of 0.12 Hz, with a sampling rate of 200 microseconds so as to avoid excessive delay. In this example, calibration of the PLL results in V.sub.OP being 6.2 V for a generator operating at a stable frequency of 60 Hz. In the example of FIG. 9, the sensitivity exhibited by the 4046 PLL circuit 410 is 80 mv/Hz. In order to achieve a 1:1 voltage to frequency ratio, V.sub.OP is scaled by 1.26 in this embodiment. The result of the analog to digital conversion and scaling is a corresponding digital value V.sub.OPG.

(100) V/Hz slope control is determined at step 804 by multiplying V.sub.OPG by a V/Hz slope parameter obtained from operational data store 810. In this example, the operation data parameters for the particular application are selected at step 812 through a user control input selection, which includes the V/Hz, Vk reference voltage, scaling factor N, threshold frequency Fth, and the generator output voltage selection Vr. The selections may be displayed at step 814.

(101) For this example, the V/Hz parameter selected is 1.26 and Vk is 1.2. The result of steps 804 and 806 is V.sub.OPG1.261.2 to create Vf, which is scaled by N at step 808 to produce scaled frequency error signal NVf. The value of N is selected to determine the rate of the AVR's response. For example, the range for N may be from one to four. The V/Hz slope parameter, in this example, ranges from 1:1 to 2:26 V/Hz. Greater ranges may be provided in some implementations.

(102) The frequency threshold Fth is also selected to determine the frequency at which the AVR begins to apply the selected V/Hz slope. In this example, the selectable range for Fth is from 60 to 55 Hz with the corresponding value for Fth stored in frequency threshold store 830 and the values for Fth vary from 0 to 0.4 depending on the desired threshold frequency. The value of variable NVf is compared with the selected value for Fth at step 820. If Fth is not greater than NVf, then the V/Hz slope is not applied and control branches to step 822, where the value of frequency control variable M is set to steady state reference value Vk, which corresponds to 6.2V in the present example for 60 Hz operation, such that no frequency adjustment is performed and control continues to step 826. If Fth is greater than NVf, then the frequency control variable M is set to the value of Fth in order to engage frequency control at the selected threshold frequency. In other examples, a similar approach may be applied to an over frequency at which frequency control is to terminate, e.g. 65 Hz.

(103) At step 826, the value of M determined above is multiplied by the output voltage level parameter Vr, which defines the selected generator output voltage. For example, ten values may be stored in the V.sub.GEN selection store 832, e.g. a ROM or EEPROM, to permit the generator's output voltage to be selected from 110 VAC to 125 VAC in ten increments. A voltmeter showing the generators output voltage through a digital display may also be included in some embodiments of an AVR.

(104) The result from multiplying MVr at step 826 is digital frequency control signal V.sub.VHD, which is converted from a digital to analog value at 828 in order to produce frequency control signal V.sub.VH, which is output to an error amplifier, such as the error amplifier shown in FIG. 12, as the analog signal that is input to a potentiometer that control the generator's output voltage in the analog version shown. However, if the error amplifier function is implemented digitally, as shown in FIG. 23, then the voltage of the generator's output is controlled by selecting a given Vr value as explained above.

(105) Note that, in some embodiments, it is possible to implement the PLL using a number controlled oscillator (NCO) and digital filtering in place of a VCO. Sampling rates will need to be high enough to ensure low noise and jitter due to quantization error. The clock frequency used should be high enough to accommodate computation of the frequency synthesis process with a delay of less than about 3 degrees at an operating frequency of 60 Hz.

(106) FIG. 23 is a control flow diagram illustrating the steps or stages of an exemplary process 850 that may be performed in a digital circuit that includes a processor or similar device to digitally produce an error signal in a digital embodiment of another example of an automatic voltage regulator. In this example, the analog DC voltage level control signal V.sub.CONTROL output from the Sample and Hold circuit 600 of FIG. 13 is converted to a digital equivalent value at step 852 to produce V.sub.CTRLD.

(107) Note that the circuits that generate V.sub.CONTROL are a mixture of digital and analog. The frequency synthesis and synchronization circuits as well as the Sample and Hold circuit are digital, but the output V.sub.CONTROL is a DC voltage level that represents the magnitude of the generator's output voltage. In this example, the analog to digital conversion has ten bit resolution and a sampling speed of 200 microseconds. Longer sampling times will degrade the transient performance of the regulator. To reduce response time, separate microcontrollers may be utilized for the Error Amplifier and the V/Hz control process 800 of FIG. 22 in order to perform these processes in parallel and reduce execution time, though execution may need to be synchronized. The speed issue may become important because a typical encoding algorithm for the Pulse Width Modulation (PWM) operates at 1 Khz with a Duty Cycle ranging from 1% to 100% and time intervals as short as 10 microseconds may need to be accommodated.

(108) The V.sub.FIELD signal from the DC modulator circuit 650 of FIG. 14 is received and filtered at step 860. The filtering step may involve a potential divider circuit and a low pass filter with a zener diode included for protection purposes. The filtering may also involve a 1 Microfarad capacitor and 120 K resistor that provide a derivative action. The analog to digital conversion performed at step 862 involves high input impedance, in one example, in order to reduce the effect on the derivative action of the filter step 860. The input filtering and dividing function of step 860 is configured to provide an output equivalent to the lowest setting of the damping adjustment control in the analog error amplifier circuit of FIG. 12. Further, the filtering functionality of step 860 is selection to have time constants that are electrically equivalent to the V/Hz control circuit 700 of FIG. 15.

(109) At step 864, the conditioned and digitized V.sub.FIELD signal is multiplied by a damping factor D selected from damping factor store 870 by a user selection at step 872. The damping factor is selected by a user as needed to compensate for loop stability and load disturbances. In one example, ten values for D ranging from 1 to 31.6 in ten evenly spaced increments are stored in a ROM and selected by the user by a control, such as up down pushbuttons, with a display that indicates the value selected, i.e. D=10 means multiply by 31.6. The result of the multiplication at step 864 is digital damping signal V.sub.DMO.

(110) At step 854, V.sub.CTRLD is subtracted from V.sub.DMO and the result multiplied by a predetermined Gain value at step 856, in this example, where a Gain value of 40 is used, which is equivalent to the combined gain of the amplifiers in error amplifier circuit of FIG. 15. The output of gain block 856 is then PWM encoded at step 858 to produce the V.sub.DCMOD signal that is output to a duty cycle modulator, such as duty cycle modulator circuit 232, which, in turn, drives the power section 234 in order to generate the field current I.sub.FIELD for the field winding.

(111) FIG. 24 depicts a computing device 900 that includes a bus 910 that may directly or indirectly couple all or some of the following devices: memory 912, one or more processors 914, one or more presentation components 916, input/output ports 918, one or more graphics processing units (GPUs) 917, input/output components 920, and an illustrative power supply 922. The bus 910 represents what may be one or more busses (such as an address bus, data bus, or combination thereof).

(112) Although the various blocks of FIG. 24 are shown with lines for the sake of clarity, in reality, delineating various components is not so clear, and metaphorically, the lines would be more accurately be grey and fuzzy. For example, one may consider a presentation component such as a display device to be an I/O component. Also, processors have memory. In addition, GPUs can have their own internal busses and independent memory to the main system memory. Not all of the components shown in FIG. 24 are needed to implement certain aspects of the present invention. For example, if no display is implemented, then the presentation components 916 and GPU 917 may not be needed. Likewise, if no input/output functionality is implemented, then components 918 and 920 may not be needed. Power supply 922 may be the same supply utilized to support the analog components. And many of the components shown may be combined in microcontroller devices, which are suitable for certain embodiments of certain aspects of the present invention. One of ordinary skill in the art will readily recognize that a wide variety of devices and systems having processing capability may be utilized in certain embodiments without departing from the scope of the present invention.

(113) The computing device 900 typically includes or can operate with a variety of computer-readable media. By way of example, computer-readable media may includes Random Access Memory (RAM); Read Only Memory (ROM); Electronically Erasable Programmable Read Only Memory (EEPROM); flash memory or other memory technologies; Compact Disc Read-Only Memory (CDROM), Digital Versatile Disks (DVD) or other optical or holographic media; magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to encode and persistently store desired information for a sufficient duration of time to allow the information to be accessed by computing device 900 for use in certain embodiments.

(114) The memory 912 includes computer-readable media in the form of volatile and/or nonvolatile memory. The memory 912 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state memory, hard drives, optical-disc drives, etc. The computing device 900 includes one or more processors that read data from various entities such as the memory 912 or I/O components 920. Presentation component(s) 916 present data indications to a user or other device. Exemplary presentation components 916 include a display device, speaker, printing component, vibrating component, etc.

(115) The GPU 917 is typically dedicated to processing and rendering data related to graphics, but can be manipulated to process other data and command types. GPUs 917 are often integrated into, or installed on a presentation component 916, such as a video card, or are integrated into, or installed on a motherboard, main circuit board, or logic board of the computing device 900. In an embodiment, the central processing unit, (CPU) provides the functions of a GPU 917 for the computing device 900. I/O ports 918 allow the computing device 900 to be logically coupled to other devices including I/O components 920, some of which may be built in.

(116) Note that in the analog example discussed above, output scaling was done to accommodate the LM3424D circuit 660 of the Duty Cycle modulator circuit 650 of FIG. 14, which has an input range of 1 to 3.5 Volts in order to obtain duty cycle control from 1% to 100%. In one example, the PWM encoding function 858 has to emulate the performance of the LM3424D. Alternatively, the input signal to PWM block 858 may be fed to a digital to analog converter to convert it an analog voltage signal that may be input to an LM3424D circuit.

(117) Embodiments of an AVR as discussed herein may be implemented digitally. Digitization may also provide a means to display the values of the key variables under control, such as V/Hz slope, voltage threshold, damping, and output voltage. It may also provide for adjustment of these variables via a user interface, such as up down pushbutton functionality or graphical user interface control, which may be readily implemented by well-known user interface functionality. A digital implementation may also facilitate remote digital control of the AVR and display of operating parameters and data of a remote AVR.

(118) The examples above demonstrate that a frequency synthesis approach to automatic voltage regulation combined with sample and hold circuitry can effectively capture and convert a peak value of an AC sinusoidal generator output voltage to an accurate DC voltage control with a response time of one half of the period of the frequency of the generator output signal being measured and regulated. This approach produces a responsive, low-noise and precise error signal for a proportional control loop of an AVR. By using an IGBT or PMOS switch chopper, the time constants of the AVR and the time delay in signal detection may be significantly reduced, e.g. by a factor of 10 to 40 times, below the time constants typically associated with conventional synchronous generators. Significant improvements in responsiveness and precision control in transient response may be achieved while maintaining stability and steady state regulation, e.g. approximately 1% no load to full load. Additionally, the frequency versus Hz linear characteristic readily available from the frequency synthesis approach lends itself to use as an effective and flexible implementation of a Volts/Hz control characteristic for handling heavy transient loads in stand-alone generator operation. By monitoring the output currents using frequency synthesis, e.g. converting the peak values of the output currents to DC voltage levels, an adjustable droop control may be added to facilitate parallel generator operation as part of a power system.

(119) It will be understood by one of ordinary skill in the art that, while the embodiments of the invention described herein are generally designed for 60 Hz at 120 VAC line to ground and 208 VAC line to line voltage generator output, the invention can also be applied to operate at 50 Hz with minor recalibration. Different voltages may be obtained by changing transformer primary voltage ratings. Additionally a selector switch may be added to select between 60 Hz and 50 Hz. A wide range of embodiments of the invention maybe be implemented utilizing the power ratings of modern Power Semiconductors and of transformer selection for different voltages (i.e. 120, 208, 440) VAC.

(120) It should also be understood that the present invention as described above can be implemented in the form of control logic using computer software in a modular or integrated manner. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will know and appreciate other ways and/or methods to implement the present invention using hardware and a combination of hardware and software.

(121) Any of the software components, processes or functions described in this application may be implemented as software code to be executed by a processor using any suitable computer language such as, for example, Java, C++ or Perl or using, for example, conventional or object-oriented techniques. The software code may be stored as a series of instructions, or commands on a computer readable medium, such as a random access memory (RAM), a read only memory (ROM), a magnetic medium such as a hard-drive or a floppy disk, or an optical medium such as a CD-ROM. Any such computer readable medium may reside on or within a single computational apparatus, and may be present on or within different computational apparatuses within a system or network.

(122) All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and/or were set forth in its entirety herein.

(123) The use of the terms a and an and the and similar referents in the specification and in the following claims are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms having, including, containing and similar referents in the specification and in the following claims are to be construed as open-ended terms (e.g., meaning including, but not limited to,) unless otherwise noted. Recitation of ranges of values herein are merely indented to serve as a shorthand method of referring individually to each separate value inclusively falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., such as) provided herein, is intended merely to better illuminate embodiments of the invention and does not pose a limitation to the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to each embodiment of the present invention.

(124) Different arrangements of the components depicted in the drawings or described above, as well as components and steps not shown or described are possible. Similarly, some features and subcombinations are useful and may be employed without reference to other features and subcombinations. Embodiments of the invention have been described for illustrative and not restrictive purposes, and alternative embodiments will become apparent to readers of this patent. Accordingly, the present invention is not limited to the embodiments described above or depicted in the drawings, and various embodiments and modifications can be made without departing from the scope of the invention.