DEVICE FOR OPERATING PASSIVE INFRARED SENSORS

Abstract

A system for measuring a sensor having two terminals includes first and second transistors with first and second control signal inputs connected to the sensor terminals. The system further includes a current divider including a reference current input, a current divider control input and first and second current outputs connected to the first and second transistors. First and second load circuits are connected to the first and second transistors at first and second differential output nodes. First and second integrating circuits are connected to the first and second differential output nodes. A comparator is driven by first and second differential output nodes. The comparator output controls a digital integrator. A value of a current divider control signal driving the current divider control input depends at least indirectly from the digital integrator.

Claims

1.-18. (canceled).

19. A system for converting a differential analog signal into a digital signal comprising: first and second differential inputs; first and second differential outputs; a differential amplifier including: a first transistor including a first terminal, a second terminal and a third terminal, the first terminal being a first transistor control terminal and connected to the first differential input and the third terminal being connected to the first differential output; a second transistor including a fourth terminal, a fifth terminal and a sixth terminal, the fourth terminal being a second transistor control terminal and connected to the second differential input and the sixth terminal connected to the second differential output; a current divider including a reference current input, a control input, a first current divider output and a second current divider output, wherein the first current divider output is connected to the second terminal of the first transistor and the second current divider output is connected to the fifth terminal of the second transistor; a reference current source connected to the reference current input; a first load circuit connected to the first differential output; and a second load circuit connected to the second differential output; and a first integrating circuit connected to the first differential output, and configured to integrate a first differential output signal; a second integrating circuit connected to the second differential output, and configured to integrate a second differential output signal; a comparator including a first comparator input, a second comparator input and a comparator output, wherein the first comparator input is connected to the first differential output and the second comparator input is connected to the second differential output; and a digital integrator having a digital integrator input and a digital integrator output, wherein the digital integrator input is driven by the comparator output; wherein: a value of a current divider control signal driving the current divider control input depends from the first digital integrator output.

20. The system of claim 19, wherein: the first and second load circuits include respectively first and second load resistors configured to provide a load to the respective first and second differential outputs.

21. The system of claim 19, wherein: the first and second load circuits include respectively first and second load current sources configured to provide a load to the respective first and second differential outputs.

22. The system of claim 19; wherein the current divider further includes: a resistor string including a plurality of resistors arranged in a series configuration including a plurality of taps, the plurality of taps including the first current divider output on a first end of the resistor string, the second current divider output on a second end of the resistor string, and a plurality of middle taps arranged respectively between pairs of adjacent resistors in the resistor string; and an analog multiplexer arranged to connect one of the plurality of taps to the reference current input, the one of the plurality of taps selected based on the value of the current divider control signal.

23. The system of claim 19, wherein: the first and second integrating circuits include respectively first and second integrated filters.

24. The system of claim 19, wherein: the first and second integrating circuits include respectively first and second integration capacitors.

25. The system of claim 19; wherein: the digital integrator includes an up/down counter; and a value of the comparator output controls a direction of counting of the up/down counter.

26. The system of claim 25, wherein: a rate of at least one of incrementing and decrementing the up/down counter is predetermined.

27. The system of claim 25, wherein: a rate of at least one of incrementing and decrementing the up/down counter is programmable.

28. The system of claim 19, further comprising: a digital filter having a digital filter input and a digital filter output; wherein: the digital integrator output is coupled the input to the second digital filter.

30. The system of claim 19, wherein the digital integrator input enables an integration by the digital integrator in a first state and disables the integration of the digital integrator in a second state.

31. The system of claim 26, wherein the digital integrator control input enables an incrementing or decrementing of the up/down counter in a first state and disables the incrementing or decrementing of the up/down counter in a second state.

32. A system for converting a differential analog signal into a digital signal comprising: first and second differential inputs; first and second differential outputs; a differential amplifier including: a first transistor including a first terminal, a second terminal and a third terminal, the first input terminal being a first transistor control terminal and connected to the first differential input and the third terminal being connected to the first differential output; a second transistor including a fourth terminal, a fifth terminal and a sixth terminal, the fourth terminal being a second transistor control terminal and connected to the second differential input and the sixth terminal connected to the second differential output; a current divider including a reference current input, a control input, a first current divider output and a second current divider output, wherein the first current divider output is connected to the second terminal of the first transistor and the second current divider output is connected to the fifth terminal of the second transistor; a reference current source connected to the reference current input; a first load circuit connected to the first differential output; and a second load circuit connected to the second differential output; and a first integrating circuit connected to the first differential output; a second integrating circuit connected to the second differential output; a comparator including a first comparator input, a second comparator input and a comparator output, wherein the first comparator input is driven at least indirectly by the first differential output and the second comparator input is driven at least indirectly by the second differential output; and a digital integrator having a digital integrator input and a digital integrator output, wherein the digital integrator input is driven by the comparator output; wherein: a value of a current divider control signal driving the current divider control input depends at least indirectly from the digital integrator output.

33. The system of claim 32; wherein the current divider further includes: a resistor string including a plurality of resistors arranged in a series configuration including a plurality of taps, the plurality of taps including the first current divider output on a first end of the resistor string, the second current divider output on a second end of the resistor string, and a plurality of middle taps arranged respectively between pairs of adjacent resistors in the resistor string; and an analog multiplexer arranged to connect one of the plurality of taps to the reference current input, the one of the plurality of taps selected based on the value of the current divider control signal.

Description

DESCRIPTION OF THE DRAWINGS

[0033] The measurement circuit is explained with reference to the accompanying diagrams.

[0034] FIG. 1 illustrates the fundamental components of a passive infrared detector in accordance with the principles of the present measurement circuit. The device consists of a passive infrared detector (PIR) that is linked to a discharge circuit R.sub.G. The objective of this discharging circuit is to discharge the PIR detectors and to maintain the subsequent -converter () at a favorable operating point without impacting the system dynamics.

[0035] The -converter () converts the signal received from the discharge circuit into a first digital signal, on the first bus, which has a first bus width (no. of bits). The subsequent digital filter (DF) filters the signal of the first bus and forwards the data, with a higher resolution, via an output bus (Out). Accordingly, the output bus Out typically has a higher bus width than the first bus. For example, the second bus bandwidth may be 14 to 17 bits.

[0036] FIG. 2 depicts an equivalent circuit diagram of a passive infrared detector with a current source (I.sub.PIR) and a series circuit of parasitic detector capacitors (C.sub.PIR) and associated loss resistors R.sub.PIR.sub._.sub.c as well as the internal resistor of the backup current source R.sub.PIR. The current source's internal resistance (R.sub.PIR) lies parallel to the current source (I.sub.PIR), and is typically very high. An excessive load on the detectors will, therefore, cause the output voltage to collapse.

[0037] FIG. 3 illustrates a singled sided version of the -converter () of FIG. 1. A first controlled current source (I.sub.1), (also depicted as an additional current source) is controlled by a feedback path that stores current into the first node (Sb). A second controlled current source (I.sub.2), (also depicted as a current source) is controlled by an output of the passive infrared detector and also stores current into the first node (S.sub.b). The combined current received from the current sources either charges or discharges the capacitor (C.sub.1b). If the control loop is stable, the second current source (I.sub.2), delivers a current opposite in sign (polarity) and equal in magnitude to the first current source (I.sub.1). The comparator is linked via its input to the capacitor (C.sub.1b) and compares the voltage of this capacitor and thereby the first node (S.sub.b) to an internal reference value. As described above (see paragraph 28), the digital integrator (Int.sub.b) may be realized as an up/down counter. As in this example, the digital integrator (Int.sub.b), realized as an up/down counter, counts with each system clock either upwards or downwards, if the input to the comparator (CP.sub.b) is over or under the comparator' s (CP.sub.b) switching threshold. Six bits of the up/down counter, for example, may be used, to provide feedback. The six bits, as in this example, are converted by a digital-to-analog-converter into an analog signal that controls the other current source (I.sub.1).

[0038] A digital filter (DF) filters the counter values obtained from the digital integrator (Int.sub.b), realized as an up/down counter, to the output signal (Out), which is the output bus of the digital filter (DF).

[0039] FIG. 4 also illustrates a single-sided version of the -converter () of FIG. 1. However, instead of a controlled current source being the source for the reference signal, it is constructed so that the counter value (Val) of the digital integrator (Int.sub.b), realized as an up-down counter, selects a tap (IN.sub.FB), into the resistor cascade (R.sub.FB) made of individual resistors (not shown). As an example, the counter value (VAL) may be a six bit digital value. This tap can be input to a differential-transconductance-amplifier (CS) that has a current output. The current outputs respectively charge and discharge the capacitors (C.sub.1, C.sub.2). The resulting voltages at the capacitors (C.sub.1, C.sub.2) are compared via a comparator to each other, which, in turn, controls the up/down counter.

[0040] FIG. 5 illustrates a controllable current divider as part of a differential stage consisting of a resistor chain of n resistors R.sub.M1 to R.sub.Mn, that is typically but not necessarily identically carried out. In this example, the n+1 resistor chain taps are connected via an analog multiplexer (MUX) to a bias current source (I.sub.ref),

[0041] The bus width of the counter value (Val) of the analog multiplexer (Mux) selected here must be sufficient and typically higher than the logarithm of n to the basis 2. The current divider, the current source and the transistors (T.sub.1, T.sub.2) form a differential stage of the measurement circuit.

[0042] FIG. 6 illustrates the differential stage in FIG. 5 with two operating point resistors (R.sub.T,1, R.sub.T,2). It can be seen that the current divider resistors (R.sub.Ml to R.sub.Mn) will result in a different feedback for the two branches of the differential amplifier. This differing current feedback is set by the counter value (Val). In this example two exemplary outputs are depicted.

[0043] FIG. 7 illustrates the differential stage in FIG. 6 as part of a circuit configuration according to FIG. 3. Instead of the load resistors (R.sub.L1, R.sub.L2) in FIG. 6, a respective first and second integrating circuit (Inta.sub.1, Inta.sub.2) is inserted from nodes I.sub.a1b and I.sub.a2b to ground, in parallel to the load resistors (R.sub.1, R.sub.2). As used herein, the term integrating circuit can include one or more capacitors (e.g., one of the capacitors C1, C2) and/or one or more integrating filters connected in parallel. The passive infrared detectors are connected to the outputs as in FIGS. 1 and 2. The terminals IN and IP of the passive infrared sensor (PIR) are connected as in FIGS. 1 and 2.

[0044] FIG. 8 corresponds to FIG. 7 with the difference that the resistors (R.sub.1, R.sub.2) are now replaced with real current sources (I.sub.W1, I.sub.W2). The advantage of this configuration is that it demonstrates an increase in the differential resistance. In implementing such an integrated semiconductor circuit, this design represents a robust solution against parametric variations.

[0045] Advantageously, the design is very simple and therefore requires very little power whereby; it also simultaneously demonstrates a very high input resistance. Further, since the source connections are connected, through negative feedback, via the current divider to their respective gate voltages (in the middle) the gate-source-voltage will not fluctuate. Therefore, the complex input impedances are very high. The gate-source-capacitors do not need to be substantially charged or discharged. The quantization noise of the -converter () becomes less with an increase in the number n of resistors R.sub.Mi.

[0046] FIG. 9 illustrates a possible implementation of a discharge circuit R.sub.G in FIG. 1 as an alternative to the discharge resistors (R.sub.dis.sub._.sub.1, R.sub.dis.sub._.sub.2) in FIG. 1. These resistors must have a relatively high resistance value and should typically have, as nearly as reasonably possible, the same value. The implemented switch-capacitor-implementation, as shown in FIG. 8, works with transfer gates that can alternatively be switched by using one of the two non-overlapping clocks (.sub.1, .sub.2). Irrespective of the non-overlapping characteristic, one clock operates inversely to that of the other clock. Each of the storage capacitors carries in each phase with it a certain amount of charge and transports the charge at each half cycle a node further.

[0047] The figure shows two strands. The two strands are respectively offset and driven each half cycle. The strands are respectively operated in delayed half cycle intervals, resulting in continuous charge dissipation. During the measurement phase, the clocks are stopped, and no power will flow. The thus formed load resistance is at high impedance. If the discharging cycle is selected dependent on the input voltage, the discharge can then, for example, be controlled in such a way that it is by high input voltage differences higher and by low input voltage differences lower and that it disappears in a given operating range.

[0048] FIG. 10 depicts a further example of a discharge circuit R.sub.G as an active circuit. The transistors T3 and T4 are directly switched dependent on the difference of the voltage input between IP and IN. The differential amplifier forms the difference on its OP and ON inputs and opens the transistors T3 and T4 in accordance with a pre-set function dependent on the differential amount. Due to the non-linear character of the transistors T3, T4, this results, in the case of a vanishing difference between the input voltages IP and IN, in a reduction to zero or nearly zero of the conductance values of the transistors T3 and T4.

[0049] FIG. 11 illustrates a further possible implementation of the discharge circuit R.sub.G. A first current source provides half of the current I to the MOS-Diode T9 and the other half of the current I to the MOS-Diode T14. The current in MOS-Diode T14 is reduced by T13. A second current source delivers a current, that typically carries 80% of the value of the current I of the first current source. Since the current of the T11 transistor mirrors the current of the MOS-Diode T12 and the current from the T13 transistor mirrors that of the same MOS-Diode T12, an offset current of typically 80% of current I is directed through T9 and T14. If the bias in the IN and IP inputs is unequal, this will lead to an unbalanced division of current through the differential stage from T5 and T6. This manifests itself, in such a way that additional current can flow through MOS Diodes T9 or T14 that then leads to the transistors T7 and T15 or T8 andT16 opening and thereby to discharging of the input node IP and IN.

[0050] FIG. 12 illustrates an example characteristic curve of the discharge circuit of FIG. 11. It can be achieved, through the suitable selection of the current mirror and the transistor relationship that the input resistor has a high impedance area A, in which the input resistance is practically only determined by the leakage current of the circuit, an area B which has a voltage regulation character, and an area C which demonstrates a very low input impedance. Both terminals are thus discharged through such an electrical circuit arrangement, which presents an equivalent resistance at an operating point in area A which is significantly greater than the equivalent resistance at an operating point in area B or C.

[0051] This makes it possible to operate a passive infrared detector in such a way that the electrical terminals are discharged through a current path, when the voltages are outside of a predetermined area A. According to this circuit, the discharge current depends on the difference in input voltage between the electrical terminals IP and IN. In the Area A, which is determined by dimensioning of component values, the discharge current reduces to the leakage current of the transistors. The discharge current increases with increasing the increasing voltage difference when the input voltage is outside of the area A. The input resistance RIN (IP-IN) depends on the differential voltage V (IP-IN) between the inputs IN and IP of the discharge circuit R.sub.G. The input resistance depicted here could be, in one case, a connection between the IP and IN terminals and/or, in a second case, a connection between IP or IN on one side and a reference potential, for example ground, on the other side. The behavior as shown in FIG. 12 should preferably be similar in each of these two cases.

REFERENCE LIST

[0052] A high impedance area of the input resistor
-converter
B area which has a voltage regulation character
C area which demonstrates a very low input impedance

C.SUB.1 .Capacitor

C.SUB.1b .Capacitor

C.SUB.2 .Capacitor

CP.SUB.b .Comparator

[0053] CPO Comparator output
CS Differential-transconductance-amplifier that has a current output
DAC Digital-to-analog-converter
DF digital filter
I.sub.1 first current source
I.sub.2 second current source
I.sub.a1b node
I.sub.a2b node
I.sub.W1 current source
I.sub.W2 current source
I.sub.PIR current source of the equivalent circuit diagram of a passive infrared detector
Iref bias current source
Int.sub.a1 integrating filter
Int.sub.a2 integrating filter
Int.sub.b digital integrator
IN input voltage
IP input voltage
MUX multiplexer
ON differential amplifier input
OP differential amplifier input
OUT output of the digital filter (DF)
PIR passive infrared detector
.sub.1 non overplapping clock
.sub.2 non overplapping clock
R.sub.1 resistor
R.sub.2 resistor
R.sub.dis.sub._.sub.1 discharge resistor
R.sub.dis.sub._.sub.2 discharge resistor
R.sub.G discharging circuit
R.sub.L1 operating point resistor
R.sub.L2 operating point resistor
R.sub.M1 current divider resistor
R.sub.M2 current divider resistor
R.sub.Mn current divider resistor
R.sub.PIR internal resistance of the current source of the equivalent circuit diagram of a passive infrared detector
R.sub.PIR.sub._.sub.C loss resistor of the equivalent circuit diagram of a passive infrared detector
RIN input resistance
S.sub.b First node
V (IP-IN) differential voltage between the inputs IN and IP of the discharge circuit R.sub.G
Val counter value