Clock recovery method and clock recovery arrangement for coherent polarization multiplex receivers

Abstract

Component signal values are derived from component signals and fed to at least one fixed equalizer which generates equalizer output signals. The signals are fed to phase error detectors generating phase error signals. The phase error signals are combined with further phase error signals derived by further error detectors receiving signal values from further equalizers and/or the component signal values directly from sample units.

Claims

1. Clock recovery method for coherent polarization multiplex receivers, comprising the steps of coherent demodulating a received polarization multiplex signal and deriving orthogonal signal components, sampling and converting the orthogonal signal components into digital component values, feeding said digital component values to a same equalizer, said equalizer being configured to effectively reverse the effect of polarization mixing of the received orthogonal signals for one specific polarization mixing angle, deriving a phase error value from output values of said equalizer and another phase error value from the digital component values, calculating resulting phase error values from at least two of the derived phase error values, deriving an oscillator control signal from said resulting phase error values, and controlling at least one controllable oscillator to generate a sample signal for sampling said orthogonal signal components or re-sample the digital component values.

2. Clock recovery method according to claim 1, wherein said resulting phase error values are calculated by combining phase error values directly derived from the digital component values with phase error values derived from the equalizer output values.

3. Clock recovery method according to claim 1, further comprising: generating different resulting phase error values for two separate clock recovery loops, and generating two sample signals, each for sampling the orthogonal signal components or re-sampling the digital component values.

4. Clock recovery method according to claim 1, comprising the step of generating phase error values according to
X.sub.PE1[n]=XI.sub.Ei[n](XI.sub.Ei[n]XI.sub.Ei[n1])+XQ.sub.Ei[n](XQ.sub.Ei[n]XQ.sub.Ei[n1]),Y.sub.PE1[n]=YI.sub.Ei[n](YI.sub.Ei[n]YI.sub.Ei[n1])+YQ.sub.Ei[n](YQ.sub.Ei[n]YQ.sub.Ei[n1]) wherein XI.sub.Ei, XQ.sub.Ei; YI.sub.Ei, YQ.sub.Ei resemble equalizer output values or component signal values; n is an integer resembling a sample instant; and i=1, 2, . . . , N.

5. Clock recovery arrangement for a coherent polarization multiplex receiver with at least one phase locked loop deriving a sample signal, including a phase error detector unit receiving sampled component values, a loop filter, and a controllable oscillator, comprising a fixed equalizer receiving sampled component values and outputting equalizer output values, said equalizer being configured to effectively reverse the effect of polarization mixing of the received orthogonal signals for one specific polarization mixing angle, at least one phase error detector receiving equalizer output values and generating at least one phase error value, at least one phase error detector receiving sampled component values and generating at least one phase error value, and means for combining said phase error values to derive resultant phase error values for controlling at least one controllable oscillator of the at least one phase locked loop.

6. The clock recovery arrangement according to claim 5, comprising a first phase error detector unit generating a first control signal, a first phase locked loop receiving said first control signal and generating a first sample signal sampling x signal components, and a second phase error detector unit generating a second control signal, and a second phase locked loop receiving said second control signal and generating a second sample signal sampling y signal components.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Examples of the invention including an embodiment are described below with reference to accompanying drawings.

(2) FIG. 1 is a schematic diagram of a coherent polarisation multiplex receiver,

(3) FIG. 2 shows a normalized gain coefficient K.sub.i/K.sub.REF indicating the Gardner phase detector performance versus DGD (differential group delay) for several polarization mixing angles a as parameters,

(4) FIG. 3 is a simplified diagram of an inventive clock recovery arrangement,

(5) FIG. 4 is a block diagram of a combined phase error detector,

(6) FIG. 5 shows a simplified embodiment of the invention, and

(7) FIG. 6 shows the normalized gain coefficient K.sub.i/K.sub.REF of an inventive phase error detector versus DGD.

DETAILED DESCRIPTION OF THE INVENTION

(8) FIG. 3 shows a simplified diagram of a presently preferred clock recovery arrangement according to the invention. The analogue signal components xi, xq and yi, yq output by the 90-hybrids (FIG. 1) are fed to analogue-digital converters 20, 21 of a first sample unit 15 and 24, 25 of a second sample unit 16.

(9) Sequences of the sampled component values XI, XQ and YI, YQ, (time variable [n] is here usually omitted) representing the signal components xi, xq, yi, yq, are fed to a combined phase error detector unit 17 to determine resulting phase error values X.sub.WPE, X.sub.RPE which are fed via a loop filter 18 as control signal CSwhere required after digital-analogue conversion to a controlled oscillator 19 (CO; numerical controlled or in the analogue domain voltage controlled) of a phase locked loop (PLL). The controlled oscillator 19 supplies the sampling units 15, 16 with a common clock signal CL or with separate clock signals. The clock signals may be adapted e.g. to different internal delay times.

(10) The inventive clock recovery can be used both with synchronous for analogue-digital embodiments and asynchronous sampling for full digital realisation. The sample frequency of the clock signal CL is a multiple of the symbol frequency for synchronous sampling, or slightly higher or lower if asynchronous sampling is used. In the case of asynchronous sampling the sampled values are re-sampled by interpolators 23, 24 and 26, 27 as known to those skilled in the art.

(11) In contrast to traditional clock recovery loops (PLLs) where the phase error information is a scalar quantity extracted by a single phase error detector (possibly per polarization), the invention uses the combined phase error detector unit 17 for extracting the phase error signal from a plurality of linearly combined signal components.

(12) The combined phase error detector unit 17 shown in FIG. 4 comprises a set of N static equalizers EQU.sub.i with associated phase error detectors PED.sub.i. The component values XI, XQ and YI, YQ are fed parallel to all equalizers, each being optimized for a specific polarization mixing condition (polarisation mixing angle ). According to a known butterfly structure (MIMOmultiple inmultiple out) an optimized equalizer can reconstruct the transmitted orthogonal signals, in the shown embodiment represented by digital equalizer component values X.sub.Ei. The transfer functions of these equalizers are fixed, but chosen in such a way that, under any polarisation mixing angle , at least one of them will effectively reverse the linear combination of the received orthogonal optical signals due to the polarisation mixing angle a, thus separating them. At least one of the output equalizer component values X.sub.Ei (X.sub.Ei=XI.sub.EiXQ.sub.Ei, YI.sub.Ei, or YQ.sub.Einot shown in FIG. 4) of each equalizer EQU.sub.i is fed to one of N phase error detectors PED.sub.i as well as to N gain coefficient estimators PCE.sub.i (PCEderived from chase detector gain coefficients estimator).

(13) One of the equalizers may pass through at least one of the input component values, e.g. equalizer EQU.sub.1 passes through component values XI, which are fed to a first phase error detector PED.sub.1 instead of a modified equalizer output signal. But this equalizer may compensate other signal distortions.

(14) The phase error detectors PED.sub.i output phase error values X.sub.PEi which are fed via multipliers M.sub.i to a first adder AD1, and the gain coefficient estimators PCEi output gain coefficients K.sub.i which are fed via squaring circuits Q.sub.i to a further adder AD3. The output of the first adder AD1 is connected to a normalizing multiplier M.sub.NOR and the output of the further adder AD3 is connected via a division device DD to a further input of said normalizing multiplier.

(15) The purpose of the gain coefficient estimators PCE.sub.i is to estimate the gain coefficients K.sub.i of the associated phase error signals X.sub.PEi serving as weights favouring those phase error signals with the strongest phase information. Therefore, the phase error values X.sub.PEi=X.sub.PE1X.sub.PEN are multiplied by said associated gain coefficients K.sub.i=K.sub.1K.sub.N derive weighted phase error signals X.sub.WPi; that is
X.sub.WPEi[n]=K.sub.i*X.sub.PE1[n]
i=1, 2, . . . , N; nsample instant.

(16) A sum of the weighted phase errors X.sub.WPEi output from the multipliers M.sub.i, is then computed by the adder AD1 as resultant weighted phase error value X.sub.WPE:
X.sub.WPE[n]=X.sub.WPEi[n]
i=1, 2, . . . , N; summation i=1, 2, . . . , N.

(17) In a basic clock recovery implementation, the derived resultant weighted phase error values X.sub.WPE could be used as an input to the loop filter of the phase locked loop.

(18) In a more advanced embodiment, the resulting phase error values X.sub.WPE become virtually independent of the input signal distortions by dividing them by a sum of squares of the individual gain coefficients K.sub.i summed up by the further adder AD3. Further, a scaling factor K.sub.SET can be imposed on the resultant weighted phase error values X.sub.WPE to achieve a resultant phase error values X.sub.RPE, computing:
X.sub.RPE[n]=X.sub.WPE[n]*K.sub.SET/(K.sub.i.sup.2)

(19) In the shown embodiment the calculation of is executed by the division device DD. Multiplication with 1/Ki.sup.2 and the scaling factor K.sub.SET is executed by the normalizing multiplier M.sub.NOR.

(20) The gain coefficient estimators PCE.sub.1-PCE.sub.N are the key for the preceding calculation, and hence for a robust clock recovery process. Therefore, a more detailed description of the gain coefficient estimation process will be given here. The gain coefficients K.sub.i are computed as follows:

(21) where X.sub.PEIi are in-phase and X.sub.PEQi are quadrature-phase error values computed from the output values X.sub.Ei of the various equalizers EQU.sub.i. The in-phase phase error values are obtained by using the Gardner's formula as follows:

(22) $\begin{array}{cc}{X}_{\mathrm{PEIi}}\left[n\right]=\left(X_{\mathrm{Ei}}\left[n\right]-X_{\mathrm{Ei}}\left[n-1\right]\right).Math.X_{\mathrm{Ei}}\left[n-\frac{1}{2}\right]& \left(5\right)\end{array}$

(23) Where X.sub.Ei is at least one out of four signal components (XI.sub.Ei, XQ.sub.Ei YI.sub.Ei, YQ.sub.Eionly the outputs are shown in FIG. 4) output from the i-th equalizer. The quadrature-phase error values are instead computed by using a newly derived quadrature Gardner's formula as follows:

(24) $\begin{array}{cc}{X}_{\mathrm{PEQi}}\left[n\right]=\frac{1}{2}\left(X_{\mathrm{Ei}}\left[n\right]+X_{\mathrm{Ei}}\left[n-\frac{1}{2}\right]-X_{\mathrm{Ei}}\left[n-1\right]-X_{\mathrm{Ei}}\left[n-\frac{3}{2}\right]\right).Math.\left(X_{\mathrm{Ei}}\left[n-\frac{1}{2}\right]+X_{\mathrm{Ei}}\left[n-1\right]\right)& \left(6\right)\end{array}$

(25) Both signals X.sub.PEIi[n] and X.sub.PEQi[n] derived from equalizer output signals X.sub.Ei[n], are functions of the phase error and feature horizontal sinusoidal s-curves. Because they are in quadrature (like sine and cosine function), nearly phase-error-independent gain coefficients K.sub.i are obtained when they are root mean squared according to equation (4). Their amplitudes are functions of distortions and indicate the performances of the equalizers and are functions of the remaining distortions, mainly of DGD/T and effects.

(26) To summarize, the derived gain coefficients K.sub.i are almost independent of phase errors of the equalizers' output signals X.sub.Ei and indicate the quality of the phase information. The gain coefficients are used to calculate the resultant phase error values X.sub.RPE according to equation (3) which are almost independent of the distortions DGD/T and of the component signals x and y.

(27) Other arrangements and mathematical calculation leading to a similar stable resulting phase error signal and therefore to a stable control signal, which is almost independent of the distortion present in the input signals or the component signals respectively, might also be used. The arrangement may be upgraded by using both component values XI, XQ or YI, YQ for a complete Gardner phase error detector or even all component values. This is not shown in FIG. 4 and not outlined in the formulas for clarity reasons. Two different PLLs may also be used for sampling the signal components xi, xq and yi, yq separately. Two resulting phase error values for the two PLLs are then generated separately by two different sets of phase detectors with allocated gain coefficient estimators.

(28) FIG. 5 shows a further simplified low cost embodiment of a clock recovery comprising two PLLs. The figure shows a simplified illustration of two sample units 15 and 16. A first and a second PLL are controlled by separate (Gardner) phase detector units 31 and 32.

(29) The first phase detector unit 31 controls via the loop filter 18 the controllable oscillator (CO) 19 generating a first sample signal CL1 The second phase detector unit 32 controls via a second loop filter 32 a second CO 29 generating a second sample signal CL2. The x signal components xi, xq are sampled by the first sample signal CL1 and the y component signals yi, yq are sampled by second sample signal. The sampled XI and XQ component values are fed to a first phase error detector PD1, and the YI and YQ component values are fed to a second phase error detector PD2.

(30) The first and second phase error detectors PD1 and PD2 generates phase error signals according to
X.sub.PE1[n]=XI[n](XI[n]XI[n1])+XQ[n](XQ[n]XQ[n1])(7); and
Y.sub.PE2[n]=YI[n](YI[n]YI[n1])+YQ[n](YQ[n]YQ[n1])(8)

(31) A single fix equalizer 30 is used to generate two pairs of component values XI.sub.E, XQ.sub.E and YI.sub.E, YQ.sub.E rotated by 45 and fed to the additional phase detectors PD3 and PD4 respectively. The further phase error detectors PD3, PD4 generate appropri-ate phase error values X.sub.PE3, Y.sub.PE4 according to their input va-lues XI.sub.E, XQ.sub.E and YI.sub.E, YQ.sub.E, XQ.sub.E respectively.

(32) Both phase error values X.sub.PEI, X.sub.PE3 from the first and third phase error detector are fed to a first adder AD1 and combined to a first resulting phase error values X.sub.PE.

(33) Second resulting phase error values Y.sub.PE controlling the second loop are generated by the second phase error detector PD2 receiving the YI and YQ component values and by the fourth phase error detector PD4 receiving the component values XIE and XQ.sub.E from further equalizer outputs. Both phase error values Y.sub.PE2 and Y.sub.PE4 are added by the second adder AD2.

(34) FIG. 6 shows the normalized gain coefficient K/K.sub.REF for the embodiment shown in FIG. 5 employing only one equalizer and trivial weighting of the phase detector outputs by the gain coefficients 1.0. As can be readily seen, the fluctuations of K/K.sub.REF versus DGD are relatively small. Moreover, K/K.sub.REF does not approach zero for any combination of DGD and including the worst case represented by a=45 degree and DGD=T/2.

(35) A second equalizer or further equalizers would improve the 25 performance significantly.

(36) In addition, all static equalizers can be adjusted to compensate different distortions in order to achieve optimum performance.

(37) The present invention is not limited to the details of the above described principles. The scope of the invention is defined by the appended claims and all changes and modifications as fall within the equivalents of the scope of the claims are therefore to be embraced by the invention. Mathematical conversions or equivalent calculations of the signal values based on the inventive method or the use of analogue signals instead of digital values are also incorporated.

REFERENCE SIGNS

(38) 1 polarisation beam splitter 2 x-90-hybrid 3 y-90-hybrid 4 local oscillator 9 dispersion compensation unit 10 clock recovery unit 11 butterfly filter 12 carrier recovery unit 13 decoder 14 parallel-serial-converter PMS polarization multiplex signal SDS serial digital signal 15 x-sample unit 16 y-sample unit 17 combined phase error detector unit 18 loop filter 19 controlled oscillator (CO) 20, 21 analogue-digital-converter 22, 23 interpolator 24, 25 analogue-digital-converter 26, 27 interpolator xi, xq; yi, yq signal components CL, CL1, CL2 sample signal xi in-phase x component xq quadrature-phase x component yi in-phase y component yq quadrature y component XI X in-phase component value XQ X quadrature-phase component value YI Y in-phase component value YQ Y quadrature-phase component value EQU equalizer PED phase error detector PCE gain coefficient estimator Q squaring circuits M multiplier DD division device X.sub.Ei equalizer output values X.sub.ETi phase error values X.sub.PEIi in-phase error values X.sub.PEOi quadrature-phase error values X.sub.WPEI weighted phase error values X.sub.WPE resultant phase error values, X.sub.RPE resultant phase error values X.sub.PE resultant x phase error value Y.sub.PE resultant y phase error value M.sub.NOR normalizing multiplier AD1 first adder AD3 further adder AD2 second adder n sample instant K gain coefficient K.sub.REF reference gain coefficient 28 second loop filter 29 second controlled oscillator (CO) 30 equalizer 31 first phase error detector unit 32 second phase error detector unit PD1-PD4 phase detector A1, A2 adder XI.sub.E equalizer x in-phase component output values XQ.sub.E equalizer x quadrature component output values YI.sub.E equalizer y in-phase component output values YQ.sub.E equalizer y quadrature component output values X.sub.PE x phase error values Y.sub.PE, y phase error values